TRANSCONDUCTANCE AMPLIFIER HAVING LOW DISTORTION

Abstract

A low distortion transconductance amplifier provides current to a grounded load using a virtual ground input stage, a pair of current mirrors, and a bias current source. The virtual ground input stage may include transistors arranged as a Darlington pair. The low distortion transconductance amplifier can function as a voltage-controlled AC current source that is operable at high frequencies.

Claims

1. A circuit, comprising: a voltage source; a reference resistor coupled to the voltage source; an input stage including an operational amplifier coupled to the reference resistor; a transistor coupled to be driven by the operational amplifier; and a bias current source coupled to the transistor and the operational amplifier; an output stage including a grounded load resistor; and a pair of current mirrors, each current mirror coupling the input stage to the output stage.

2. The circuit of claim 1 wherein one or more of the current mirrors further includes first and second arrays of bipolar junction transistors.

3. The circuit of claim 2 wherein a current supplied to the output stage is equal to a difference in bias currents of the first and second arrays of the current mirror.

4. The circuit of claim 1, wherein the transistor is a first transistor and further comprises a second transistor arranged with the first transistor as a Darlington pair connecting the input stage to the pair of current mirrors.

5. The circuit of claim 4 wherein the transistors arranged as a Darlington pair collectively have unity gain.

6. The circuit of claim 1 wherein a positive terminal of the operational amplifier is grounded and the operational amplifier is configured to provide a virtual ground at a negative input terminal of the operational amplifier.

7. The circuit of claim 1 wherein the voltage source is a first voltage source and input terminals of the operational amplifier are coupled directly to second and third voltage sources, respectively.

8. The circuit of claim 1 wherein the transistor coupled to be driven by the operational amplifier is a bipolar junction transistor.

9. The circuit of claim 1 wherein the transistor coupled to be driven by the operational amplifier is a field effect transistor.

10. The circuit of claim 1 wherein the input stage is a pull input stage that pulls current into the load resistor.

11. The circuit of claim 1 wherein the pair of current mirrors is a pair of current attenuation mirrors.

12. The circuit of claim 1 wherein the pair of current mirrors is a pair of current gain mirrors.

13. The circuit of claim 1 wherein the circuit includes a linear transconductance amplifier.

14. A method of operating a circuit comprising: creating an input current source by coupling an input voltage source to a reference resistor; coupling the current source to a virtual ground; coupling a bias resistor to the virtual ground; coupling the virtual ground to a current mirror that provides a bias current via the bias resistor; supplying the bias current to a load resistor; and controlling the bias current by modulating the input current source.

15. The method of claim 14 wherein the virtual ground is established by an operational amplifier.

16. The method of claim 14 wherein the current mirror includes first and second arrays of bipolar junction transistors.

17. A circuit, comprising: a current source; a transconductance amplifier coupled to the current source, the transconductance amplifier having a virtual ground input stage; and an output stage coupled to the transconductance amplifier, the output stage having a grounded load.

18. The circuit of claim 17, further comprising a pair of current mirrors coupled between the virtual ground input stage and the output stage.

19. The circuit of claim 17 wherein the virtual ground input stage includes two bipolar junction transistors arranged as a Darlington pair.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0008] FIG. 1 is a high level schematic of a basic transconductance amplifier circuit, according to the prior art.

[0009] FIG. 2 is a schematic of a transconductance amplifier circuit according to the prior art.

[0010] FIG. 3 is a schematic of a transconductance amplifier circuit that includes a current mirror and a virtual ground input stage, according to the prior art.

[0011] FIG. 4 is a circuit schematic of a virtual ground input stage suitable for use in a transconductance amplifier, according to an embodiment as described herein.

[0012] FIG. 5 is a high level schematic of a transconductance amplifier circuit that includes two current mirrors and a virtual ground input stage, according to an embodiment as described herein.

[0013] FIG. 6 is a schematic of a transconductance amplifier circuit implemented with a Darlington pair, according to an embodiment as described herein.

[0014] FIG. 7 is a detailed schematic of the transconductance amplifier circuit shown in FIG. 6.

[0015] FIG. 8 is a schematic of a transconductance amplifier circuit implemented with a field effect transistor, according to an embodiment as described herein.

[0016] FIG. 9 is a schematic of a transconductance amplifier circuit implemented with a pull input stage, according to an embodiment as described herein.

[0017] FIG. 10 is a schematic of a transconductance amplifier circuit implemented with current gain or attenuation mirrors, according to an embodiment as described herein.

[0018] FIG. 11 is a schematic of a class B transconductance amplifier circuit, according to an embodiment as described herein.

[0019] FIG. 12 is a flow diagram illustrating a method of operating a transconductance amplifier circuit, according to an embodiment as described herein.

DETAILED DESCRIPTION

[0020] In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.

[0021] Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

[0022] Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases “In an embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

[0023] In the figures, identical reference numbers identify similar features or elements. The sizes and relative positions of the features in the figures are not necessarily drawn to scale. Furthermore, specific embodiments are described herein with reference to exemplary transconductance amplifier circuits. The present disclosure and the reference to certain materials, dimensions, and the details and ordering of method steps should not be limited to those shown.

[0024] FIG. 1 shows a known generic transconductance amplifier circuit 100. The transconductance amplifier circuit 100 includes an input stage 102, an output stage 104, and a transconductance amplifier 106. The transconductance amplifier circuit 100 can be thought of as a voltage-controlled current source that produces an output current I.sub.out in response to V.sub.in. The output stage 104 includes a load resistor R.sub.L, through which the output current I.sub.out flows to ground. The relationship between the input voltage and the output current is

I.sub.out=g.sub.mV.sub.in.

wherein g.sub.m is the gain of the transconductance amplifier 106. Embodiments described herein present various configurations for the transconductance amplifier 106.

[0025] FIG. 2 shows a known transconductance amplifier circuit 105. The transconductance amplifier circuit 105 includes the input stage 102 and the output stage 104 having a grounded load. In the transconductance amplifier circuit 105, the input stage 102 further includes an op-amp U1, an NPN bipolar junction transistor (BJT) Q0, and a precision reference resistor R.sub.ref. The NPN transistor Q0 has emitter, collector, and base terminals as is known in the art. The op-amp U1 has positive and negative input terminals and an output terminal, as is known in the art. In the transconductance amplifier circuit 105, V.sub.in is coupled directly to the positive terminal of U1, and R.sub.ref is coupled to the negative terminal of U1 at a node A. The output of U1 is coupled to the base of Q0. The emitter terminal of Q1 is coupled to node A. If the current gain of Q0 is large enough,

I.sub.out=−I.sub.ref=−V.sub.in/R.sub.ref.

[0026] The gain of the transconductance amplifier 106 is then

g.sub.m=−1/R.sub.ref.

[0027] Existing transconductance amplifiers capable of converting a single-ended input voltage to a single-ended ground-referenced output current typically use op-amp based voltage-to-current converters such as the one shown in FIG. 2. However, such amplifiers have limitations on the load R.sub.L. In practice, a grounded load is not possible due to input range and output range limitations illustrated by the following example. It is noted that V.sub.in must be positive for Q1 to be in forward active mode (V.sub.be≧0.7V and V.sub.ce≧0.2V). The restriction V.sub.in≧0 means I.sub.out≧0. Furthermore, V.sub.out=V.sub.in+C.sub.ce. Therefore, V.sub.out≧V.sub.in+0.2V, which requires that R.sub.L<0.

[0028] FIG. 3 shows a known transconductance amplifier circuit 107. The transconductance amplifier circuit 107 overcomes some limitations of the conventional transconductance amplifier circuit 105 of FIG. 2 by adding a current mirror 108 and a current source I.sub.b for delivering current to grounded loads. The bias current I.sub.b is coupled to a negative supply voltage V.sub.ee. In the transconductance amplifier circuit 107, the output stage 104 is grounded.

[0029] The current mirror 108 is coupled to a power supply V.sub.cc. When the transistor Q0 switches on, a current I.sub.ref at the input is “mirrored” at the output of the current mirror 108. That is, the current mirror 108 responds to an input current by delivering an equivalent output current. This means that whichever current exits the input terminal of the current mirror 108 also exits the output terminal of the current mirror 108. The current mirror 108 has the effect of pushing current into the load R.sub.L as opposed to pulling current from the load.

[0030] In the transconductance amplifier circuit 107, a transconductance amplifier 106a further includes the conventional op-amp stage 110a as shown in FIG. 2. The op-amp stage 110a includes the operational amplifier U1, the NPN transistor Q0, and the reference resistor R.sub.ref. The negative terminal of the op-amp U1 is coupled to ground via R.sub.ref. The output of U1 is coupled to the base terminal of Q0 and the emitter terminal of Q0 is coupled to the negative input of U1, such that I.sub.ref=V.sub.in/R.sub.ref. Adding the current source I.sub.b changes the transconductance gain relationship to be:

I.sub.out=−g.sub.mV.sub.in−I.sub.b.

The current source I.sub.b can be designed to ensure that the transconductance amplifier 107 delivers negative output current to an arbitrary load. This eliminates the limitation I.sub.out≧0. However, when I.sub.out=0, the input voltage is non-zero, i.e., a DC bias is applied: V.sub.in=I.sub.bR.sub.ref. The need for a DC bias at the input of a transconductance amplifier can be a disadvantage. First, additional circuitry is required to provide the DC bias at the input. Second, adding a DC bias voltage at the input of an amplifier reduces the amount of signal headroom in the direction of the DC bias. Third, operating an amplifier near a power rail (V.sub.cc or V.sub.ee) introduces distortion.

[0031] FIG. 4 shows a virtual ground input stage 110b suitable for use in a low distortion transconductance amplifier 106b, according to an embodiment of the present disclosure. The transconductance amplifier 106b, shown enclosed by a dotted line, includes the virtual ground input stage 110b and the bias current source I.sub.b. The virtual ground input stage 110b provides a current bias as a substitute for a DC bias voltage at the input stage, thus circumventing the problems described above that are associated with such a DC bias voltage. In the input stage 102, the voltage source V.sub.in is applied across a precision reference resistor R.sub.ref to produce an input current I.sub.in at an input node A. Instead of biasing Q1 using an input bias voltage, the current source I.sub.b is coupled to the emitter of Q1 and drives current through Q1. I.sub.b is desirably several times larger than the absolute value of the largest possible input current.

[0032] The virtual ground input stage 110b includes the op-amp U1 and a PNP transistor Q1. In a conventional op-amp implementation, an op-amp functions as a differential amplifier that boosts a voltage between the positive and negative input terminals by drawing energy from the power supply V.sub.cc. However, the op-amp U1 is not used as an amplifier in the virtual ground input stage 110b. Instead, the op-amp U1 is used to establish a virtual ground at input node A, below a bias resistor R.sub.B. Thus, U1 is coupled in a negative feedback configuration. It is noted that the bias resistor R.sub.B, not shown, sets the bias current to a desired value, and is represented in the Figures herein as an ideal current source instead of a resistor. Consequently, the output terminal of U1 will settle to whatever voltage is necessary to force the positive and negative inputs of U1 to be at substantially the same voltage, V.sub.in−I.sub.inR.sub.ref. The output voltage of U1 is variable, and adjusts itself so as to force the differential voltage between the input terminals of U1 to be substantially zero. Because the positive input of U1 is grounded, the negative input is also held at 0V, which effectively grounds the input node A. Because the negative terminal of U1 is electrically isolated from ground, it is referred to as a “virtual ground.” The bias current I.sub.b flows from the power supply V.sub.cc through the bias resistor R.sub.B. The output stage 104 is coupled to the negative power supply V.sub.ee. When Q1 is switched on, I.sub.out=I.sub.b+I.sub.in. The input current I.sub.in flows around U1 to the grounded node A and enters the emitter of Q1 where it is then delivered to the load R.sub.L. Use of the virtual ground input stage 110b will still require additional circuitry to deliver current to a grounded load. However, because an input current is used instead of a DC bias input voltage, the input stage has lower distortion and better noise performance. Additional zeroing circuitry is also not needed at the input. Furthermore, the virtual ground input stage 110b is able to handle input voltages of both positive and negative polarity.

[0033] FIG. 5 shows a low distortion transconductance amplifier circuit 115, according to an embodiment of the present disclosure. In the low distortion transconductance amplifier circuit 115, the transconductance amplifier 106c, shown enclosed by a dotted line, includes the virtual ground input stage 110b and two current mirrors 108a, 108b. By adding the current mirrors 108a, 108b to the circuit, the output current can be driven to a grounded load without the bias current I.sub.b being delivered to the load.

[0034] In the input stage 102, the voltage source V.sub.in is applied across the precision reference resistor R.sub.ref to produce the input current I.sub.in at the input node A. Also delivered to the input node A is the bias current I.sub.b drawn from the current mirror 108a. The current mirror 108a is coupled to the positive supply voltage V.sub.cc and the current mirror 108b is coupled to the negative supply voltage V.sub.ee. The virtual ground input stage 110b includes the op-amp U1 and the PNP transistor Q1. Establishing a virtual ground below R.sub.b draws current from V.sub.cc through the current mirror 108a. I.sub.out is then equal to the difference between the top and bottom bias currents at output node B:

I.sub.out=I.sub.b−(I.sub.b+I.sub.in)=−V.sub.in/R.sub.ref.

When the current through the top and bottom current mirrors is equal, I.sub.out=0. However, when the currents are not precisely mirrored, excess current is directed to the load R.sub.L. In the transconductance amplifier circuit 115, the output stage 104 is grounded.

[0035] FIG. 6 shows a low distortion transconductance amplifier circuit 121, according to an embodiment of the present disclosure. In the low distortion transconductance amplifier circuit 121, the transconductance amplifier 106d, shown enclosed by a dotted line, includes a virtual ground input stage 110c and the two current mirrors 108a, 108b. In the input stage 102, the voltage source V.sub.in is applied across the precision reference resistor R.sub.ref to generate a current source I.sub.in at the input node A. V.sub.in can be an AC or a DC source. Also delivered to the input node A is the bias current I.sub.b drawn from the current mirror 108a. The current mirror 108a is coupled to the positive supply voltage V.sub.cc and the current mirror 108b is coupled to the negative supply voltage V.sub.ee. The op-amp U1 drives the transistor Q2. In the transconductance amplifier circuit 121, the output stage 104 is grounded.

[0036] The right side of R.sub.ref is connected to the negative terminal of U1. The positive terminal of U1 is connected to ground. The output of U1 forces the negative terminal of U1 to be the same as the positive terminal, that is, a “virtual ground” is created at the negative terminal of U1 so that the differential voltage across the inputs to the op-amp U1 is zero. Thus, node A is grounded.

[0037] The virtual ground input stage 110c includes the op-amp U1 and a Darlington pair 122 of PNP transistors, Q1 and Q2. A bias current flows from V.sub.CC down through R.sub.b and into the Darlington pair, Q1 and Q2. In one embodiment, the Darlington pair has unity gain, i.e., no amplification. Therefore, in such embodiment, Q1 and Q2 could alternatively be replaced by a single transistor. Currents flowing out of the top current mirror 108a, I.sub.b, are equal. Likewise, currents flowing into the bottom current mirror 108b are also equal. In each one of Q1 and Q2, the arrow side is the emitter and the other side is the collector.

[0038] FIG. 7 shows the low distortion transconductance amplifier circuit 121 of FIG. 6 in greater detail. The input stage 102 includes the voltage source V.sub.in and the resistor R.sub.ref. The op-amp U1 is shown coupled between the power supplies V.sub.cc and V.sub.ee. The virtual ground input stage 110c may further include a voltage source V2 coupled between U1 and V.sub.cc, and a voltage source V3 coupled between U1 and V.sub.ee. The current mirrors 108a, 108b include bipolar junction transistors (BJTs) arranged in a lower transistor array corresponding to the current mirror 108b and an upper transistor array corresponding to the current mirror 108a. The current mirrors 108a, 108b are powered by voltage supplies V.sub.cc and V.sub.ee, respectively. The lower current mirror 108b includes four BJTs, Q3, Q4, Q5, and Q6. Each BJT is a three-terminal device having an emitter, a base, and a collector. Exemplary labels are provided on the terminals of Q6 in FIG. 7. The base and the collector of Q6 are coupled together by a short circuit connection S1. The base and the collector of Q3 are coupled together by a short circuit connection S2. The upper current mirror 108a includes four BJTs, Q7, Q8, Q9, and Q10. The base and the collector of Q7 are coupled together by a short circuit connection S3. The base and the collector of Q10 are coupled together by a short circuit connection S4. Conventional op-amp based current mirrors have low frequency poles whereas the BJT current mirrors shown in FIG. 7 have high frequency poles. Hence, through the use of BJTs, the bandwidth of the current mirrors 108a, 108b is shifted to higher frequencies.

[0039] FIG. 8 shows a low distortion transconductance amplifier circuit 123, according to an embodiment of the present disclosure. In the low distortion transconductance amplifier circuit 123, the transconductance amplifier 106e, shown enclosed by a dotted line, includes a virtual ground input stage 110d and the two current mirrors 108a, 108b. In the input stage 102, the voltage source V is applied across the precision reference resistor R.sub.ref to produce the input current I.sub.in at the input node A. The current mirror 108a is coupled to the positive supply voltage V.sub.cc and the current mirror 108b is coupled to the negative supply voltage V.sub.ee. The virtual ground input stage 110d includes the op-amp U1 and a p-type metal-oxide-semiconductor (PMOS) field effect transistor M1, which is a substantially equivalent substitute for the PNP bipolar junction transistor Q1. M1 is particularly suitable for use at lower operating voltages, as is customary in the art. Otherwise, the transconductance amplifier circuit 123 is similar to the transconductance amplifier circuit 115.

[0040] FIG. 9 shows a low distortion transconductance amplifier circuit 125, according to an embodiment of the present disclosure. In the low distortion transconductance amplifier circuit 125, the transconductance amplifier 106f, shown enclosed by a dotted line, includes a virtual ground input stage 110e and the two current mirrors 108a, 108b. In the input stage 102, the voltage source V.sub.in is applied across the precision reference resistor R.sub.ref to produce the input current I.sub.in at the input node A. The current mirror 108a is coupled to the positive supply voltage V.sub.cc and the current mirror 108b is coupled to the negative supply voltage V.sub.ee. The virtual ground input stage 110e includes the op-amp U1 and an NPN transistor Q2. The positive terminal of U1 is grounded and I.sub.in is coupled to the negative terminal of U1. However, the node A is below the transistor Q2 instead of above Q2. The input stage shown in FIG. 9 configured with the NPN transistor Q2 pulls current into the output stage 104 instead of pushing the current. Otherwise, the transconductance amplifier circuit 125 is similar to the transconductance amplifier circuit 115.

[0041] FIG. 10 shows a low distortion transconductance amplifier circuit 127, according to an embodiment of the present disclosure. In the low distortion transconductance amplifier circuit 127, the transconductance amplifier 106g, shown enclosed by a dotted line, includes the virtual ground input stage 110b and the two current mirrors 112a, 112b. In the input stage 102, the voltage source V.sub.in is applied across the precision reference resistor R.sub.ref to produce the input current I.sub.in at the input node A. The current mirror 112a is coupled to the positive supply voltage V.sub.cc and the current mirror 112b is coupled to the negative supply voltage V.sub.ee. The current mirrors 112a,b are current gain or current attenuation blocks that permit the signal level to be changed. The gain/attenuation blocks function in a similar way as the current mirrors 108, except that they output a current equal to a constant multiplied by the input current. I.sub.out/I.sub.in<1 for a current attenuation block, and I.sub.out/I.sub.in>1 for a current gain block. In contrast, the current mirrors 108a,b have an effective unity current gain. The virtual ground input stage 110b includes the op-amp U1 and the PNP transistor Q1 as in the transconductance amplifier circuit 115.

[0042] FIG. 11 shows a class B low distortion transconductance amplifier circuit 129, according to an embodiment. In the class B transconductance amplifier circuit 129, the transconductance amplifier 106h, shown enclosed by a dotted line, includes the two current mirrors 108a, 108b and a virtual ground input stage 110f. In the input stage 102, the voltage source V.sub.in is applied across the precision reference resistor R.sub.ref to produce the input current I.sub.in at the input node A. In at least one example, the reference resistor R.sub.ref has a value of 1 kΩ. The current mirror 108a is coupled to the positive supply voltage V.sub.cc and the current mirror 108b is coupled to the negative supply voltage V.sub.ee. The virtual ground input stage 110f includes the op-amp U1 and the PNP transistors Q1, Q2. However, unlike the Darlington pair embodiment shown in FIGS. 6 and 7, Q1 and Q2 are coupled in series and the base of each transistor is coupled to the collector. The bias current source I.sub.b is coupled to V.sub.cc and a second bias current source I.sub.b2 is coupled to V.sub.ee. In addition, transistors Q7 and Q8 are coupled to the current mirrors 108a, 108b respectively. In other embodiments, the low distortion transconductance amplifier circuit 129 can feature a linear transconductance amplifier as a class A, class B, or a hybrid class AB amplifier.

[0043] FIG. 12 shows steps in a method 150 of operating the low distortion transconductance circuits described above, according to an embodiment of the present disclosure.

[0044] At 152, an input current source is created from an input voltage source V.sub.in and a reference resistor R.sub.ref.

[0045] At 154, the input current source is coupled to a virtual ground.

[0046] At 156, a bias resistor is coupled to the virtual ground,

[0047] At 158, the virtual ground is coupled to a current mirror to provide a bias current source I.sub.b.

[0048] At 160, the bias current I.sub.b is supplied to the load resistor R.sub.L.

[0049] At 162, the input current source I.sub.in is modulated to control the bias current I.sub.b.

[0050] It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of various other patents, patent applications and publications to provide yet further embodiments.

[0051] These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.