Three-dimensional stacked phase change memory and preparation method thereof

Abstract

The disclosure belongs to the technical field of microelectronic devices and memories, and discloses a three-dimensional stacked phase change memory and a preparation method thereof. The preparation method includes: preparing a multilayer structure in which horizontal electrode layers and insulating layers are alternately stacked, then performing etching to form trenches and separated three-dimensional strip electrodes, next filling the trenches with an insulating medium, and then forming small holes at the boundary region between the three-dimensional strip electrodes and the insulating medium, thereafter sequentially depositing a phase change material on the walls of the small holes, and filling the small holes with an electrode material to prepare vertical electrodes, so as to obtain a three-dimensional stacked phase change memory stacked in multiple layers. By improving the overall process of the preparation method, the disclosure realizes the establishment of a three-dimensional phase change memory array by using a vertical electrode structure.

Claims

1. A method for preparing a three-dimensional stacked phase change memory, comprising the following steps: (S1) preparing a substrate, using an upper surface of the substrate as a base surface, depositing an entire layer of an electrode material on the substrate as a first horizontal electrode layer, and then preparing a first insulating layer on the first horizontal electrode layer, wherein a projection of the first insulating layer on a plane where a substrate surface is located is within a projection of the first horizontal electrode layer, at least along a linear direction in the plane where the substrate surface is located, a projection length of the first insulating layer is smaller than a projection length of the first horizontal electrode layer, so that the first horizontal electrode layer exposes pins and is not completely covered by the first insulating layer, thereby forming the first horizontal electrode layer and the first insulating layer provided to match the first horizontal electrode layer; (S2) using an uppermost insulating layer as the base surface, repeat the operations of depositing the electrode material and preparing the insulating layer, thereby forming a three-dimensional stacked structure composed of a total of i horizontal electrode layers and a total of i insulating layers provided to match each of the horizontal electrode layers respectively, wherein the three-dimensional stacked structure is a multilayer structure; wherein, i is a positive integer≥2; (S3) etching the multilayer structure to partially expose the substrate and produce trenches, thereby obtaining several three-dimensional strip electrodes that are separated from each other and arranged in strips, wherein any one of the three-dimensional strip electrodes comprises i horizontal electrode layers and i insulating layers, and one of the trenches is provided between any two adjacent three-dimensional strip electrodes; (S4) filling the trenches with an insulating medium to achieve electrical and thermal isolation in a horizontal direction; (S5) using projection lines of interfaces between the three-dimensional strip electrodes and the insulating medium on the plane where the substrate surface is located as a reference, etching a region at a boundary between the three-dimensional strip electrodes and the insulating medium, thereby obtaining a number of small holes separated from each other, wherein a bottom of any one of the small holes is located below the upper surface of the substrate, and a projection center point of each of the small holes on the plane where the substrate surface is located is on the projection lines; (S6) depositing a phase change material on hole walls of the small holes obtained in the step (S5) and making the phase change material cover the bottoms of the small holes, and then filling an electrode material in regions of the small holes surrounded by the phase change material to prepare vertical electrodes, thereby obtaining a three-dimensional stacked phase change memory stacked in multiple layers.

2. The method for preparing the three-dimensional stacked phase change memory according to claim 1, wherein in the step (S3), a width of each of the three-dimensional strip electrodes is equal to each other, a width of each of the trenches is equal to each other, and the width of any one of the trenches is equal to the width of any one of the three-dimensional strip electrodes.

3. The method for preparing the three-dimensional stacked phase change memory according to claim 1, wherein in the step (S5), N small holes that are evenly distributed with each other are correspondingly etched on any one of the interfaces between the three-dimensional strip electrodes and the insulating medium, and for any two of the interfaces, a one to one correspondence is between positions of the small holes on one interface and positions of the small holes on another interface, a connection line of the projection center points of the small holes at the same corresponding position on the plane where the substrate surface is located is perpendicular to the projection lines of the interfaces on the plane where the substrate surface is located.

4. The method for preparing the three-dimensional stacked phase change memory according to claim 3, wherein a total number of the three-dimensional strip electrodes obtained in the step (S3) is M, and a total number of the small holes is 2×(M−1)×N.

5. The method for preparing the three-dimensional stacked phase change memory according to claim 1, wherein in the step (S6), the deposited phase change material has a self-selection effect.

6. The method for preparing the three-dimensional stacked phase change memory according to claim 1, wherein an electrode material adopted in the horizontal electrode layer and an electrode material adopted in the vertical electrode are both low work function conductive materials with a work function lower than that of the phase change material, the electrode material adopted in the horizontal electrode layer and the electrode material adopted in the vertical electrode include one or more materials below: the following low work function conductive materials Cr, Ag, Al, Ti, W, Ni, Mo, Fe, oxide conductive materials thereof, nitride conductive materials thereof, and N-type silicon.

7. The method for preparing the three-dimensional stacked phase change memory according to claim 1, wherein in the step (S6), the deposited phase change material is any one selected from GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, GeSbTe and AglnSbTe, or a mixture formed by doping any one of the above compounds with elements S, C, N, 0, Cu, Si, As, B, Al, or Au, or a superlattice structure formed by any several compounds selected from the above compounds.

8. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 1.

9. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 2.

10. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 3.

11. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 4.

12. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 5.

13. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 6.

14. A three-dimensional stacked phase change memory prepared by using the method for preparing the three-dimensional stacked phase change memory according to claim 7.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 to FIG. 6 are schematic cross-sectional views of the preparation process flow of the two-layer stack in the three-dimensional stacked phase change memory along a direction perpendicular to the horizontal electrode direction in an embodiment of the disclosure.

(2) FIG. 1 is a schematic view of sequentially depositing electrodes and insulating layers on a substrate.

(3) FIG. 2 is a schematic view of forming trenches by etching on a multilayer electrode structure.

(4) FIG. 3 is a schematic view of filling an insulating medium in a trench formed by etching for electrical and thermal insulation in the horizontal direction.

(5) FIG. 4 is a schematic view of forming small holes by etching at the boundary between the electrodes and the insulating medium.

(6) FIG. 5 is a schematic view of depositing a phase change material in the small holes to form a phase change functional layer.

(7) FIG. 6 is a schematic view of filling an electrode material in the small holes to form vertical electrodes.

(8) FIG. 7 is a top view after filling the vertical electrodes.

(9) The denotation of the reference signs in the figures are as follows: 1 denotes substrate (such as a single crystal silicon substrate with a SiO.sub.2 insulating layer on its surface), 2 denotes first electrode layer, 3 denotes first insulating layer, 4 denotes second electrode layer, 5 denotes second insulating layer, 6 denotes electric and thermal insulating layer, 7 denotes phase change functional layer, and 8 denotes vertical electrode.

DESCRIPTION OF EMBODIMENTS

(10) In order to make the objectives, technical solutions, and advantages of the present disclosure more comprehensible, the present disclosure are further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present disclosure, but not to limit the present disclosure. In addition, the technical features involved in the various embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other.

(11) As shown in FIG. 1 to FIG. 6, the disclosure provides a method for preparing a three-dimensional stacked phase change memory, which specifically includes the following steps.

(12) (1) An entire layer of an electrode material is prepared on the substrate as the first horizontal electrode.

(13) (2) A first insulating layer slightly smaller than the first horizontal electrode in a certain direction (such as the length direction or the width direction of the square substrate) is prepared on the entire layer of the first horizontal electrode.

(14) (3) An entire layer of a second horizontal electrode is prepared on the first insulating layer.

(15) (4) On the above structure, an insulating layer slightly smaller than the second horizontal electrode in a certain direction is prepared. For example, a second insulating layer smaller than the second horizontal electrode in the same direction as the first insulating layer is prepared.

(16) (5) If more layers are to be stacked, the above steps are repeated. For example, the steps (1) to (4) are repeated several times in sequence to form multilayer horizontal electrodes.

(17) (6) Etching is performed until reaching the substrate. For example, the multilayer electrodes may be etched regularly to penetrate through the substrate surface, so that the multilayer electrodes are arranged in regular strips, wherein the trenches have the same width as the strip multilayer electrodes.

(18) (7) The trenches produced by etching are filled with an insulating medium for electrical and thermal insulation in the horizontal direction.

(19) (8) Small holes are formed by etching at the boundary between the multilayer electrodes and the insulating medium until reaching the substrate. For example, small holes in regular arrangement may be obtained by etching with the points on the boundary line between the strip multilayer electrodes and the insulating medium as the center, the bottom of the small holes is below the substrate surface.

(20) (9) A phase change material is deposited on the hole walls until reaching the bottom of the small holes.

(21) (10) An electrode material is filled in small holes of the phase change material to prepare a vertical electrode, so as to obtain a phase change memory with a multilayer vertical structure.

(22) The following takes a two-layer stacked memory as an example to describe the disclosure in detail.

Embodiment 1

(23) This embodiment includes the following steps.

(24) Step 1: On the single crystal silicon substrate 1 with a SiO.sub.2 insulating layer on its surface, 100 nm of Al is deposited as the first electrode layer 2 through an electron beam evaporation process.

(25) Step 2: On the basis of Step 1, PECVD is performed to deposit 100 nm of SiO.sub.2 as the first insulating layer 3 and the first electrode pin layer is exposed.

(26) Step 3: On the basis of Step 2, 100 nm of Al is deposited as the second electrode layer 4 through electron beam evaporation, which is located on the first insulating layer.

(27) Step 4: On the basis of Step 3, PECVD is performed to grow 100 nm of SiO.sub.2 as the second insulating layer 5 and the second electrode pin layer is exposed (as shown in FIG. 1; FIG. 1 does not show the exposed pins. For details on the exposed pins, please refer to FIG. 7).

(28) Step 5: The ICP etching equipment is utilized to regularly etch the multilayer electrode structure until reaching the substrate to form strip multilayer electrode structures regularly arranged, as shown in FIG. 2.

(29) Step 6: On the basis of Step 5, the insulating medium SiO.sub.2 is filled in the cavities formed by etching, and planarized as the electric and thermal insulation layer 6 in the horizontal direction.

(30) Step 7: Photolithography and etching are performed at the boundary between the strip multilayer electrode structures and the SiO.sub.2 insulating medium to obtain small holes arranged regularly. The bottom of the small holes reaches the surface of substrate (as shown in FIG. 4).

(31) Step 8: Atomic layer deposition ALD is performed to deposit 20 nm of Ge.sub.2Sb.sub.2Te.sub.5 as the phase change functional layer 7 on the walls of the small holes.

(32) Step 9: Magnetron sputtering is performed to deposit TiW at the centers of the phase change material holes until it is completely filled to form the vertical electrodes 8, as shown in the figure.

(33) The parameters and condition settings, etc. in the above-mentioned embodiment have a good feasibility and are of course only taken as examples. To prepare more stacked layers, the above steps 1 to 4 are repeated.

(34) Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modification, equivalent replacement and improvement, etc. made within the spirit and principle of the present disclosure should fall within the scope of the present disclosure.