LOGIC DESIGN WITH UNIPOLAR MEMRISTORS

Abstract

Logic gates are made from first and second resistive elements connected together to form a voltage divider. One or both of the resistive elements is a unipolar memristor. OR and NOT gates may be constructed to make a digital logic system.

Claims

1. Logic gate apparatus, comprising: a first resistive element; and a second resistive element; wherein the first and second resistive elements are connected together to form a voltage divider and one of said first and second resistive elements comprises a unipolar memristor.

2. The logic gate apparatus of claim 1, wherein said second resistive element is a second unipolar memristor connected in series with the first unipolar memristor, thereby to form a section of an OR gate.

3. The logic gate apparatus according to claim 1, and comprising a voltage source connected across the first and second resistive elements.

4. The logic gate apparatus according to claim 2, and comprising a first capacitor connected in parallel with the first unipolar memristor, and a second capacitor connected in parallel with the second unipolar memristor.

5. The logic gate apparatus of claim 1, wherein said second resistive element comprises a resistance connected in series with the unipolar memristor so as to form a section of a NOT gate.

6. The logic gate apparatus according to claim 5, and comprising a first capacitor connected in parallel with the unipolar memristor, and a second capacitor connected in parallel with the resistance.

7. The logic gate apparatus of claim 1, further comprising a third memristor element connected via an OR gate to preserve a state of said first resistive element.

8. Digital logic apparatus, comprising a plurality of logic gates, wherein the gates are at least one of an OR gate and a NOT gate, each gate comprising at least one unipolar memristor.

9. The digital logic apparatus of claim 8, wherein at least one of said gates is said OR gate, and said OR gate comprises: a first unipolar memristor; and a second unipolar memristor connected in series with the first unipolar memristor so as to form a section of said OR gate.

10. The digital logic apparatus according to claim 9, and comprising a first capacitor connected in parallel with the first unipolar memristor, and a second capacitor connected in parallel with the second unipolar memristor.

11. The digital logic apparatus of claim 8, wherein at least one of said gates is said NOT gate, and said NOT gate comprises: a unipolar memristor; and a resistance connected in series with the unipolar memristor so as to form a section of a NOT gate.

12. The digital logic apparatus according to claim 11, and comprising a first capacitor connected in parallel with the unipolar memristor, and a second capacitor connected in parallel with the resistance.

13. The digital logic apparatus according to claim 9, and comprising a first backup memristor and a second backup memristor which are respectively coupled via an OR gate to the first unipolar memristor and the second unipolar memristor.

14. The digital logic apparatus according to claim 11, and comprising a backup memristor which is coupled via an OR gate to the unipolar memristor.

15. A method of constructing a logic circuit comprising: forming at least two logic gates using unipolar memristors, and connecting said logic gates together.

16. The method of claim 15, wherein one of said logic gates is an OR gate, the method comprising: connecting a first unipolar memristor in series with a second unipolar memristor so as to form a section of said OR gate; and applying an initial voltage to the series so as to input a first logical state of the first unipolar memristor and a second logical state of the second unipolar memristor to the OR gate.

17. The method according to claim 16, and comprising applying a further voltage to the series, subsequent to the initial voltage, so as to determine an output of the OR gate.

18. The method of claim 15, comprising: connecting a unipolar memristor in series with a resistance so as to form a section of a NOT gate; and applying an initial voltage to the series so as to input a logical state to the NOT gate.

19. The method according to claim 18, and comprising applying a further voltage to the series, subsequent to the initial voltage, so as to determine an output of the NOT gate.

20. The method according to claim 17, wherein application of the initial voltage and the further voltage is for respective preset fixed durations in time.

21. The method according to claim 19, wherein application of the initial voltage and the further voltage is for respective preset fixed durations in time.

22. The method according to claim 16, comprising applying the initial voltage during a preset stage of the OR gate, applying the further voltage during an evaluation stage of the OR gate, and further comprising applying another voltage between application of the initial voltage and further voltage, in a switching phase of the OR gate.

23. The method according to claim 22, comprising inputting the state of the first and second memristor elements, during the preset stage, to the OR gate.

24. The method according to claim 18, comprising applying the initial voltage during a preset stage of the NOT gate, applying the further voltage during an evaluation stage of the NOT gate, and further comprising applying another voltage between application of the initial voltage and further voltage, in a switching phase of the NOT gate.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0041] Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced.

[0042] In the drawings:

[0043] FIGS. 1A and 1B are simplified state diagrams showing unipolar and bipolar switching of existing memristor devices;

[0044] FIG. 2 is a simplified diagram showing a generalized logic element according to a first preferred embodiment of the present invention;

[0045] FIG. 3 is a simplified graph showing three stages of preset, evaluation and switching stages during a logic operation using the generalized logic element of FIG. 2;

[0046] FIG. 4 is a simplified diagram showing an OR gate constructed using two unipolar memristor elements;

[0047] FIGS. 5A and 5B are simplified diagrams showing voltage and resistance respectively during a logic operation of the OR gate of FIG. 4;

[0048] FIG. 6 is a simplified diagram showing a NOT gate constructed using a unipolar memristor element and a resistive element according to an embodiment of the present invention;

[0049] FIGS. 7A and 7B are simplified diagrams showing voltage and resistance respectively during a logic operation of the NOT gate of FIG. 6;

[0050] FIG. 8 is a simplified diagram showing applied voltage and time with the NOT gate of FIG. 6; and

[0051] FIGS. 9A and 9B are simplified diagrams showing OR and NOT gates according to the present embodiments and showing how they can be used to construct a NAND gate.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

[0052] The present invention, in some embodiments thereof, relates to a logic design using memristors and, more particularly, but not exclusively, to a set of two logic blocks that allow full logic systems to be constructed therefrom.

[0053] The present embodiments focus on logic with unipolar devices, and may provide a technique to construct OR and NOT logic gates with unipolar memristors that can be extended to execute any logical function. Embodiments are tested in simulations using a modified Verilog-A model, to fit TiO.sub.2 thin film unipolar memristors. However, embodiments may be provided to suit any other unipolar materials, such as Phase Change Memory (PCM) materials, so that it will be understood that the method is relevant for any unipolar memristive device.

[0054] Unlike previously proposed logical techniques for unipolar memristors, the present technique is based on intuitive building blocks, in this case OR and NOT gates or logic blocks. Additionally, the present embodiments may be integrated into a memory since only resistance is used to represent logical values throughout the operation, just as data is stored within memristive memories, and no sensing nor transformation between logical representations is needed.

[0055] The basic concept of the proposed logic with unipolar memristors is described along with the basic building blocks of the proposed logic family, being in the present embodiments OR and NOT gates. Timing considerations for the logic gates are also discussed. The design of an advanced logic function is then demonstrated.

[0056] For purposes of better understanding some embodiments of the present invention, as illustrated in FIGS. 2-7B of the drawings, reference is first made to the FIGS. 1A and 1B which illustrate the concepts of unipolar and bipolar switching in memristors.

[0057] The classification of switching into unipolar and bipolar cases is illustrated in Error! Reference source not found. A-B. As discussed in the background, curves I-V of (a) unipolar and (b) bipolar switching mechanisms of memristors are shown. For bipolar switching, a transition from HRS.fwdarw.LRS (SET) occurs at a negative voltage (−VSET), while the transition from LRS.fwdarw.HRS (RESET) occurs at a positive voltage (VRESET). In the case of unipolar switching, a transition from HRS.fwdarw.LRS occurs when crossing a voltage threshold (V.sub.SET or −VSET). Typically, the current during the transition may be limited below a compliance current to avoid overloading the device. Resetting back to the OFF state happens at a voltage below V.sub.SET and above V.sub.RESET (or above −VSET and below −VRESET). A higher current is needed for switching to the OFF state. Thus unipolar switching is preferred in the present embodiments.

[0058] Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways.

[0059] Referring now to the drawings, FIG. 2 illustrates a generalized logic element that uses a unipolar memristor as one of the resistive elements according to an embodiment of the present invention. Logic gate 10 comprises first resistive element 12 and second resistive element 14 connected together to form a voltage divider. One of the resistive elements is a unipolar memristor. The second resistive element is either a conventional resistive element or a unipolar memristor.

[0060] That is to say, the basic mechanism of the logic gates of the present embodiments is made up of a voltage divider between two resistive elements—a memristor and a resistor for a NOT gate or two memristors for an OR gate. On connecting two resistive elements in series and applying a voltage bias; the ratio of voltages on the two elements complies with the ratio of their resistance, i.e., the states are distinguished using a bias voltage. The first stage of operation is translating resistance to resistive states. The applied voltage needed to make a distinction is called the preset voltage.

[0061] After distinction between two states has been achieved, an additional voltage is applied to the circuit, adding a higher or lower applied voltage across both elements, regardless of their states. The voltage in this latter stage is predetermined to a value that promotes switching if necessary for proper execution, and the additional voltage is called the evaluation voltage. The operation may therefore comprise two execution stages—preset and switching. The first, or preset, stage may be thought of as setting up the input(s) for the gate. The second, or switching, stage may be thought of as operating the gate so as to find out, or determine, its output.

[0062] One obstacle to smooth operation of the circuits of the present embodiments arises from the fact that every change in resistance immediately changes the measured voltages, hence, possibly changing the distinction between states. The change may lead to an incorrect result. Therefore maintaining the initial voltage distinction may be required for a sufficient time to reach the desired resistance (HRS or LRS). One possible approach is to incorporate capacitors in the circuit in parallel with the memristors. Since capacitors take time to charge/discharge, they add delay to the system, and such capacitors may be referred to as suspension capacitors. In addition to prolonging the validity of voltage values in the switching stage, suspension capacitors may also delay the preset stage and in the case of the NOT gate, are typically necessary for correct operation. Furthermore, the transition from preset to switching stages cannot be instantaneous.

[0063] Reference is now made to FIG. 3, which is a simplified graph that illustrates three states of the circuits of the present embodiments during a logic operation, preset, evaluation and switching. The intermediate evaluation stage is abstractly depicted as a transitive state and three stages are used to execute the operation as illustrated in FIG. 3. The preset voltage distinguishes between logical states and charges the suspension capacitors. The evaluation stage converts the preceding voltages to the required voltages for switching.

Preset Stage

[0064] In more detail, in the preset stage, a voltage V.sub.PRESET is applied to the circuit to charge the capacitors to initial voltage divider values. The applied voltage is high enough to distinguish between resistive states, but lower than the switching voltage. After sufficient time, approximately no current passes through the capacitors and their voltages are consistent with the voltage divider.

Evaluation Stage

[0065] The evaluation stage starts immediately after the preset stage. A voltage pulse V.sub.EVALUATION is applied to the circuit. The purpose of the evaluation stage is to increase the voltage on both elements abruptly. The final voltage in this stage depends on the final voltage of the preset stage, hence correlates with the resistance of the circuit elements. However, the voltage increase V.sub.EVALUATION−V.sub.PRESET is typically fixed for all scenarios. The exact increase in voltage after the voltage jump is determined by the capacitance ratio (charge sharing). Generally, branches with less capacitance gain more of the voltage increase.

Switching Stage

[0066] In the switching stage, V.sub.EVALUATION is still applied for sufficient time to allow switching of the memristors. A pulse length and voltage magnitude may be selected to switch the memristors according to the desired logical functionality.

Or Gate

[0067] Reference is now made to FIG. 4, which illustrates a two-input OR gate according to the present embodiments. The OR gate 40 consists of two unipolar memristors U.sub.1 and U.sub.2 42 and 44, connected in series with suspension capacitors 46 and 48 connected in parallel to each memristor. The initial logical state of the memristors is the input of the gate and after execution both memristors have the same logical state, which serves as the output of the gate.

[0068] We assume V.sub.SET>V.sub.RESET, and for correct behavior of the gate, certain conditions need to be fulfilled. First, when both inputs are identical (i.e., both are logical ‘1’ or ‘0’) there is no memristor switching. Second, when the inputs are different, the HRS memristor (in logical ‘0’) has to switch to LRS since the desired output is logical ‘1’. The constraints on the voltages are therefore:

V.sub.PRESET<2V.sub.RESET,  (1a)

[0069] Regarding condition (1a), for two memristors with the same input value, e.g., {LRS,LRS} no switching should occur. In this case the voltage on each one of them is 0.5*Vpreset. (If 0.5*Vpreset>Vreset we may cause LRS.fwdarw.HRS switching which is not desired.) The same applies for {HRS,HRS} but since Vreset<Vset the necessary condition is covered this as well.

2V.sub.SET−V.sub.PRESET<V.sub.EVALUATION<2V.sub.RESET.  (1b)

[0070] Regarding condition (1b), the right side of the inequality is as for condition (1a), i.e., to avoid false switching when no switching should occur.

[0071] The left side of the inequality ensures switching occurs when it should. I.e. for {HRS,LRS} .fwdarw.{LRS,LRS} the voltage on the switching memristor at the beginning of the evaluation stage is approximately Vpreset+0.5*(Vevaluation−Vpreset). This should be larger than Vset.

[0072] Thus during operation, the input elements U.sub.1, U.sub.2 are overwritten with the output in terms of changed or unchanged memristive states.

[0073] Reference is now made to FIGS. 5A and 5B, which show simulation results of an OR gate for the case where the inputs are different and U.sub.2 switches for proper result. Note that when U.sub.1 is logical ‘0’ and U.sub.2 logical ‘1’, the operation is destructive, and the value of the inputs may be overwritten.

[0074] In greater detail, in FIGS. 5A and 5B, OR gate simulation results are shown. U.sub.1 and U.sub.2 are initialized to, respectively, LRS (logical ‘1’) and HRS (logical ‘0’) In FIG. 5A, voltages across the memristors during the operation are shown, and FIG. 5B shows the corresponding resistances. In the first 4 μsec the system is in the preset stage, and the capacitors are charged/discharged to distinctive voltages. In the switching stage, U.sub.2 voltage is higher than V.sub.set for sufficient time and its logical value is switched to logical ‘1’ as desired.

[0075] It will be understood that the voltage application during the preset stage inputs the state of the memristors, to the memristor combination acting as an OR gate, as either logical 1 or logical 0.

[0076] It will also be understood that FIGS. 5A and 5B illustrate one possible input of the two-input OR gate, and the resulting output. Those having ordinary skill in the art will be able to generate graphs illustrating the other three possible inputs of the OR gate, and respective resulting outputs. In particular a second set of graphs for inputs U1=1 and U2=0, is similar to 5A and 5B, but with labels reversed. For inputs U1=1 and U2=1 (or U1=0, U2=0) graphs in 5A overlay each other, and graph 5B is just a horizontal line at level Ron) and the voltages never climb above Vreset.

NOT Gate

[0077] Reference is now made to FIG. 6, which is a simplified diagram illustrating a NOT gate according to the present embodiments and based on the generalized embodiment of FIG. 2. The NOT gate 60 consists of a single unipolar memristor 62 connected in series with a reference resistor 64. The memristor acts as both input and output of the NOT gate. Both the memristor and the resistor have a suspension capacitor, 66 and 68 respectively, connected to them in parallel. The resistor 64 may serve as a reference to determine the state of the memristor.

[0078] Reference is now made to the graphs of FIGS. 7A and 7B. Suspension capacitors 66 and 68 are typically necessary for proper operation of the NOT gate. Without the suspension capacitors, V.sub.EVALUATION may be high for correct switching in the case of RESET operations. The resistance of the reference resistor is typically between LRS and HRS. Such a value ensures that the voltage at the end of the preset stage across a HRS (LRS) memristor is high (low). A reasonable choice is R.sub.REF=√{square root over (R.sub.OFFR.sub.ON)}. In one embodiment, the conditions on the applied voltage are:

[00001]$\begin{array}{cc}{V}_{\mathrm{PRESET}}<\min .Math.\left\{\sqrt{\frac{R_{\mathrm{OFF}}}{R_{\mathrm{ON}}}}.Math.V_{\mathrm{RESET}},V_{\mathrm{SET}}\right\},& \left(2.Math.a\right)\\ V_{\mathrm{EVALUATION}}>\frac{1}{\gamma }.Math.\max .Math.\left\{V_{\mathrm{SET}},V_{\mathrm{RESET}}+V_{\mathrm{PRESET}}\right\},& \left(2.Math.b\right)\\ V_{\mathrm{EVALUATION}}<\frac{1}{\gamma }.Math.\left(V_{\mathrm{SET}}+V_{\mathrm{PRESET}}\right),.Math.\mathrm{where}.Math..Math.\gamma .Math.\stackrel{△}{=}.Math.\frac{C_{\mathrm{REF}}}{C_{\mathrm{REF}}+C_{S_1}}.& \left(2.Math.c\right)\end{array}$

[0079] In greater detail, FIGS. 7A and 7B show simulation results for the NOT gate of FIG. 6. FIG. 7A shows voltages and FIG. 7B shows the corresponding resistance during two consecutive memristor switchings. In a first NOT operation, during the first 3 μsec, U.sub.1 switches from LRS.fwdarw.HRS. In the second NOT operation, during the second 3 μsec, U.sub.1 switches back to LRS.

Timing Considerations

[0080] One of the points for suitable behavior of the proposed logic technique is to apply the right voltage for a sufficient time during the switching stage. In this section, possible timing constraints in the switching stage are explored. Assume τ.sub.SET (τ.sub.RESET) is a minimal transition time from HRS (LRS) to LRS (HRS). For successful switching, the duration of the switching stage may be greater than the minimal required switching time. The minimum condition on the length of the stage is therefore:

T.sub.pulse>max{τ.sub.set,τ.sub.reset}=T.sub.pulse,min.  (3)

[0081] At the beginning of the switching stage, each memristor is biased with a voltage which promotes switching (if necessary). The validity of the specified voltage level is typically maintained for a short period of time, due to the use of suspension capacitors, but will eventually become invalid. If the switching stage is not terminated in time, a memristor may reach a voltage range which promotes the opposite transition, i.e., reverse switching. The maximal length of the switching stage may be determined according to the transient analysis of voltages in the circuit, and may be different for SET and RESET operations. For this purpose it is possible to define T.sub.SET (T.sub.RESET) as the approximate period of time in which the conditions for a SET (RESET) operation are met. It is important to understand that while τ.sub.set and τ.sub.reset are properties of the memristor, T.sub.SET and T.sub.RESET are determined by the selection of the different circuit parameters, namely V.sub.PRESET, V.sub.EVALUATION, R.sub.REF, C.sub.REF, C.sub.S, and T.sub.PRESET. Hence, the maximum condition on the length of the switching stage is:

T.sub.pulse<min{T.sub.SET,T.sub.RESET}=T.sub.pulse,max.  (4)

[0082] To comply with both minimum and maximum conditions, both (3) and (4) should apply, as illustrated in FIG. 8. FIG. 8 is a schematic graph showing applied voltage duration in the switching stage according to embodiments of the present invention. T.sub.pulse satisfies condition (3) to reach the desired resistance and also meets condition (4) to avoid reverse switching. The parameters V.sub.PRESET, V.sub.EVALUATION, R.sub.ref, and the switching capacitors can be chosen to support (3) and (4). Different circuit parameters, however, may lead to a reduction in performance. For example, larger capacitors ease the maximum condition, but slow the preset stage and increase power consumption.

Advanced Logic Functions

[0083] OR and NOT functions, such as in the gates illustrated above, may form a complete logic structure, and any desired digital logic function may be reduced to a combination of OR and NOT gates using suitable logic reduction and mapping techniques.

[0084] One difference between the suggested logic gates and conventional CMOS logic is the destructive nature of the operations, i.e. the result of the operation overwrites the input. To resolve this issue a backup memristor with a copy of the initial value can be assigned through an OR operation with a memristor which is initialized to HRS.

[0085] To perform advanced logic operations, a function may be disassembled to its basic ingredients (OR, NOT). Each basic function of the computation may occur at a different time, and in a predetermined order. Reference is now made to FIG. 9A which illustrates a CMOS-based passgate design to select which logic operation (OR/NOT) to perform. An example of NAND(U.sub.1, U.sub.2) operation is listed in Table 1. The schematic of a NAND gate and how it may be constructed from elements according to the present embodiments using Table 1 is shown in FIG. 9B.

TABLE-US-00001 TABLE I NAND operation using a sequence of OR and NOT gates Stage Operation Logical S.sub.OR S.sub.NOT 1a NOT U.sub.1 ← U.sub.1 0 1 1b NOT U.sub.2← U.sub.2 0 1 2 OR U.sub.1 ← U.sub.1 + U.sub.2, U.sub.2 ← U.sub.1 + U.sub.2 1 0

[0086] More particularly, FIG. 9A shows OR and NOT gate symbols and schematics and FIG. 9B shows a schematic of a NAND gate based on the OR and NOT gates of the present embodiments. The signals S.sub.OR and S.sub.NOT control the sequence of operations through the CMOS passgates.

[0087] As research into memristors progresses, using these novel devices for logic computations becomes more appealing and opens opportunities to combine computation and memory. In the present embodiments, a logic technique for unipolar memristors is described using OR and NOT gates. Computation speed is proportional to the intrinsic switching time of the device, and thus performance of systems using the present embodiments may be modified. Likewise different circuit and device parameters may improve control.

[0088] Incorporating the present embodiments into a logic system within a memory may serve as the foundation for a memory based computer architecture. The present embodiments destroy the input state, although additional circuitry can be provided to preserve the input state as discussed herein. It is thus possible using the present embodiments to compute any desired function that conventional digital logic is able to compute.

[0089] Execution of the suggested method with other devices and technologies, such as phase-change memory, has been tested and has also proven feasible.

[0090] It is expected that during the life of a patent maturing from this application many relevant memristor technologies will be developed and the scope of the term ‘memristor’ is intended to include all such new technologies a priori.

[0091] The terms “comprises”, “comprising”, “includes”, “including”, “having” and their conjugates mean “including but not limited to”.

[0092] As used herein, the singular form “a”, “an” and “the” include plural references unless the context clearly dictates otherwise.

[0093] It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

[0094] Although the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

[0095] All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.