SYNCHRONOUS RECTIFICATION DC/DC CONVERTER

Abstract

A pulse modulator generates a pulse signal, such that an output signal of a DC/DC converter approaches a target value. When a detection value of a coil current of the DC/DC converter crosses a threshold for zero crossing, a reverse flow detection circuit asserts a reverse flow detection signal and turns off a synchronous rectification transistor of the DC/DC converter. An optimizer controls an operation parameter of the reverse flow detection circuit, on the basis of a cycle of the pulse signal.

Claims

1. A controller of a synchronous rectification DC/DC converter, the controller comprising: a pulse modulator structured to generate a pulse signal, such that an output signal of the DC/DC converter approaches a target value; a reverse flow detection circuit structured to, when a detection value of a coil current of the DC/DC converter crosses a threshold for zero crossing, assert a reverse flow detection signal and structured to turn off a synchronous rectification transistor of the DC/DC converter; and an optimizer structured to control an operation parameter of the reverse flow detection circuit, on the basis of the pulse signal.

2. The controller according to claim 1, wherein the optimizer is structured to control the operation parameter of the reverse flow detection circuit, on the basis of a cycle of the pulse signal.

3. The controller according to claim 1, wherein the optimizer is structured to control the operation parameter of the reverse flow detection circuit, such that a cycle of the pulse signal approaches a maximum value.

4. The controller according to claim 1, wherein the optimizer is activated at an interval longer than a cycle of the pulse signal.

5. The controller according to claim 2, wherein the optimizer includes a cycle counter structured to measure the cycle of the pulse signal.

6. The controller according to claim 5, wherein the cycle counter is structured to measure the cycle of the pulse signal twice and stops an operation until next measurement, and the optimizer is structured to perform first measurement using an operation parameter in an immediately previous idle period, to perform second measurement using an operation parameter obtained by changing the operation parameter used in the first measurement by a predetermined step, and to determine an operation parameter used in a next idle period, on the basis of a comparison result of two measurement values.

7. The controller according to claim 6, wherein in the optimizer, switching of upstate and downstate is enabled, in the upstate, the operation parameter used in the second measurement is obtained by changing the operation parameter used in the first measurement in a first direction, and in the downstate, the operation parameter used in the second measurement is obtained by changing the operation parameter used in the first measurement in a second direction to be a direction opposite to the first direction.

8. The controller according to claim 7, wherein when a second measurement value is larger than a first measurement value, the operation parameter is changed in the first direction more than a second operation parameter and the optimizer is set to the upstate, and when the second measurement value is smaller than the first measurement value, the operation parameter is changed in the second direction more than the second operation parameter and the optimizer is set to the upstate.

9. The controller according to claim 1, wherein the reverse flow detection circuit includes a comparator which compares the detection value of the coil current with the threshold and a variable delay circuit which delays an output of the comparator and generates the detection signal, and the optimizer controls a delay time of the variable delay circuit.

10. The controller according to claim 1, wherein the reverse flow detection circuit includes a comparator structured to compare the detection value of the coil current with the threshold, and the optimizer is structured to control an offset voltage of the comparator.

11. The controller according to claim 1, wherein the reverse flow detection circuit includes a comparator structured to compare the detection value of the coil current with the threshold, and the optimizer controls the threshold.

12. The controller according to claim 1, wherein the detection value of the coil current is generated on the basis of a voltage across an inductor of the DC/DC converter.

13. The controller according to claim 1, wherein the detection value of the coil current is generated on the basis of a voltage drop across a sense resistor provided in series to an inductor of the DC/DC converter.

14. The controller according to claim 1, wherein the detection value of the coil current is generated on the basis of a voltage across the synchronous rectification transistor of the DC/DC converter.

15. The controller according to claim 1, wherein the controller is monolithically integrated on a semiconductor substrate.

16. A synchronous rectification DC/DC converter comprising the controller according to claim 1.

17. An electronic apparatus comprising the DC/DC converter according to claim 16.

18. A synchronous rectification DC/DC converter comprising: a pulse modulator structured to generate a pulse signal, such that an output signal of the DC/DC converter approaches a target value; a current detection circuit structured to generate a detection value of a coil current of the DC/DC converter; a reverse flow detection circuit structured to assert a detection signal, when the detection value of the coil current crosses a threshold for zero crossing; a driver which structured to drive a switching transistor and a synchronous rectification transistor of the DC/DC converter, on the basis of the pulse signal, and to turn off the synchronous rectification transistor of the DC/DC converter, when the detection signal is asserted; and an optimizer structured to control an operation parameter of the reverse flow detection circuit, on the basis of the pulse signal.

19. A control method for a synchronous rectification DC/DC converter, the control method comprising: generating a pulse signal, such that an output signal of the DC/DC converter approaches a target value; generating a detection value of a coil current of the DC/DC converter; asserting a detection signal, when the detection value of the coil current crosses a threshold for zero crossing; driving a switching transistor and a synchronous rectification transistor of the DC/DC converter, on the basis of the pulse signal; turning off the synchronous rectification transistor of the DC/DC converter, when the detection signal is asserted; and controlling a response speed when the detection signal is generated, on the basis of the pulse signal.

20. The control method according to claim 19, further comprising: measuring a cycle of the pulse signal, wherein, in the controlling of the response speed, the response speed is controlled such that the cycle of the pulse signal increases.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:

[0034] FIG. 1 is a block diagram of a synchronous rectification step-down DC/DC converter;

[0035] FIGS. 2A to 2C are operation waveform diagrams of the DC/DC converter;

[0036] FIGS. 3A to 3C are diagrams illustrating operation waveforms of a discontinuous mode;

[0037] FIG. 4 is a block diagram of a DC/DC converter according to an embodiment;

[0038] FIG. 5 is a circuit diagram illustrating a configuration example of a reverse flow detection circuit and an optimizer;

[0039] FIGS. 6A to 6D are diagrams illustrating examples of efficiency, a delay amount τ.sub.D, a cycle T.sub.P of a pulse signal, and a coil current I.sub.L at timing when a synchronous rectification transistor is turned off;

[0040] FIG. 7 is a time chart illustrating an example of an operation of the optimizer;

[0041] FIG. 8 is a flowchart illustrating an optimization algorithm of the optimizer;

[0042] FIG. 9 is a circuit diagram illustrating a configuration example of a controller according to the embodiment;

[0043] FIG. 10 is a diagram illustrating an example of an electronic apparatus including the DC/DC converter according to the embodiment; and

[0044] FIGS. 11A and 11B are diagrams illustrating modifications of current detection.

DETAILED DESCRIPTION OF THE INVENTION

[0045] The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.

[0046] In the present specification, a “state in which a member A is connected to a member B” includes a state in which the member A is indirectly connected to the member B via another member, not substantially affecting a state of electric connection thereof or impairing a function and an effect achieved by coupling thereof, in addition to a state in which the member A is physically and directly connected to the member B.

[0047] Similarly, a “state in which a member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C via another member or the member B is indirectly connected to the member C via another member, not substantially affecting a state of electric connection thereof or impairing a function and an effect achieved by coupling thereof, in addition to a state in which the member A is directly connected to the member C or the member B is directly connected to the member C.

[0048] FIG. 4 is a block diagram of a DC/DC converter 100 according to an embodiment. In this embodiment, it is assumed that the DC/DC converter 100 is a step-down DC/DC converter (buck converter). The DC/DC converter 100 receives a DC input voltage V.sub.IN by an input terminal P1, generates an output voltage V.sub.OUT stabilized to a predetermined target value V.sub.OUT(REF), and supplies the output voltage V.sub.OUT to a load connected to an output terminal P2.

[0049] A switching transistor M1, a synchronous rectification transistor M2, an inductor L1, and an output capacitor C1 configure an output circuit of the buck converter.

[0050] A pulse modulator 202 generates a pulse signal S1 such that an output signal (output voltage V.sub.OUT) of the DC/DC converter 100 approaches the target value V.sub.OUT(REF). A driver 102 switches the switching transistor M1 and the synchronous rectification transistor M2, according to the pulse signal S1. In this embodiment, the switching transistor M1 is an N-channel MOSFET and a bootstrap circuit (not illustrated in the drawings) including a bootstrap capacitor C2 is provided to turn on the switching transistor M1. The switching transistor M1 may be a P-channel MOSFET. In this case, the bootstrap circuit is not necessary.

[0051] A current detection circuit 104 generates a current detection signal V.sub.CS showing a detection value of a coil current I.sub.L flowing to the inductor L1.

[0052] If the detection value V.sub.CS of the coil current I.sub.L of the DC/DC converter 100 crosses a threshold V.sub.TH for zero crossing, a reverse flow detection circuit 204 asserts a reverse flow detection signal S2 (referred to as ZEROCOMP) and turns off the synchronous rectification transistor M2 of the DC/DC converter 100. The threshold V.sub.TH is set to a positive value near zero.

[0053] A reverse flow detection optimizer 206 (hereinafter, simply referred to as the optimizer 206) controls an operation parameter of the reverse flow detection circuit 204, on the basis of the pulse signal S1. In other words, the reverse flow detection circuit 204 is configured such that at least one operation parameter affecting a delay time τ from crossing of the detection value V.sub.CS of the coil current I.sub.L and the threshold V.sub.TH to turning-off of the synchronous rectification transistor M2 is varied.

[0054] The above is the configuration of the DC/DC converter 100. Next, an operation of the DC/DC converter 100 will be described.

[0055] As described with reference to FIGS. 3A to 3C, efficiency at the time of light loading in the DC/DC converter 100 depends on timing when the synchronous rectification transistor M2 is turned off. According to an examination result from the present inventors, a cycle (interval of the pulse signal S1) of the pulse signal S1 takes a maximum value at optimal timing t.sub.ZC of FIG. 3A or timing near the optimal timing. As illustrated in FIG. 3B, when turning-off timing is earlier than the optimal timing of FIG. 3A, the cycle of the pulse signal Si decreases. In contrast, as illustrated in FIG. 3C, even when the turning-off timing is later than the optimal timing of FIG. 3A, the cycle of the pulse signal S1 decreases.

[0056] In other words, the operation parameter is changed to increase the cycle of the pulse signal S1, so that the turning-off timing of the synchronous rectification transistor M2 can be caused to approach the timing t.sub.ZC when the coil current I.sub.L crosses zero, and efficiency can be improved.

[0057] The present invention extends to various apparatuses and circuits grasped as the block diagram of FIG. 4 or a circuit diagram or derived from the above description and is not limited to a specific configuration. Hereinafter, more concrete control method, configuration, and embodiment will be described to help understanding of the nature of the invention or a circuit operation and to clarify them, not to narrow a range of the present invention.

[0058] The optimizer 206 measures a cycle T.sub.P of the pulse signal S1 and controls the operation parameter of the reverse flow detection circuit 204, on the basis of a measurement value of the cycle T.sub.P. Preferably, the optimizer 206 may control the operation parameter of the reverse flow detection circuit 204, such that the cycle T.sub.P of the pulse signal S1 approaches a maximum value.

[0059] FIG. 5 is a circuit diagram illustrating a configuration example of the reverse flow detection circuit 204 and the optimizer 206. In this configuration, the operation parameter of the reverse flow detection circuit 204 corresponds to a delay amount of the reverse flow detection signal S2. For example, the reverse flow detection circuit 204 includes a comparator 220 and a variable delay circuit 222. The comparator 220 compares the current detection signal V.sub.CS and the threshold voltage V.sub.TH and generates a comparison signal S3 showing a comparison result. The variable delay circuit 222 gives a variable delay τ.sub.D to the comparison signal S3 and generates the reverse flow detection signal S2. The variable delay circuit 222 may be configured integrally with the comparator 220.

[0060] The configuration of the variable delay circuit 222 is not limited in particular and known technology may be used. For example, the variable delay circuit 222 may include a CR circuit, configure at least one of a capacitor and a resistor by a variable element, and change a capacity value or a resistance value to change a delay amount. Or, the variable delay circuit 222 may include a plurality of delay elements connected in series and a selector selecting one of a plurality of taps provided in outputs of the plurality of delay elements.

[0061] The optimizer 206 controls the delay amount TD of the variable delay circuit 222. The optimizer 206 includes a cycle counter 210 and a logic unit 212. The cycle counter 210 measures the cycle T.sub.P of the pulse signal S1. The measurement of the cycle of the pulse signal S1 includes measurement of a cycle of a signal equal to the pulse signal S1 or a signal in an inverse relation with the pulse signal S1, in addition to the measurement of the cycle of the pulse signal S1. The logic unit 212 changes a control signal S4 to designate the delay amount τ.sub.D of the variable delay circuit 222, such that the measured cycle T.sub.P increases.

[0062] FIGS. 6A to 6D are diagrams illustrating examples of the efficiency, the delay amount τ.sub.D, the cycle T.sub.P of the pulse signal S1, and the coil current I.sub.L at timing when the synchronous rectification transistor M2 is turned off. ZeroAdjCode of a horizontal axis shows a value of the control signal S4. In this example, as illustrated in FIG. 6B, the delay amount m decreases when the value of the control signal S4 increases. Referring to FIG. 6D, when the value of the control signal S4 is 10, the synchronous rectification transistor M2 is turned off at timing when the coil current I.sub.L is zero. Referring to FIG. 6A, a maximum point of the efficiency exists near S4=10. If FIGS. 6A and 6C are compared, it is known that the control signal S4 in which the efficiency is maximized and the control signal S4 in which the cycle T.sub.P of the pulse signal S1 is maximized are substantially matched with each other or approach each other.

[0063] Therefore, the control signal S4 is adjusted to increase the cycle T.sub.P of the pulse signal S1, so that the efficiency can be raised.

[0064] Next, a control example of the optimizer 206 will be described. FIG. 7 is a time chart illustrating an example of an operation of the optimizer 206. If the optimizer 206 is always operated, consumption power increases. Therefore, the optimizer 206 is activated intermittently at an interval longer than the cycle of the pulse signal S1 and stops the operation during a period of the remaining interval. As a result, the consumption power can be suppressed from increasing.

[0065] During a first operation period, the cycle counter 210 changes the control signal S4 (operation parameter) and measures cycles of the pulse signal S1 for each operation parameter. In addition, the cycle counter 210 determines a value of the control signal S4 in a next idle period, on the basis of a magnitude relation of the measured cycles. For example, during the first operation period, the cycle counter 210 may change the control signal S4 by two values D.sub.1 and D.sub.2 and measure corresponding cycles T.sub.P1 and T.sub.P2. The first measurement may be performed using an operation parameter in an immediately previous idle period. In addition, the second measurement may be performed using an operation parameter obtained by changing the operation parameter used in the first measurement by a predetermined step. In addition, an operation parameter used in a next idle period may be determined on the basis of a comparison result of the two measurement values T.sub.P1 and T.sub.P2.

[0066] In the optimizer 206, upstate and downstate can be switched. In the upstate, the operation parameter used in the second measurement is obtained by changing (for example, increasing) the operation parameter used in the first measurement in a first direction. In the downstate, the operation parameter used in the second measurement is obtained by changing (for example, decreasing) the operation parameter used in the first measurement in a second direction to be a direction opposite to the first direction.

[0067] FIG. 8 is a flowchart illustrating an optimization algorithm of the optimizer 206. When the optimization algorithm proceeds to an operation period (S100), the cycle T.sub.P1 is measured in a state of the control signal S4 in an immediately previous idle period (S102). In addition, in the case of the upstate (Y of S104), the control signal S4 increases (increments) by one step (S106). In contrast, in the case of the downstate (N of S104), the control signal S4 decreases (decrements) by one step (S108). Next, the cycle T.sub.P2 is measured (S110).

[0068] In the case of T.sub.P1≦T.sub.P2 (Y of S112), the control signal S4 is increased by one step (S114) and is set to the upstate (S116). In the case of T.sub.P1>T.sub.P2 (N of S112), the control signal S4 is decreased by one step (S118) and is set to the downstate (S120). In addition, steps S114 and S118 may be omitted. In step S112, in the case of T.sub.P1=T.sub.P2, the optimization algorithm proceeds to step S118.

[0069] Then, the optimization algorithm proceeds to a next idle period (S122). If a predetermined interval passes, the optimization algorithm returns to step 5100.

[0070] The above is the control of the optimizer 206. According to the control, when the cycle of the pulse signal Si is different from the maximum value, the cycle can be caused to approach the maximum value and the cycle can be maintained at almost the maximum value.

[0071] FIG. 9 is a circuit diagram illustrating a configuration example of a controller 200 according to the embodiment. The controller 200 is a functional integrated circuit (IC) that mainly includes the pulse modulator 202, the reverse flow detection circuit 204, and the optimizer 206 of FIG. 4 and is monolithically integrated on a semiconductor substrate.

[0072] A feedback signal V.sub.FB according to an output voltage V.sub.OUT is input to a feedback (FB) terminal of the controller 200. The pulse modulator 202 generates the pulse signal S1 such that the feedback signal V.sub.FB approaches a reference voltage V.sub.REF. A configuration and a control method of the pulse modulator 202 are not limited in particular and known technology may be used.

[0073] For example, the pulse modulator 202 includes an error amplifier 230, a comparator 232, and a ripple superimposition circuit 234. The ripple superimposition circuit 234 receives a pulse signal S5 according to the pulse signal S1 and superimposes a ripple signal S6 on an input side of the error amplifier 230. The error amplifier 230 amplifies an error of the feedback signal V.sub.FB and the reference voltage V.sub.REF and generates an error signal V.sub.ERR. The comparator 232 compares the feedback signal V.sub.FB on which ripples are superimposed with the error signal V.sub.ERR and generates a pulse signal S7.

[0074] The current detection circuit 104 detects the coil current I.sub.L flowing to the inductor L1, on the basis of a voltage across the inductor L1. For the current detection circuit 104, known technology may be used. An output of the current detection circuit 104 is input to a CSP terminal and a CSN terminal of the controller 200.

[0075] A voltage of one end of the inductor L1 is input to a VOS terminal of the controller 200. The reverse flow detection circuit 204 compares a voltage of the CSP terminal and a voltage of the VOS terminal and generates the reverse flow detection signal S2.

[0076] A peak current detection circuit 208 is provided to regulate an on time of the switching transistor M1 at the time of light loading. The peak current detection circuit 208 includes an amplifier 240 that amplifies a potential difference of the CSP terminal and the CSN terminal and a peak detection comparator 242 that compares an output signal S8 of the amplifier 240 with a threshold V.sub.PEAK. An output S9 of the peak detection comparator 242 is asserted (for example, a high level) when the coil current I.sub.L reaches a peak value I.sub.PEAK corresponding to the voltage V.sub.PEAK.

[0077] A logic circuit 250 generates the pulse signal S1 and generates a control signal S10 to execute an operation in a discontinuous mode, on the basis of the pulse signal S7, the reverse flow detection signal S2, and the peak detection signal S9. If the reverse flow detection signal S2 is asserted, the logic circuit 250 asserts the control signal S10. If the control signal S10 is asserted, the driver 102 turns off the switching transistor M1 and the synchronous rectification transistor M2. In the logic circuit 250, in a light loading state, an on time of the switching transistor M1 is regulated according to the peak detection signal S9 and an on state of the switching transistor M1 is maintained until the peak detection signal S9 is asserted. As a result, energy accumulated in the inductor L1 in the light loading state can be regulated.

[0078] The optimizer 206 can be configured as a part of the logic circuit 250.

[0079] The above is the configuration of the controller 200. According to the controller 200, the DC/DC converter 100 can be operated with high efficiency. The driver 102 or the switching transistor M1 and the synchronous rectification transistor M2 may be integrated into the controller 200.

(Application)

[0080] FIG. 10 is a diagram illustrating an example of an electronic apparatus 700 including the DC/DC converter 100 according to the embodiment. The electronic apparatus 700 is a battery-driven device such as a mobile phone terminal, a digital camera, a digital video camera, a tablet terminal, and a portable audio player. The electronic apparatus 700 includes a casing 702, a battery 704, a microprocessor 706, and the DC/DC converter 100. The DC/DC converter 100 receives a battery voltage V.sub.BAT (=V.sub.IN) from the battery 704 by the input terminal thereof and supplies the output voltage V.sub.OUT to the microprocessor 706 connected to the output terminal thereof.

[0081] The DC/DC converter 100 in which the high efficiency operation is enabled is mounted on the battery-driven electronic apparatus 700, so that an operation time of the electronic apparatus 700 can be increased.

[0082] The present invention has been described on the basis of the embodiment. However, it should be understood by those skilled in the art that the embodiment is only exemplary, various modifications can be made in combinations of the individual components or the individual processes, and the modifications are also included in a range of the present invention. Hereinafter, the modifications will be described.

(First Modification)

[0083] FIGS. 11A and 11B are diagrams illustrating modifications of current detection. In FIG. 11A, a sense resistor R.sub.S is provided in series to the inductor L1. An amplifier 260 amplifies a voltage drop across the sense resistor R.sub.S and generates a detection value of the coil current I.sub.L.

[0084] In FIG. 11B, the coil current I.sub.L is detected using on resistance of the synchronous rectification transistor M2. That is, the detection value of the coil current I.sub.L is generated on the basis of a voltage V.sub.DS across the synchronous rectification transistor M2 of the DC/DC converter 100.

(Second Modification)

[0085] The operation parameter of the reverse flow detection circuit 204 is not limited to the delay time. For example, in FIG. 5, the threshold voltage V.sub.TH input to the comparator 220 may be varied and the threshold voltage V.sub.TH may be controlled by the optimizer 206. Or, an input offset voltage of the comparator 220 may be varied and an offset voltage V.sub.OFS may be controlled by the optimizer 206.

(Third Modification)

[0086] The control algorithm of the optimizer 206 is not limited to the above example and a known maximum value search algorithm may be adopted. For example, simply, the operation parameter may be swept and a point where the pulse cycle T.sub.P is maximized may be searched. The optimizer 206 may control the operation parameter of the reverse flow detection circuit 204, such that the cycle T.sub.P of the pulse signal S1 is included in a predetermined target range.

(Fourth Modification)

[0087] In the embodiment, the optimization is performed by the optimizer 206 during the operation of the DC/DC converter 100. However, the present invention is not limited thereto. Before a load operates immediately after the DC/DC converter 100 starts, a calibration period may be provided and the operation parameter may be optimized during the calibration period.

(Fifth Modification)

[0088] In the embodiment, the operation parameter of the reverse flow detection circuit 204 is controlled on the basis of the cycle T.sub.P of the pulse signal S1. However, the present invention is not limited thereto. For example, the operation parameter may be controlled on the basis of a length of an off time of the switching transistor M1 or a period in which the switching transistor M1 and the synchronous rectification transistor M2 enter a high impedance state. That is, the operation parameter can be controlled on the basis of the various characteristics (the cycle, the frequency, the on time, the off time, and the high impedance period) of the pulse signal S1 correlated with the efficiency.

(Sixth Modification)

[0089] In the embodiment, the step-down converter is described as the example. However, the present invention is applicable to a synchronous rectification boosting or step-up/down converter.

[0090] While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.