Hall device

Abstract

A Hall effect device includes a semiconductor region and at least three contacts to the semiconductor region, which are arranged in the semiconductor region substantially along a line or curve. The line or curve functionally separates the semiconductor region in a first region and a second region. The Hall effect device further including a first electrode that is electrically isolated against the first region and a second electrode that is electrically isolated against the second region. Two of the at least three contacts supply electric energy to the first region and to the second region, and the remaining at least one contact taps an output signal of the first region and/or the second region that responds to a magnetic field component.

Claims

1. A Hall effect device comprising a semiconductor region, at least three contacts to the semiconductor region, wherein the at least three contacts are arranged in the semiconductor region substantially along a line or curve, and wherein the line or curve functionally separates the semiconductor region in a first region and a second region, a first electrode that is electrically isolated against the first region, a second electrode that is electrically isolated against the second region, wherein the first electrode is configured to activate or deactivate the first region, and wherein the second electrode is configured to activate or deactivate the second region, wherein two contacts of the at least three contacts supply electric energy to the first region and to the second region, wherein a remaining at least one contact, of the at least three contacts, taps an output signal of at least one of the first region or the second region that responds to a magnetic field component affecting the Hall effect device.

2. The Hall effect device according to claim 1, wherein the first region and the second region are alternately activated and deactivated.

3. The Hall effect device according to claim 1, wherein the at least three contacts are integrated in the semiconductor region and with at least one of a different material or doping compared to the semiconductor region.

4. The Hall effect device according to claim 3, wherein the first electrode is activated and the second electrode is deactivated for a first duration, and the first electrode is deactivated and the second electrode is activated for a second duration.

5. The Hall effect device according to claim 4, wherein the first duration and the second duration are defined by a rectangular pulse signal or a sinusoidal signal with a frequency f.sub.0.

6. The Hall effect device according to claim 5, wherein the output signal is determined based on a signal obtained via the remaining at least one contact, wherein the signal is demodulated with the rectangular pulse signal or the sinusoidal signal.

7. The Hall effect device according to claim 5, wherein the signal obtained via the remaining at least one contact is at least one of filtered and/oror amplified before the signal is demodulated.

8. The Hall effect device according to claim 1, comprising at least two contacts to at least one of activate or deactivate the first region and the second region.

9. The Hall effect device according to claim 1, wherein the at least three contacts are arranged substantially along a straight line.

10. The Hall effect device according to claim 1, wherein the at least three contacts are arranged substantially on a circle line, wherein the at least three contacts are substantially evenly distributed along the circle line.

11. The Hall effect device according to claim 1, wherein the at least three contacts are switched pursuant to a spinning current scheme.

12. A method for operating a Hall device,. wherein the Hall device comprises: a semiconductor region, at least three contacts to the semiconductor region, wherein the at least three contacts are arranged in the semiconductor region substantially along a line or curve, and wherein the line or curve functionally separates the semiconductor region in a first region and a second region, a first electrode that is electrically isolated against the first region, and a second electrode that is electrically isolated against the second region, wherein the method comprises: activating or deactivating the first region via the first electrode, activating or deactivating the second region via the second electrode, supplying electric energy to the first region and to the second region by two contacts of the at least three contacts, tapping by a remaining at least one contact, of the at least three contacts, an output signal of at least one of the first region or the second region that responds to a magnetic field component affecting the Hall device.

13. The method according to claim 12, further comprising: determining the output signal based on a signal obtained via the remaining at least one contact, wherein the signal is demodulated with a rectangular pulse signal or a sinusoidal signal, which is also used to drive the first electrode and the second electrode in an alternating manner.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Implementations are shown and illustrated with reference to the drawings. The drawings serve to illustrate the basic principle, so that only aspects necessary for understanding the basic principle are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.

(2) FIG. 1 shows an example schematic layout view (top view) of a Hall region comprising a bulk area, terminals and pole plates;

(3) FIG. 2 shows an alternative layout, wherein the terminals are arranged substantially on a circle line;

(4) FIG. 3 shows an alternative implementation of FIG. 1 comprising three contacts that are implemented in three regions of the bulk area;

(5) FIG. 4A shows a first phase of a spinning scheme with five contacts; and

(6) FIG. 4B shows a second phase of a spinning scheme with five contacts.

DETAILED DESCRIPTION

(7) FIG. 1 shows an example schematic layout view (top view) of a Hall region comprising a bulk area 101 with four regions 104 to 107.

(8) The bulk area 101 may be low p-doped similar to a CMOS p-well in silicon technology. The regions 104 to 107 each has an n.sup.+ doping. The region 104 is accessible via a contact T1, the region 105 is accessible via a contact T2, the region 106 is accessible via a contact T3 and the region 107 is accessible via a contact T4.

(9) On top of the bulk area 101, two pole plates 102 and 103 (also referred to as electrodes) are arranged, wherein the pole plate 102 is connected to a terminal G1 and the pole plate 103 is connected to a terminal G2. The terminals G1 and G2 may be regarded as gates and the regions 104 to 107 may each be regarded as drain-source regions.

(10) The combination of bulk area 101, regions 104 to 107 and pole plates 102, 103 can be regarded as Hall region.

(11) In the example shown in FIG. 1, a magnetic field (B-Field) affects the Hall region, wherein the direction of the B-Field is perpendicular to the drawing plane, pointing towards the Hall region. The B-Field may cover the whole Hall device shown in FIG. 1.

(12) The contacts T1 to T4 may be arranged on (or along) a symmetry line 131 of the Hall region thereby dividing the Hall region in a first (upper) area and a second (lower) area. The first area is covered by the pole plate 102 and the second area is covered by the pole plate 103.

(13) The pole plate 102 and the pole plate 103 each is isolated with a thin dielectric from the bulk area 101 so that the potential of each pole plate 102, 103 controls the charge in the Hall region (comparable to an NMOS transistor). The pole plates 102, 103 may thus correspond to the gate electrode of such NMOS transistor.

(14) The operation of the device can be described as follows:

(15) A current I.sub.0 is injected via a current source 112 in the contact T1, wherein the contact T3 is connected to ground.

(16) Voltages are tapped via the contacts T2 and T4.

(17) A generator 111 supplies a rectangular pulse voltage with a frequency f.sub.0, which is supplied via a single inverter 108 to the terminal G1 and via a series connection of two inverters 109, 110 to the terminal G2.

(18) Each of the inverters 108 to 110 supplies an inverted signal, wherein two inverters connected in series supply substantially the original signal. In addition, each inverter 108 to 110 may be a driver that allows a higher current level at its output.

(19) The arrangement of the inverters 108 to 110 depicted in FIG. 1 is an example solution that ensures that the signals at the terminals G1 and G2 are inverse to each other: whenever the signal at the terminal G1 is high, the signal at the terminal G2 is low and vice versa.

(20) If the terminal G1 is high, the Hall region below the pole plate 102 is active (conducting). At the same time, the terminal G2 is low and the Hall region below the pole plate 103 is inactive (not conducting). The B-Field perpendicular to the Hall region, results in a voltage at the contact T2 being larger than a voltage at the contact T4.

(21) In a second operating phase, the terminal G1 is low and the terminal G2 is high. The Hall region below the pole plate 102 is inactive and the Hall region below the pole plate 103 is active.

(22) Since the contacts T1 to T4 are located on the upper edge of the terminal G2 but on the lower edge of the terminal G1, the Hall signal changes its sign: The potential at the contact T2 is smaller than the potential at the contact T4.

(23) Thus, the voltage between the contact T2 and the contact T4 oscillates between two values, which become larger when the magnetic field (B-Field) increases. As long as the two halves (defined by the pole plates 102, 103) of the Hall region are symmetric to the contacts T1 to T4, there is no (significant) offset.

(24) The contact T2 is connected via a capacitor C1 to the positive input terminal of an operational amplifier 121 and the contact T4 is connected via a capacitor C2 to the negative input of the operational amplifier 121. The capacitors C1, C2 ensure that the DC components in the signals conveyed via the contacts T2, T4 are reduced or filtered out. The output signal of the operational amplifier 121 is demodulated via a demodulator 122 using the frequency f.sub.0 of the generator 111 thereby supplying a Hall signal V.sub.out that is proportional to the magnetic field (B-Field) applied to the Hall region.

(25) As an option, a low-pass filter may be added to suppress glitches which may be injected into the signal path via the terminals G1 and G2.

(26) This approach bears the advantage that the signal path, e.g. the path from the contacts T2, T4 towards the Hall signal V.sub.out is not chopped in the low-voltage domain (e.g. left of the operational amplifier 121). Hence, the frequency f.sub.0 can be high compared to solutions of the prior art.

(27) The approach presented may be combined with known spinning schemes. In such case, the contacts T1 to T4 may be connected to switches, which exchange the role of supply terminals and signal terminals, e.g., periodically. In the example shown in FIG. 1, the contacts T1 and T2 may be periodically switched together with the contacts T3 and T4. Such periodically switching of the terminals may preferably occur with a frequency that is smaller than or equal to the frequency f.sub.0.

(28) FIG. 2 shows a top view of an alternative implementation comprising an inner disc 201 and an outer ring 202. The inner disc 201 corresponds to the first pole plate and the outer ring 202 corresponds to the second pole plate. The inner disc 201 is connected to a terminal G1 and the outer ring 202 is connected to a terminal G2.

(29) Contacts T1 to T4 are substantially equally distributed across the circumference of the inner disc 201, which is the curve between the inner disc 201 and the outer ring 202.

(30) It is noted that the bulk area is below the structure shown in FIG. 2 and that the pole plates are isolated with a thin dielectric from the bulk area so that the potential of each of the pole plates may control the charge in the Hall region.

(31) FIG. 3 shows an alternative implementation based on FIG. 1 with three regions 301 to 303 and three contacts T1, T2 and T3 instead of the four regions and four contacts shown in FIG. 1.

(32) The contact T1 is connected to the current source 112 and the contact T3 is connected to ground. The contact T2 is connected via an optional buffer 305 and a high-pass filter 304 to the positive input of the operational amplifier 121. The negative input of the operational amplifier 121 is connected to ground.

(33) The high-pass filter 304 may comprise a capacitor C3 and a resistor R, which build an RC-high pass of first order.

(34) FIG. 4A and FIG. 4B show an alternative implementation also based on FIG. 1 with five regions 401 to 405 and five contacts T1 to T5.

(35) FIG. 4A shows a first phase of a spinning scheme and FIG. 4B shows a second phase of a spinning scheme. In each phase, the contacts T1 to T5 are connected (switched) differently towards the current source 112 and the operational amplifier 121.

(36) In the first phase shown in FIG. 4A, the contacts T1 and T5 are connected to the current source 112 and the contact T3 is connected to ground. The contact T2 is connected to the positive input of the operational amplifier 121 and the contact T4 is connected to the negative input of the operational amplifier 121.

(37) In the second phase shown in FIG. 4B, the contact T2 is connected to the current source 112 and the contact T4 is connected to ground. The contacts T1 and T5 are both connected to the positive input of the operational amplifier 121 and the contact T3 is connected to the negative input of the operational amplifier 121.

(38) In contrast to FIG. 1, FIG. 4A and FIG. 4B do not have the capacitors C1 and C2, but a high-pass filter 406 is arranged between the output of the operational amplifier 121 and the demodulator 122.

(39) Several phases (also phases different to the ones shown and explained above) can be realized to enable the benefits of spinning current schemes.

(40) Although various example implementations of the implementation have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the implementation without departing from the spirit and scope of the implementation. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. It should be mentioned that features explained with reference to a specific figure may be combined with features of other figures, even in those cases in which this has not explicitly been mentioned. Further, the methods of the implementation may be achieved in either all software implementations, using the appropriate processor instructions, or in hybrid implementations that utilize a combination of hardware logic and software logic to achieve the same results. Such modifications to the inventive concept are intended to be covered by the appended claims.