Current-controlled CMOS logic family

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus comprising: an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C.sup.3MOS) logic, configured to deserialize a serialized signal to generate a plurality of signals; and wherein: the C.sup.3MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein: a current steering circuit within the C.sup.3MOS logic including the first source and the second source; the first source and the second source being coupled together and to a current source; the first drain and the second drain being coupled to a power supply; and the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with deserializing the serialized signal to generate the plurality of signals.

2. The apparatus of claim 1 further comprising: a C.sup.3MOS logic circuitry, within the integrated circuitry, configured to receive the serialized signal and to generate the plurality of signals; and a CMOS logic circuitry, within the integrated circuitry, configured to receive at least one of the plurality of signals from the C.sup.3MOS logic circuitry.

3. The apparatus of claim 1 further comprising: a C.sup.3MOS logic circuitry, within the integrated circuitry, configured to receive the serialized signal and to generate the plurality of signals; and a first CMOS logic circuitry, within the integrated circuitry, configured to receive a first signal of the plurality of signals from the C.sup.3MOS logic circuitry; and a second CMOS logic circuitry, within the integrated circuitry, configured to receive a second signal of the plurality of signals from the C.sup.3MOS logic circuitry.

4. The apparatus of claim 1 further comprising: a first C.sup.3MOS logic circuitry, within the integrated circuitry, configured to receive the serialized signal and to generate the plurality of signals; and a CMOS logic circuitry, within the integrated circuitry, configured to process the plurality of signals to generate a plurality of processed signals; and a second C.sup.3MOS logic circuitry configured to receive the plurality of processed signals.

5. The apparatus of claim 1, wherein the CMOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

6. The apparatus of claim 1, wherein: the serialized signal has a first frequency; and each signal of the plurality of signals has a second frequency that is different than the first frequency.

7. The apparatus of claim 1, wherein: the serialized signal has a first frequency; and each signal of the plurality of signals has a second frequency that is approximately one-half of the first frequency.

8. The apparatus of claim 1 further comprising: a C.sup.3MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

9. The apparatus of claim 1, wherein the plurality of signals and the serialized signal being electrical signals including data compliant with a fiber channel.

10. The apparatus of claim 1, wherein the serialized signal being a differential signal.

11. An apparatus comprising: an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C.sup.3MOS) logic, configured to: receive a first serialized signal; process the first serialized signal to generate a second serialized signal; and output the second serialized signal; and wherein: the C.sup.3MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein: a current steering circuit within the C.sup.3MOS logic including the first source and the second source; the first source and the second source being coupled together and to a current source; the first drain and the second drain being coupled to a power supply; and the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with receiving the first serialized signal, processing the first serialized signal to generate the second serialized signal, or outputting the second serialized signal.

12. The apparatus of claim 11 further comprising: a first C.sup.3MOS logic circuitry, within the integrated circuitry, configured to process the first serialized signal to generate a plurality of signals; and a CMOS logic circuitry, within the integrated circuitry, configured to process the plurality of signals to generate a plurality of processed signals, wherein each signal of the plurality of signals and the plurality of processed signals has a first frequency; and a second C.sup.3MOS logic circuitry configured to process the plurality of processed signals to generate the second serialized signal, wherein the first serialized signal and the second serialized signal have a second frequency that is different than the first frequency.

13. The apparatus of claim 11, wherein the C.sup.3MOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

14. The apparatus of claim 11 further comprising: a C.sup.3MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

15. The apparatus of claim 11, wherein the first serialized signal of the second serialized signal being an electrical signal including data compliant with a fiber channel.

16. An apparatus comprising: an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C.sup.3MOS) logic, configured to process a first signal using at least one processing operation to generate a second signal, wherein the at least one processing operation corresponds to an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop; and wherein: the C.sup.3MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein: a current steering circuit within the C.sup.3MOS logic including the first source and the second source; the first source and the second source being coupled together and to a current source; the first drain and the second drain being coupled to a power supply; and the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with processing the first signal using at least one processing operation to generate the second signal.

17. The apparatus of claim 16 further comprising: a C.sup.3MOS logic circuitry, within the integrated circuitry, configured to receive the first signal and to generate another signal; and a CMOS logic circuitry, within the integrated circuitry, configured to process the another signal to generate the second signal.

18. The apparatus of claim 16, wherein at least one of the first signal or the second signal including data compliant with a fiber channel.

19. The apparatus of claim 16 further comprising: a C.sup.3MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

20. The apparatus of claim 16, wherein the first signal or the second signal being a differential signal.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 shows a conventional CMOS inverter;

(2) FIG. 2 is an inverter/buffer implemented in C.sup.3MOS according to an exemplary embodiment of the present invention;

(3) FIG. 3 shows an exemplary C.sup.3MOS level shift buffer according to the present invention;

(4) FIGS. 4A and 4B show exemplary C.sup.3MOS implementations for an AND/NAND gate and an OR/NOR gate, respectively;

(5) FIG. 5 shows an exemplary C.sup.3MOS implementation for a 2:1 multiplexer;

(6) FIG. 6 shows an exemplary C.sup.3MOS implementation for a two-input exclusive OR/NOR gate;

(7) FIG. 7 is a circuit schematic showing an exemplary C.sup.3MOS clocked latch according to the present invention;

(8) FIG. 8 is a circuit schematic for an alternate embodiment for a C.sup.3MOS flip-flop according to the present invention;

(9) FIG. 9 shows an exemplary C.sup.3MOS implementation for a flip-flop using the C.sup.3MOS latch of FIG. 7;

(10) FIG. 10 shows a block diagram for a circuit that combines C.sup.3MOS and conventional CMOS logic on a single silicon substrate to achieve optimum tradeoff between speed and power consumption;

(11) FIG. 11 shows an exemplary circuit application of the C.sup.3MOS/CMOS combined logic wherein C.sup.3MOS logic is used to deserialize and serialize the signal stream while CMOS logic is used as the core signal processing logic circuitry;

(12) FIG. 12 is a simplified block diagram of a transceiver system that utilizes the C.sup.3MOS/CMOS combined logic according to the present invention to facilitate interconnecting high speed fiber optic communication channels.

DETAILED DESCRIPTION OF THE INVENTION

(13) The present invention provides ultra high-speed logic circuitry implemented in silicon complementary metal-oxide-semiconductor (CMOS) process technology. A distinction is made herein between the terminology “CMOS process technology” and “CMOS logic.” CMOS process technology as used herein refers generally to a variety of well established CMOS fabrication processes that form a field-effect transistor over a silicon substrate with a gate terminal typically made of polysilicon material disposed on top of an insulating material such as silicon dioxide. CMOS logic, on the other hand, refers to the use of complementary CMOS transistors (n-channel and p-channel) to form various logic gates and more complex logic circuitry, wherein zero static current is dissipated. The present invention uses current-controlled mechanisms to develop a family of very fast current-controlled CMOS (or C.sup.3MOS™) logic that can be fabricated using a variety of conventional CMOS process technologies, but that unlike conventional CMOS logic does dissipate static current. C.sup.3MOS logic or current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) logic are used herein interchangeably.

(14) In a preferred embodiment, the basic building block of this logic family is an NMOS differential pair with resistive loads. Referring to FIG. 2, there is shown one embodiment for the basic C.sup.3MOS inverter/buffer 200 according to the present invention. Inverter/buffer 200 includes a pair of n-channel MOSFETs 202 and 204 that receive differential logic signals D and D# at their gate terminals, respectively. Resistive loads 206 and 208 connect the drain terminals of MOSFETs 202 and 204, respectively, to the power supply Vcc. Drain terminals of MOSFETs 202 and 204 form the outputs OUT# and OUT of the inverter/buffer, respectively. Resistive loads 206 and 208 may be made up of either p-channel MOSFETs operating in their linear region, or resistors made up of, for example, polysilicon material. In a preferred embodiment, polysilicon resistors are used to implement resistive loads 206 and 208, which maximize the speed of inverter/buffer 200. The source terminals of n-channel MOSFETs 202 and 204 connect together at node 210. A current-source n-channel MOSFET 212 connects node 210 to ground (or negative power supply). A bias voltage VB drives the gate terminal of current-source MOSFET 212 and sets up the amount of current I that flows through inverter/buffer 200. In response to the differential signal at D and D#, one of the two input n-channel MOSFETs 202 and 204 switches on while the other switches off. All of current I, thus flows in one leg of the differential pair pulling the drain terminal (OUT or OUT#) of the on transistor down to logic low, while the drain of the other (off) transistor is pulled up by its resistive load toward logic high. At the OUT output this circuit is a buffer, while at the OUT# output the circuit acts as an inverter.

(15) Significant speed advantages are obtained by this type of current steering logic. Unlike the conventional CMOS inverter of FIG. 1, when either one of the input MOSFETs 202 or 204 is switching on, there is no p-channel pull-up transistor that fights the n-channel. Further, circuit 200 requires a relatively small differential signal to switch its transistors. This circuit also exhibits improved noise performance as compared to the CMOS inverter of FIG. 1, since in the C3MOS inverter/buffer, transistors do not switch between the power supply and the substrate. Logic circuitry based on current-steering techniques have been known in other technologies such as bipolar, where it is called emitter-coupled logic (ECL), and GaAs where it is called source-coupled FET logic (SCFL). This technique, however, has not been seen in silicon CMOS technology for a number of reasons, among which is the fact that CMOS logic has always been viewed as one that dissipates zero static current. The C.sup.3MOS logic as proposed by the present invention, on the other hand, does dissipate static current.

(16) The design of each C.sup.3MOS logic cell according to the present invention is optimized based on several considerations including speed, current dissipation, and voltage swing. The speed of the logic gate is determined by the resistive load and the capacitance being driven. As discussed above, the preferred embodiment according to the present invention uses polysilicon resistors to implement the load devices. P-channel MOSFETs can alternatively be used, however, they require special biasing to ensure they remain in linear region. Further, the junction capacitances of the p-channel load MOSFETs introduce undesirable parasitics. Speed requirements place a maximum limit on the value of the resistive loads. On the other hand, the various C.sup.3MOS logic cells are designed to preferably maintain a constant voltage swing (I×R). Accordingly, the values for R and I are adjusted based on the capacitive load being driven to strike the optimum trade-off between switching speed and power consumption.

(17) The C.sup.3MOS logic family, according to the present invention, contains all the building blocks of other logic families. Examples of such building blocks include inverters, buffers, level shift buffers, N-input NOR and NAND gates, exclusive OR (XOR) gates, flip flops and latches, and the like. FIG. 3 shows an exemplary C.sup.3MOS level shift circuit 300 according to the present invention. Level shift circuit 300 includes essentially the same circuit elements as inverter/buffer 200 shown in FIG. 2, with an additional resistor Rs 302 inserted between the power supply Vcc and the load resistors. Circuit 300 operates in the same fashion as inverter/buffer 200 except that it has its power supply voltage shifted by a value equal to (I×Rs). The C.sup.3MOS logic circuitry according to the present invention employs this type of level shifter to make the necessary adjustments in the signal level depending on the circuit requirements. Examples of C.sup.3MOS circuits utilizing this type of level shifting will be described below in connection with other types of C.sup.3MOS logic elements.

(18) FIGS. 4A and 4B show exemplary C.sup.3MOS implementations for an exemplary 2-input AND/NAND gate 400 and an exemplary 2-input OR/NOR gate 402, respectively. These gates operate based on the same current steering principal as discussed above. A logic low signal at input B of AND/NAND gate 400 brings OUT to ground via Q4 while OUT# is pulled high by its load resistor. A logic low at the A input also pulls OUT to ground via Q2 and Q3 (B=high). OUT is pulled high only when both A and B are high disconnecting any path to ground. OUT# provides the inverse of OUT. OR/NOR gate 402 operates similarly to generate OR/NOR logic at its outputs. When another set of transistors are inserted in each leg of the differential pair as is the case for gates 400 and 402, the signals driving the inserted transistors (Q3, Q4) need level shifting to ensure proper switching operation of the circuit. Thus, high speed C.sup.3MOS level shifters such as those presented in FIG. 3 can be employed to drive signals B and B#. In a preferred embodiment, since node OUT in both gates 400 and 402 must drive the additional parasitics associated transistors Q4, dummy load transistors DQL1 and DQL2 connect to node OUT# to match the loading conditions at both outputs.

(19) FIG. 5 shows an exemplary C.sup.3MOS implementation for a 2:1 multiplexer 500. Similar to the other C.sup.3MOS logic gates, multiplexer 500 includes a differential pair for each input, but multiplexer 500 further includes select transistors 502 and 504 inserted between the common source terminals of the differential pairs and the current source transistor in a cascade structure. By asserting one of the select input signals SELA or SELB, the bias current is steered to the differential pair associated with that select transistor. Thus, signal SELA steers the bias current to the differential pair with A and A# inputs, and signal SELB steers the bias current to the differential pair with B and B# inputs. Similar to gates 400 and 402, the signals SELA and SELB driving 15 inserted transistors 502 and 504 need level shifting to ensure proper switching operation of the circuit.

(20) FIG. 6 shows an exemplary C.sup.3MOS implementation for a two-input exclusive OR (XOR) gate 600. This implementation includes two differential pairs 602 and 606 that share the same resistive load, receive differential signals A and A# at their inputs as shown, and have their drain terminals cross-coupled at the outputs. The other differential input signals B and B# are first level shifted by circuit 606 and then applied to cascade transistors 608 and 610 that are inserted between the differential pairs and the current source transistor. The circuit as thus constructed performs the XOR function on the two input signals A and B.

(21) FIG. 7 is a circuit schematic showing an exemplary C.sup.3MOS clocked latch 700 according to the present invention. Latch 700 includes a first differential pair 702 that receives differential inputs D and D# at the gate terminals, and a second differential pair 704 that has its gate and drain terminals cross-coupled to the outputs of OUT and OUT# first differential pair 702. Clocked transistors 706 and 708 respectively connect common-source nodes of differential pairs 702 and 704 to the current-source transistor. Complementary clock signals CK and CKB drive the gate terminals of clocked transistors 706 and 708. Similar to the other C.sup.3MOS gates that have additional transistors inserted between the differential pair and the current-source transistor, clock signals CK and CKB are level shifted by level shift circuits such as that of FIG. 3.

(22) A C.sup.3MOS master-slave flip-flop 800 according to the present invention can be made by combining two latches 700 as shown in FIG. 8. A first latch 802 receives differential input signals D and D# and generates differential output signals QI and QI#. The differential output signals QI and QI# are then applied to the differential inputs of a second latch 804. The differential outputs Q and Q# of second latch 804 provide the outputs of flip-flop 800.

(23) In FIG. 8, a different power supply voltage (e.g., AVDD) may be employed for a C.sup.3MOS circuit portion than may be employed for a CMOS circuit portion (e.g., Vcc as in FIG. 1). In addition, FIG. 8 shows that yet another, different power supply (e.g., AVSS) may be connected to the source terminal of a current source transistor (e.g., see the current source transistors near the bottom of FIG. 8).

(24) Every one of the logic gates described thus far may be implemented using p channel transistors. The use of p-channel transistors provides for various alternative embodiments for C.sup.3MOS logic gates. FIG. 9 shows one example of an alternative implementation for a C.sup.3MOS clocked latch 900 that uses p-channel transistors. In this embodiment, instead of inserting the n-channel clocked transistors between the common-source nodes of the differential pairs and the current-source transistor, p channel clocked transistors 902 and 904 connect between the common-source nodes and the power supply Vcc. This implementation also requires that each differential pair have a separate current-source transistor as shown. Clocked latch 900 operates essentially the same as latch 700 shown in FIG. 7, except the implementation is not as efficient both in terms of size and speed.

(25) As illustrated by the various C.sup.3MOS logic elements described above, all of the building blocks of any logic circuitry can be constructed using the C.sup.3MOS technique of the present invention. More complex logic circuits such as shift registers, counters, frequency dividers, etc., can be constructed in C.sup.3MOS using the basic elements described above. As mentioned above, however, C.sup.3MOS logic does consume static power. The static current dissipation of C.sup.3MOS may become a limiting factor in certain large scale circuit applications. In one embodiment, the present invention combines C.sup.3MOS logic with conventional CMOS logic to achieve an optimum balance between speed and power consumption. According to this embodiment of the present invention, an integrated circuit utilizes C.sup.3MOS logic for the ultra high speed (e.g., GHz) portions of the circuitry, and conventional CMOS logic for the relatively lower speed sections. For example, to enable an integrated circuit to be used in ultra high speed applications, the input and output circuitry that interfaces with and processes the high speed signals is implemented using C.sup.3MOS. The circuit also employs C.sup.3MOS to divide down the frequency of the signals being processed to a low enough frequency where conventional CMOS logic can be used. The core of the circuit, according to this embodiment, is therefore implemented by conventional CMOS logic that consumes zero static current. FIG. 10 shows a simplified block diagram illustrating this exemplary embodiment of the invention. A C.sup.3MOS input circuit 1000 receives a high frequency input signal IN and outputs a divided down version of the signal IN/n. The lower frequency signal IN/n is then processes by core circuitry 1002 that is implemented in conventional CMOS logic. A C.sup.3MOS output circuit 1004 then converts the processed IN/n signal back to the original frequency (or any other desired frequency) before driving it onto the output node OUT.

(26) An example of a circuit implemented using combined CMOS/C.sup.3MOS logic according to the present invention is shown in FIG. 11. C.sup.3MOS input circuitry 1100 is a deserializer that receives a serial bit stream at a high frequency of, for example, 2 GHz. A 2 GHz input clock signal CLK is divided down to 1 GHz using a C.sup.3MOS flip-flop 1102, such as the one shown in FIG. 8, that is connected in a ÷2 feedback configuration. The 1 GHz output of flip-flop 1102 is then supplied to clock inputs of a pair of C.sup.3MOS latches 1104 and 1106. Latches 1104 and 1106, which may be of the type shown in FIG. 6, receive the 2 GHz input bit stream at their inputs and respectively sample the rising and falling edges of the input bit stream in response to the 1 GHz clock signal CLK/2. The signal CLK/2 which is applied to the B/B# inputs of each latch (the level shifted input; see FIG. 6), samples the input data preferably at its center. It is to be noted that the rise and fall times of the signal in CMOS logic is often very dependent on process variations and device matching. C.sup.3MOS logic, on the other hand, is differential in nature and therefore provides much improved margins for sampling.

(27) Referring back to FIG. 11, block 1100 thus deserializes the input bit stream with its frequency halved to allow for the use of conventional CMOS logic to process the signals. The signals at the outputs of latches 1104 and 1106 are applied to parallel processing circuitry 1108 that are implemented in conventional CMOS logic operating at 1 GHz. The reverse is performed at the output where a serializer 1110 receives the output signals from processing circuitry 1108 and serializes them using C.sup.3MOS logic. The final output signal is a bit stream with the original 2 GHz frequency. Circuit applications wherein this technique can be advantageously employed include high speed single or multi-channel serial links in communication systems.

(28) As apparent from the circuit shown in FIG. 11, this technique doubles the amount of the core signal processing circuitry. However, since this part of the circuit is implemented in conventional CMOS logic, current dissipation is not increased by the doubling of the circuitry. Those skilled in the art appreciate that there can be more than one level of deserializing if further reduction in operating frequency is desired. That is, the frequency of the input signal can be divided down further by 4 or 8 or more if desired. As each resulting bit stream will require its own signal processing circuitry, the amount and size of the overall circuitry increases in direct proportion to the number by which the input signal frequency is divided. For each application, therefore, there is an optimum number depending on the speed, power and area requirements.

(29) According to one embodiment of the present invention the combined C.sup.3MOS/CMOS circuit technique as shown in FIG. 11 is employed in a transceiver of the type illustrated in FIG. 12. The exemplary transceiver of FIG. 12 is typically found along fiber optic channels in high speed telecommunication networks. The transceiver includes at its input a photo detect and driver circuit 1200 that receives the input signal from the fiber optic channel. Circuit 1200 converts fiber-optic signal to packets of data and supplies it to a clock data recovery (CDR) circuit 1202. CDR circuit 1202 recovers the clock and data signals that may be in the frequency range of about 2.5 GHz, or higher. Established telecommunication standards require the transceiver to perform various functions, including data monitoring and error correction. These functions are performed at a lower frequency. Thus, the transceiver uses a demultiplexer 1204 which deserializes the 2.5 GHz data stream into, for example, 16 parallel signals having a frequency of about 155 MHz. An application specific integrated circuit (ASIC) 1206 then performs the monitoring and error correction functions at the lower (155 MHz) frequency. A multiplexer and clock multiplication unit (CMU) 1208 converts the parallel signals back into a single bit stream at 2.5 GHz. This signal is then retransmitted back onto the fiber optic channel by a laser drive 1212. The combined C.sup.3MOS/CMOS technique of the present invention allows fabrication of demultiplexer 1204, ASIC 1206 and multiplexer and CMU 1208 on a single silicon die, as indicated by reference numeral 1210, in a similar fashion as described in connection with the circuit of FIGS. 10 and 11. That is, demultiplexer 1204 and multiplexer and CMU 1208 are implemented in C.sup.3MOS with ASIC 1206 implemented in conventional CMOS.

(30) In conclusion, the present invention provides various circuit techniques for implementing ultra high speed circuits using current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like have been developed using C.sup.3MOS according to the present invention. In one embodiment, the present invention advantageously combines high speed C.sup.3MOS logic with low power conventional CMOS logic. According to this embodiment circuits such as transceivers along fiber optic channels can be fabricated on a single chip where the ultra-high speed portions of the circuit utilize C.sup.3MOS and the relatively lower speed parts of the circuit use conventional CMOS logic. While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents.

(31) In addition, certain embodiments of the present invention provide a new family of CMOS logic that is based on current-controlled mechanism to maximize speed of operation. The current-controlled CMOS (or C.sup.3MOS™) logic family according to the present invention includes all the building blocks of any other logic family. The basic building block of the C.sup.3MOS logic family uses a pair of conventional MOSFETs that steer current between a pair of load devices in response to a difference between a pair of input signals. Thus, unlike conventional CMOS logic, C.sup.3MOS logic according to this invention dissipates static current, but operates at much higher speeds. In one embodiment, the present invention combines C.sup.3MOS logic with CMOS logic within the same integrated circuitry, where C.sup.3MOS is utilized in high speed sections and CMOS is used in the lower speed parts of the circuit.

(32) Accordingly, in one embodiment, the present invention provides a current-controlled metal-oxide semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, including a clocked latch made up of first and second n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to receive a pair of differential logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively; a first clocked n-channel MOSFET having a drain terminal connected to the source terminals of the first and second n-channel MOSFETs, a gate terminal coupled to receive a first clock signal CK, and a source terminal; third and fourth n-channel MOSFETs having their source terminals connected together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output; a second clocked n-channel MOSFET having a drain terminal connected to the source terminals of the third and fourth n-channel MOSFETs, a gate terminal coupled to receive a second clock signal CKB, and a source terminal; first and second resistive elements respectively coupling the true output and the complementary output to a high logic level; and a current-source n-channel MOSFET connected between the source terminals of the first and second clocked n-channel MOSFETs and a logic low level.

(33) In another embodiment, the circuit further includes a buffer/inverter made up of first and second n-channel MOSFETs having their source terminals connected together, their gate terminals respectively coupled to receive a pair of differential logic signals, and their drain terminals coupled to a high logic level via a respective pair of resistive loads; and a current-source n-channel MOSFET connected between the source terminals of the first and second n-channel MOSFETs and a low logic level, wherein, the drain terminal of the first n-channel MOSFET provides a true output of the buffer/inverter and the drain terminal of the second n-channel MOSFET provides the complementary output of the buffer/inverter.

(34) In yet another embodiment, the present invention provides complementary metal-oxide-semiconductor (CMOS) logic circuitry that combines on the same silicon substrate, current-controlled MOSFET circuitry of the type described above for high speed signal processing, with conventional CMOS logic that does not dissipate static current. Examples of such combined circuitry include serializer/deserializer circuitry used in high speed serial links, high speed phase-locked loop dividers, and the like.