Hybrid power stage and gate driver circuit

Abstract

Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

Claims

1. A power semiconductor switching stage comprising: a hybrid power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein: the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device implemented with at least one transistor, wherein every transistor of the high-side switch is an enhancement-mode GaN power transistor having a source, a drain and a gate; and the low-side switch is a Silicon (Si) semiconductor power switching device implemented with at least one transistor, wherein every transistor of the low-side switch is an enhancement-mode Si MOSFET having a source, a drain and a gate; the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a switch node, the drain of every Si MOSFET is connected to the switch node, and the source of every Si MOSFET is connected to a source bus; a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver; a gate drive output of the low-side driver being connected to the gate of every Si MOSFET through a first gate drive circuit comprising a gate resistor to provide a gate drive of a first voltage range for driving every Si MOSFET; a gate drive output of the high-side driver being connected to the gate of every GaN power transistor through a second gate drive circuit comprising a gate resistor and a voltage level shift circuit to provide a gate drive of a second voltage range for driving every GaN power transistor.

2. The power semiconductor switching stage of claim 1, wherein the low-side switch comprises a plurality of Si MOSFETs connected in parallel.

3. The power semiconductor switching stage of claim 1, wherein the high-side switch comprises a plurality of GaN power transistors connected in parallel.

4. The power semiconductor switching stage of claim 1 wherein, for a supply voltage V.sub.DD, said first voltage range for driving every Si MOSFET is a range from 0V to V.sub.DD, and the second voltage range for driving every GaN power transistor is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.

5. The power semiconductor switching stage of claim 4, wherein the voltage level shift circuit comprises a capacitor in parallel with a resistor, connected in series between the gate resistor and the gate of every GaN power transistor, and a clamp circuit connected between the gate of every GaN power transistor and the source of every GaN power transistor for clamping the positive turn-on gate voltage and the negative turn-off gate voltage.

6. The power semiconductor switching stage of claim 5, wherein the clamp circuit comprises a diode clamp.

7. The power semiconductor switching stage of claim 1, which is part of a half-bridge or full-bridge power switching stage.

8. The power semiconductor switching stage of claim 1, wherein every GaN power transistor is a GaN HEMT.

9. The power semiconductor switching stage of claim 1, wherein said MOSFET half-bridge gate driver is integrated with a driver controller.

10. A gate driver for a hybrid power switching device comprising a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein: the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device implemented with at least one transistor, wherein every transistor of the high-side switch is an enhancement mode GaN power transistor having a source, a drain and a gate; and the low-side switch is an enhancement-mode Silicon (Si) semiconductor power switching device implemented with at least one transistor, wherein every power transistor of the low-side switch is a Si MOSFET having a source, a drain and a gate; the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a switch node, the drain of every Si MOSFET is connected to the switch node, and the source of every Si MOSFET is connected to a source bus; the gate driver comprising: a half-bridge driver comprising a high-side driver and a low-side driver; a gate drive output of the low-side driver being connected through a first gate drive circuit comprising a first gate resistor to provide a gate drive voltage output of a first voltage range for driving the gate of every Si MOSFET of the low-side switch; a gate drive output of the high-side driver being connected through a second gate drive circuit comprising a gate resistor and a voltage level shift circuit to provide a gate drive voltage output of a second voltage range for driving the gate of every GaN transistor of the high-side switch.

11. The gate driver of claim 10, wherein for a supply voltage V.sub.DD, the first voltage range for driving the Si semiconductor power switching device is in a range from 0V to V.sub.DD and the second voltage range for driving the GaN semiconductor power switching device is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.

12. The gate driver of claim 11, wherein the level shift circuit comprises a capacitor in parallel with a resistor, connected in series between the gate resistor and the gate of every GaN power transitor, and a clamp circuit connected between the gate of every GaN power transistor and the source of every GaN power transistor for clamping the positive turn-on gate voltage and the negative turn-off gate voltage.

13. The gate driver of claim 12, wherein the clamp circuit comprises a diode clamp.

14. The gate driver of claim 10, integrated with a driver controller.

15. A power semiconductor switching stage comprising: a hybrid power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein: the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device, implemented with a plurality of power transistors connected in parallel, wherein every power transistor of the high-side switch is an enhancement-mode GaN power transistor, having a drain, a source and a gate; the low-side switch is a Silicon (Si) semiconductor power switching device, implemented with a plurality of power transistors connected in parallel, wherein every power transistor of the low-side switch is an enhancement-mode Si MOSFET, having a drain, a source and a gate; the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a switch node, the drain of every Si MOSFET is connected to the common switch node, and the source of every Si MOSFET is connected to a source bus; a gate driver comprising a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver; a gate drive output of the low-side driver being connected to the gate of every Si MOSFET through a first gate drive circuit comprising a gate resistor to provide a gate drive of a first voltage range for driving the plurality of Si MOSFETs; a gate drive output of the high-side driver being connected to the gate of every GaN power transistor through a second gate drive circuit comprising a gate resistor and a voltage level shift circuit to provide a gate drive of a second voltage range, different from the first voltage range, for driving the plurality of GaN power transistors.

16. The power semiconductor switching stage of claim 15 wherein, for a power supply voltage V.sub.DD, said first voltage range for driving the plurality of Si MOSFETs is in a range from 0V to V.sub.DD, and the second voltage range for driving the plurality of GaN power transistors is level shifted to provide a negative turn-off gate voltage and a positive turn-on gate voltage.

17. A power semiconductor switching stage comprising: a hybrid power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein: the high-side switch is implemented with at least one transistor, wherein every transistor of the high-side switch is a GaN power transistor, having a drain, a source and a gate; and the low-side switch is implemented with at least one transistor, wherein every transistor of the low-side switch is a Si MOSFET having a drain, a source and a gate; the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a phase node, the drain of every Si MOSFET is connected to the phase node, and the source of every Si MOSFET is connected to a source bus; a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver; a gate drive output of the low-side driver being connected to the gate of every Si MOSFET of the low-side switch through a first gate drive circuit comprising a first gate resistor to provide a gate drive of a first voltage range for driving every Si MOSFET; a gate drive output of the high-side driver being connected to the gate of every GaN power transistor of the high-side switch through a second gate drive circuit comprising a second gate resistor and a voltage level shift circuit to provide a gate drive of a second voltage range for driving every GaN power transistor; wherein for a supply voltage V.sub.DD, said first voltage range for driving every Si MOSFET is in a range from 0V to V.sub.DD, and the second voltage range for driving every GaN power transistor is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a circuit schematic for a hybrid power stage comprising a hybrid Si—GaN half-bridge and driver circuit of an embodiment;

(2) FIG. 2 shows an example gate driver circuit comprising a level shift circuit of the embodiment shown in FIG. 1;

(3) FIG. 3 shows a table with component values for the gate driver circuit of FIG. 2 selected for driving an example GaN-HEMT;

(4) FIGS. 4 and 5 shows example waveforms for the gate driver circuit of FIG. 2;

(5) FIG. 6 shows an example plot of the inductor current of each phase of an example four-phase half-bridge power stage, as a function of time;

(6) FIG. 7 shows plots of switching energy losses E.sub.on and E.sub.off as a function of drain current I.sub.d for a hybrid power stage comprising a hybrid Si—GaN half-bridge and driver circuit of an example embodiment;

(7) FIG. 8 shows a data table comparing performance of power stages comprising a GaN half-bridge, a hybrid Si—GaN half-bridge, and a Si half-bridge, for switching frequencies of 50 kHz, 100 kHz and 200 kHz.

(8) The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, of some embodiments of the invention, which description is by way of example only.

DETAILED DESCRIPTION

(9) A circuit schematic for a power stage comprising a hybrid Si—GaN half-bridge and driver circuit is shown in FIG. 1. The high-side switch 1 (HSS) of the half-bridge comprises a GaN power transistor, such as a GaN HEMT and the low-side switch 2 (LSS) comprises a Si MOSFET. Of the two switches of a half-bridge, the high-side switch is used for hard switching and the low-side switch is used for soft switching. Thus, in this design, the GaN HEMT is used for hard switching and the Si MOSFET for soft switching. Since the gate voltage V.sub.GS requirements for driving the GaN HEMT and the Si MOSFET are different, the gate driver circuit 100 is configured to provide suitable gate drive signals for each of the GaN HEMT and the Si MOSFET from a single power source, e.g. a 12V power supply.

(10) The gate driver circuit 100 comprises a half bridge driver 102, which may be a standard 12V MOSFET driver. The gate driver may be integrated with a driver controller. The output of the low-side driver L.sub.O is connected through a gate driver circuit, comprising a first gate resistor 108 (R.sub.G2), to the gate of the Si MOSFET to provide a gate drive voltage in a first gate voltage range based on the supply voltage V.sub.DD, e.g. 0 to 12V. The output of the high-side driver Ho is connected through a gate driver circuit comprising a second gate resistor 106 (R.sub.G1) and a level shift circuit 104. For example, as illustrated the level shift circuit may comprise a GaN Systems EZDrive™ circuit comprising a capacitor Coo with parallel resistor R.sub.DD1, which are connected between the gate resistor R.sub.G1 and the gate of the GaN HEMT, and a clamp circuit, e.g. comprising a Zener diode Zoo′ and diode Dom, for clamping the turn-in and turn-off gate drive voltages. The EZDrive circuit provides a drive voltage level shift. For example, when a negative gate voltage is to be used for turn-off of the GaN HEMT, by appropriate selection of components of the EZDrive circuit, a required gate drive voltage for the GaN HEMT, e.g. −6V to +6V can be generated by a voltage level shift from the 0-12V power supply voltage. The low-side driver circuit provides a gate drive voltage of e.g. 0V to 12V, i.e. without level shift, for the Si MOSFET through gate resistor R.sub.G2. FIG. 2 shows an enlarged view of the gate drive circuit with level shift 104 for driving the GaN HEMT. FIG. 3 shows some example component values for driving the GaN HEMT, and FIGS. 4 and 5 shows example waveforms.

(11) This gate driver circuit enables a standard MOSFET driver to provide a low-side gate drive of a first voltage range for driving the Si MOSFET, and a high-side gate drive of a second voltage range for driving the GaN power transistor. For example, the first voltage range for driving the Si-MOSFET is a range from 0V to V.sub.DD, and the second voltage range for driving the GaN-HEMT is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.

(12) By way of example only, test results are presented for a four-phase half-bridge for a Si—GaN hybrid half-bridge wherein the high-side switch comprises a GaN Systems GS61008P GaN HEMT and the low-side switch comprises an Infineon OptiMOS™5 Si MOSFET. The GS61008P GaN HEMT has an on-state resistance R.sub.on of 7 mΩ. A 1.2 mΩ Si MOSFET was selected for the low-side switch. These devices are rated for 100V operation. As an example, the total power of the four-phase half-bridge is 3.5 kW, with an input voltage Vin of 48V, and an output voltage V.sub.o of 13.6V, and an inductance of 6 μH, for switching frequencies of 50 kHz, 100 kHz and 200 kHz. FIG. 6 shows an example waveform for the inductor current of one phase as a function of time for a switching frequency of 50 kHz.

(13) FIG. 7 shows example test results for the on-switching energy loss and the off-switching energy loss for a Si—GaN hybrid half-bridge comprising a GS61008T GaN HEMT and an OptiMOS BSC070N10NS5 Si MOSFET, for test conditions of V.sub.DS=50V, R.sub.Gon=4.7Ω and R.sub.Goff=1Ω. A GaN HEMT having an on-resistance R.sub.DSon of 7 mΩ has about one third of switching energies E.sub.on and E.sub.off compared to a Si MOSFET of the same on-resistance. Compared with a 2.1 mΩ GaN HEMT, a 7 mΩ GaN HEMT will have switching energies about 10 times smaller.

(14) The test results for the Si—GaN hybrid half-bridge are compared with the test results for a pure GaN implementation using GS61008P GaN HEMTs for both the high-side and low-side switches, and a pure Si implementation using OptiMOS5 Si MOSFETs for both the high-side and low-side switches (2.1 mΩ and 1.2 mΩ). Some example test data are shown in the table in FIG. 8 to compare the Si—GaN hybrid half-bridge performance with the pure GaN and pure Si implementations, for different switching frequencies of 50 kHz, 100 kHz and 200 kHz. These results demonstrate that the Si—GaN hybrid solution combines the advantages of Si and GaN and offers best performance, in terms of total losses at each of these switching frequencies. Relative to a pure GaN implementation, the pure Si implementation has higher on-switching and off-switching energies E.sub.on and E.sub.off but offers significantly lower conduction losses. The Si—GaN hybrid solutions offers an E.sub.off of 0.86 W, an E.sub.on of 2.23 W and conduction losses of 12.02 W.

(15) For this 100V hybrid Si—GaN half-bridge application it is demonstrated that the reverse recovery of the 100V OptiMOS Si MOSFET is acceptable and use of the Si MOSFET for freewheeling does not significantly compromise the performance of the GaN HEMT. Use of a Si MOSFET for freewheeling substantially reduces the system cost for power stages comprising half-bridge and full-bridge switching topologies.

(16) Although the GaN HEMT and Si MOSFET have different drive voltage V.sub.GS requirements, a low cost driver circuit is disclosed which uses a single power supply, e.g. 0 to 12V, for generating a required gate drive voltages with a positive turn-on voltage and a negative turn-off voltage for the GaN HEMT, e.g. −6V to +6V for the GaN HEMT, and a conventional 0 to 12V gate drive for the Si MOSFET.

(17) This gate driver circuit has applications for power switching devices wherein a high-side switch comprises a GaN power transistor and a low-side switch comprises a Si MOSFET, e.g. half-bridge and full-bridge power switching stages, which offer at least one of improved performance and lower cost. The low-side switch may comprise a plurality of Si MOSFETs connected in parallel. The high-side switch may comprise a plurality of GaN power transistors connected in parallel.

(18) Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims.