High electron mobility transistor with trench isolation structure capable of applying stress and method of manufacturing the same

Abstract

A method of fabricating high electron mobility transistor, including the steps of providing a substrate with active areas, forming a buffer layer, a channel layer and a barrier layer sequentially on the substrate and gate, source and drain on the barrier layer, forming a trench surrounding the channel layer and the barrier layer, and forming a trench isolation structure in the trench, wherein the trench isolation structure applies stress on the channel layer and the barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

Claims

1. A method of fabricating high electron mobility transistor, comprising: providing a substrate with active areas; forming a buffer layer, a channel layer and a barrier layer sequentially on said substrate, and forming gate, source and drain on said barrier layer; forming a trench surrounding said channel layer and said barrier layer; and forming a trench isolation structure in said trench, wherein said trench isolation structure applies stress on said channel layer and said barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of said high electron mobility transistor, wherein said high electron mobility transistor is n-type high electron mobility transistor, and said stress applied by said trench isolation structure is compressive stress, and an area of said active area at said source is larger than an area of said active area at said gate and is larger than an area of said active area at said drain.

2. A method of fabricating high electron mobility transistor, comprising: providing a substrate with active areas; forming a buffer layer, a channel layer and a barrier layer sequentially on said substrate, and forming gate, source and drain on said barrier layer; forming a trench surrounding said channel layer and said barrier layer; and forming a trench isolation structure in said trench, wherein said trench isolation structure applies stress on said channel layer and said barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of said high electron mobility transistor, wherein said high electron mobility transistor is n-type high electron mobility transistor, and said stress applied by said trench isolation structure is tensile stress, and an area of said active area at said source is smaller than an area of said active area at said gate and is smaller than an area of said active area at said drain.

3. A method of fabricating high electron mobility transistor, comprising: providing a substrate with active areas; forming a buffer layer, a channel layer and a barrier layer sequentially on said substrate, and forming gate, source and drain on said barrier layer; forming a trench surrounding said channel layer and said barrier layer; and forming a trench isolation structure in said trench, wherein said trench isolation structure applies stress on said channel layer and said barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of said high electron mobility transistor, wherein said high electron mobility transistor is p-type high electron mobility transistor, and said stress applied by said trench isolation structure is tensile stress, and an area of said active area at said source is larger than an area of said active area at said gate and is larger than an area of said active area at said drain.

4. A method of fabricating high electron mobility transistor, comprising: providing a substrate with active areas; forming a buffer layer, a channel layer and a barrier layer sequentially on said substrate, and forming gate, source and drain on said barrier layer; forming a trench surrounding said channel layer and said barrier layer; and forming a trench isolation structure in said trench, wherein said trench isolation structure applies stress on said channel layer and said barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of said high electron mobility transistor, wherein said high electron mobility transistor is p-type high electron mobility transistor, and said stress applied by said trench isolation structure is compressive stress, and an area of said active area at said source is smaller than an area of said active area at said gate and is smaller than an area of said active area at said drain.

5. The method of fabricating high electron mobility transistor of claim 1, wherein the material of said buffer layer is aluminum nitride (AlN) and gallium nitride (GaN), and the material of said channel layer is gallium nitride (GaN), and the material of said barrier layer is aluminum gallium nitride (AlGaN), and the material of said trench isolation is silicon nitride.

6. The method of fabricating high electron mobility transistor of claim 1, wherein said trench isolation structure is further adjacent and surrounds said active area and connects downward to an insulating layer under said active area.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

(2) FIGS. 1-4 are schematic cross-sections illustrating the steps of fabricating a high electron mobility transistor in accordance with the preferred embodiment of present invention;

(3) FIG. 5 is a schematic cross-section illustrating the structure of a p-type high electron mobility transistor in accordance with the preferred embodiment of present invention; and

(4) FIGS. 6-11 are schematic plan views illustrating n-type high electron mobility transistors and p-type high electron mobility transistors matching the trench isolation structures with different stress property.

(5) It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

(6) The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. The absolute and relative sizes of the components are presented in an exaggeration manner.

(7) Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

(8) Embodiments for a high electron mobility transistor (HEMT) and method for fabricating the same are provided. FIGS. 1-4 show cross-sectional representations of various stages of fabricating a high electron mobility transistor 100 in accordance with some embodiments of the disclosure. The high electron mobility transistor 100 is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of using a doped region as the channel, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs).

(9) Please refer to FIG. 1. First, a substrate 102 is provided. The substrate 102 may be made of silicon (Si) or other semiconductor materials. In some embodiments, the substrate 102 is a silicon wafer. In some embodiments, the substrate 102 is a silicon substrate having <100> lattice structure. An insulating layer 104 is formed on the substrate 102. The insulating layer 104 may be a silicon oxide layer, to reduce parasitic capacitance of overlying devices. A semiconductor layer 106 is formed on the insulating layer 104. In some embodiment, the semiconductor layer 106 is a silicon layer having <111> lattice structure. The Si <111> layer provides an optimal lattice matching with overlying layers, such as a gallium nitride (GaN) layer. In some embodiments, the semiconductor layer 106 is made of a compound semiconductor such as silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the semiconductor layer 106 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

(10) Next, refer again to FIG. 1. A buffer layer 108 is formed over the semiconductor layer 106, in accordance with some embodiments of the disclosure. The buffer layer 108 is configured to define a high resistivity layer for increasing the breakdown voltage of the high electron mobility transistor 100. The buffer layer 108 has a resistivity higher than a resistivity of the channel layer to be formed in later process.

(11) In some embodiments, the buffer layer 108 includes one or more Group III-V compound layer. Examples of Group III-V compound layers include, but are not limited to, gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) and indium aluminum gallium nitride (InAlGaN). In some embodiments, the buffer layer 108 includes a dopant to achieve a predetermined high resistivity. In some embodiments, the dopant is a p-type dopant. In some embodiments, the buffer layer 108 includes GaN doped with the p-type dopant. Examples of the p-type dopant include, but are not limited to, carbon (C), iron (Fe), magnesium (Mg) or zinc (Zn). In some embodiment, the buffer layer 108 is formed by an epitaxial growth process. Examples of epitaxial growth processes include, but are not limited to, a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, and a hydride vapor phase epitaxy (HVPE) process.

(12) In addition, before the buffer layer 108 is formed, a nucleation layer and a transition layer (not shown) may be formed sequentially on the semiconductor layer 106. The nucleation layer is used to compensate for the mismatch in lattice structures and/or in coefficient of thermal expansion between the semiconductor layer 106 and the overlying layer. In some embodiments, the nucleation layer includes a step-wise change in lattice structure. The material of nucleation layer may include aluminum nitride (AlN). The transition layer is used to facilitate gradual the step-wise changes of the lattice structure and the coefficient of thermal expansion between the semiconductor layer 106 and the overlying layer (e.g. the buffer layer 108). In some embodiments, the transition layer includes a graded aluminum gallium nitride layer (Al.sub.xGa.sub.1-xN), wherein X is the aluminum content ratio in the aluminum gallium constituent, and X is in a range from 0 to 1. In some embodiments, the graded aluminum gallium nitride layer includes multilayer structure, wherein each layer has a decreased X ratio (from a bottom layer adjoining the nucleation layer to a top layer adjoining the buffer layer 108). In some embodiments, the graded aluminum gallium nitride layer has a continuous gradient of the X ratio. The nucleation layer and the transition layer may be formed by an epitaxial growth process. Examples of epitaxial growth processes include, but are not limited to, a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, and a hydride vapor phase epitaxy (HVPE) process. For the purpose of simplicity and clarity, the nucleation layer and the transition layer will not be shown in figures.

(13) Thereafter, refer again to FIG. 1. A channel layer 110 is formed over the buffer layer 108, in accordance with the embodiment of the disclosure. The channel layer 110 has a resistivity lower than the buffer layer 108, for improving the current performance of HEMT 100 device. In some embodiments, the channel layer 110 includes one or more Group III-V compound layers. Examples of Group III-V compound layers include, but are not limited to, GaN, AlGaN, InGaN and InAlGaN. In some embodiments, the channel layer 110 includes alternatingly arranged p-doped and n-doped Group III-V compound layers. In some embodiments, the channel layer 110 includes a p-doped GaN layer. Examples of the p-type dopant in the p-doped GaN layer include, but are not limited to, carbon (C), iron (Fe), magnesium (Mg) and zinc (Zn). Alternatively, the channel layer 110 may include an un-doped GaN layer. In some embodiments, the channel layer 110 is formed by an epitaxial growth process. Examples of epitaxial growth processes include, but are not limited to, a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, and a hydride vapor phase epitaxy (HVPE) process.

(14) Thereafter, as shown in FIG. 1, a barrier layer 112 is formed over the channel layer 110, in accordance with some embodiments of the disclosure. The barrier layer 112 is configured to cause a two dimensional electron gas (2DEG) 114 to be formed in the channel layer 110 along an interface between the channel layer 110 and the barrier layer 112. A heterojunction is formed between the barrier layer 112 and the channel layer 110. A band gap discontinuity exists between the barrier layer 112 and the channel layer 110. In some embodiments, the band gap of the barrier layer 112 is greater than the band gap of the channel layer 110, thereby creating a thin layer of highly mobile conducting electrons, i.e., the two dimensional electron gas 114 in the channel layer 110, adjacent the interface with the barrier layer 112. The electrons in the two dimensional electron gas 114 are charge carriers in the channel layer 110.

(15) Due to the naturally occurring two dimensional electron gas 114 without gate structure, the HEMT 100 would be conductive without the application of a voltage to the gate electrode. Therefore, the HEMT 100 would be a normally-ON device in a negative threshold voltage. Such a normally-ON state is a design concern in power applications where it is desirable to prevent, or substantially inhibit, the current from flowing in or through the HEMT 100. In some embodiments, in order to convert a normally-ON HEMT device to a normally-OFF HEMT device, a gate structure is configured over the barrier layer 112 to deplete the two dimensional electron gas 114 under the gate structure. The details will be described in later embodiments.

(16) In some embodiments, the barrier layer 112 includes one or more Group III-V compound layers which are different in composition from the Group III-V compound layers of the channel layer 110. Examples of these materials include aluminum nitride (AlN), graded aluminum gallium nitride (Al.sub.yGa.sub.(1-y)N) (wherein y is the aluminum content ratio in AlGaN, and y is in a range from 0 to 1), or a combination thereof. In some embodiments, the barrier layer 112 is formed by an epitaxial growth process. Examples of epitaxial growth processes include, but are not limited to, a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, and a hydride vapor phase epitaxy (HVPE) process.

(17) Thereafter, as shown in FIG. 2, a p-doped gallium nitride (p-GaN) layer 116 is formed over the barrier layer 112, in accordance with some embodiments of the disclosure. In some embodiments, the p-GaN layer 116 has a constant concentration. Examples of the p-type dopant in the p-doped GaN layer 116 includes, but are not limited to, carbon (C), iron (Fe), magnesium (Mg) and zinc (Zn). In some embodiments, the p-GaN layer 116 may be formed by a epitaxial growth process. Examples of epitaxial growth processes include, but are not limited to, a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, and a hydride vapor phase epitaxy (HVPE) process. In other embodiment, the p-GaN layer 116 may be replaced with a p-AlGaN layer. Other additional p-GaN layers with different doping concentration may also be formed over the p-GaN layer 116 to increase the gate operation voltage of HEMT 100.

(18) The operations for forming the buffer layer 108, the channel layer 110, the barrier layer 112 and the p-GaN layer 116 may be in-situ performed in the same process chamber without removing to another chamber, thereby saving cost and reducing pollution.

(19) Refer again to FIG. 2. After the p-GaN layer 116 is formed, a gate electrode 118 is formed over the p-GaN layer 116. In some embodiments, gate electrode 118 includes a conductive material layer that includes a refractory metal or the respective compounds including, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), and tungsten (W). Alternatively, the gate electrode 118 includes nickel (Ni), gold (Au), copper (Cu), or the alloys thereof. The gate electrode 118 and the p-GaN layer 116 may be patterned through photolithographic and etching processes, and a gate dielectric layer or a dielectric passivation layer may be formed therebetween to increase the threshold voltage of HEMT 100. For the purpose of simplicity and clarity of description and drawing, the gate dielectric layer, the dielectric passivation layer and relevant processes would not be shown in the figures.

(20) Thereafter, as shown in FIG. 2, a source 120 and a drain 122 are formed respectively at two sides of the gate electrode 118 on the barrier layer 112. Therefore, the gate electrode 118, source 120, drain 122 and the carrier channel layer 110 form collectively the HEMT 100 structure. When a voltage is applied to gate electrode 118, the device current may be modulated. In some embodiments, source 120 and drain 122 may include one or more conductive materials, for example, Ti, Co, Ni, W, Pt, Ta, Pd, Mo, TiN, an AlCu alloy, and alloys thereof. The gate electrode 118, the source 12 and the drain 122 may be formed separately or simultaneously by deposition process and photolithographic and etch processes. The deposition process includes a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), a high density plasma CVD (HDPCVD), a metal organic CVD (MOCVD), a plasma enhanced CVD (PECVD), or other applicable processes.

(21) Please refer to FIG. 3. After the gate electrode 118, source 120 and drain 122 are formed, a trench 124 is formed surrounding the HEMT 100. In the embodiment of present invention, the trench 124 would define the active area in every HEMT 100. The trench 124 may be formed by using anisotropic etch process to etch through barrier layer 112, channel layer 110, buffer layer 108 and semiconductor layer 106 and stop at insulating layer 104 with the insulating layer 104 functions as an etch stop layer. In the embodiment of present invention, the dimension of active areas in various parts of the HEMT 100 would affect the threshold voltage of the device, which will be explained in later embodiments. Please note that, although the trench 124 in the figure is adjacent to source 120 and drain 122, the trench 124 may be separated from source 120 and drain 122 at a distance in other embodiments.

(22) Thereafter, as shown in FIG. 4 in accordance with the embodiment of the disclosure, a trench isolation structure 128 is formed in trench 124. The trench isolation structure 128 fills up entire trench 124 and connects downward to the underlying insulating layer 104, so that entire HEMT 100 is isolated by surrounding trench isolation structure 128 and underlying insulating layer 104, and the problems like cross-talk between transistors and backgating effect may be solved efficiently. More particularly, in the embodiment of the disclosure, the trench isolation structure 128 is designed to be adjacent to and surrounds the channel layer 110 and the barrier layer 112 of HEMT 100. In this way, the trench isolation structure 128 may apply stress on channel layer 110 and barrier layer 112 to modify the two dimensional electron gas therebetween, thereby further controlling the threshold voltage of the transistor. The principle of voltage modification is that the concentration of two dimensional electron gas may be modified by changing total polarization vector of piezoelectric components in the barrier layer 112, thereby further modifying the current flowing through the transistor, and the threshold voltage of the transistor may be, therefore, modified.

(23) In the example of n-type HEMT 100, the current flowing through the transistor may be decreased by applying compressive stress on channel layer 110 and barrier layer 112 to reduce the concentration of two dimensional electron gas therebetween, thereby achieving the effect of a normally-OFF transistor. On the other hand, in the example of p-type HEMT, two dimension hole gas (2DHG) is the carrier channel of p-type HEMT. Accordingly, the current flowing through the transistor may be decreased by applying tensile stress on channel layer 110 to reduce the concentration of two dimensional hole gas, thereby achieving the effect of a normally-OFF transistor.

(24) In the embodiment of present invention, the material of trench isolation structure 128 would decide the stress applied on the HEMT 100 is compressive or tensile. In this regard, silicon nitride is an excellent material. Since the cell parameter of silicon nitride is different from the one of elementary silicon, the grown silicon nitride film may generate tensile stress or compressive stress based on its deposition method, especially when using plasma enhanced CVD that the deposition parameter may be adjusted to determine whether it is compressive stress or tensile stress applied on the AlGaN layer.

(25) In other embodiment, the aforementioned trench isolation structure 128 may be formed before gate electrode 118, source 120 and drain 122, depending on the actual process requirement or design.

(26) Please refer now to FIG. 5, which is a schematic cross-section illustrating a p-type HEMT 200 in accordance with the embodiment of the present invention. In the embodiment of the present invention, the structure of p-type HEMT 200 is similar to the aforementioned n-type HEMT 100. The difference therebetween lies in an additional unintentionally doped (UID) GaN layer 130 that is formed between p-doped GaN layer 116 and barrier layer 112 in the p-type HEMT 200. With this design, a two dimension hole gas 132 is generated at the interface between the unintentionally doped GaN layer 130 and the barrier layer 112. For the p-type HEMT 200 using two dimension hole gas 132 as a carrier channel, the current flowing through the transistor may be decreased by forming trench isolation structure 128 capable of applying tensile stress to reduce the concentration of two dimension hole gas 132, thereby achieving the effect of a normally-OFF transistor.

(27) Variations of active areas in n-type and p-type HEMTs will be explained hereinbelow in following embodiment. FIGS. 6-11 are schematic plan views illustrating n-type and p-type HEMTs matching trench isolation structures with different stress property. In actual implementation, these various matching approaches may be utilized to achieve desired effect of modifying (increasing or decreasing) the threshold voltage of transistors. Please note that all following embodiments are implemented based on the assumption that the gate electrode 118, the source 120 and the drain 122 have same area.

(28) First, please refer to FIG. 6. In the condition that n-type HEMT 100 matching the trench isolation structure 128a with compressive stress, the area of active area 126 at source 120 may be designed to be larger than the area of active area 126 at gate electrode 118 or at drain 122. In this way, since the trench isolation structure 128a providing compressive stress is farther from the source 120, the compressive stress taken by the source 120 would be smaller than the compressive stress taken by the gate electrode 118 or drain 122, so that the concentration of two dimension electron gas at source 120 would be greater than the one at drain 122. The current flowing through the transistor is thereby increased.

(29) On the other hand, in the condition that n-type HEMT 100 matching the trench isolation structure 128b with tensile stress, as shown in FIG. 7, the area of active area 126 at source 120 may be designed to be smaller than the area of active area 126 at gate electrode 118 or at drain 122. In this way, since the trench isolation structure 128b providing tensile stress is relatively close to the source 120, the tensile stress taken by the source 120 would be larger than the tensile stress taken by the gate electrode 118 or drain 122, so that the concentration of two dimension electron gas at source 120 would be greater than the one at drain 122. The current flowing through the transistor is thereby increased.

(30) Regarding p-type HEMT 200, please refer to FIG. 8. In the condition that trench isolation structure 128a provides compressive stress, the area of active area 126 at source 120 may be designed to be smaller than the area of active area 126 at gate electrode 118 or at drain 122. In this way, since the trench isolation structure 128a providing compressive stress is relatively close to the source 120, the compressive stress taken by the source 120 would be larger than the compressive stress taken by the gate electrode 118 or drain 122, so that the concentration of two dimension hole gas at source 120 would be greater than the one at drain 122. The current flowing through the transistor is thereby increased.

(31) On the other hand, in the condition that p-type HEMT 200 matching the trench isolation structure 128b with tensile stress, as shown in FIG. 9, the area of active area 126 at source 120 may be designed to be smaller than the area of active area 126 at gate electrode 118 or at drain 122. In this way, since the trench isolation structure 128b providing tensile stress is farther from the source 120, the tensile stress taken by the source 120 would be smaller than the tensile stress taken by the gate electrode 118 or drain 122, so that the concentration of two dimension hole gas at source 120 would be greater than the one at drain 122. The current flowing through the transistor is thereby increased.

(32) In other embodiment, different stresses may be simultaneously applied on the source 120 and the gate electrode 118 and drain 122 of single transistor to achieve desired effect. For example, by forming trench isolation structures capable of providing tensile stress and compressive stress respectively at source 120 and at gate 118 or source 120, the effect of increasing current through the transistor may be further improved.

(33) In the present invention, the aforementioned embodiments may be applied in combination. Please refer to FIG. 10. In the condition that trench isolation structure 128a provides compressive stress, n-type HEMT 100 and p-type HEMT 200 may be disposed simultaneously in the trench isolation structure 128a, wherein the area of active area 126 at source 120 of the n-type HEMT 100 may be designed to be larger than the area of active area 126 at gate electrode 118 or at drain 122 of the n-type HEMT 100, while the area of active area 126 at source 120 of the p-type HEMT 200 may be designed to be smaller than the area of active area 126 at gate electrode 118 or at drain 122 of the p-type HEMT 200. This design may make both currents flowing through the n-type HEMT 100 and the p-type HEMT 200 increase.

(34) On the other hand, In the condition that trench isolation structure 128b provides tensile stress, n-type HEMT 100 and p-type HEMT 200 may be disposed simultaneously in the trench isolation structure 128b, wherein the area of active area 126 at source 120 of the n-type HEMT 100 may be designed to be smaller than the area of active area 126 at gate electrode 118 or at drain 122 of the n-type HEMT 100, while the area of active area 126 at source 120 of the p-type HEMT 200 may be designed to be larger than the area of active area 126 at gate electrode 118 or at drain 122 of the p-type HEMT 200. This design may make both currents flowing through the n-type HEMT 100 and the p-type HEMT 200 increase.

(35) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.