High breaking capacity chip fuse

Abstract

A high breaking capacity chip fuse including a bottom insulative layer, a first intermediate insulative layer, a second intermediate insulative layer, and a top insulative layer disposed in a stacked arrangement in the aforementioned order, a fusible element disposed between the first and second intermediate insulative layers and extending between electrically conductive first and second terminals at opposing longitudinal ends of the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer, wherein the first and second intermediate insulative layers are formed of porous ceramic.

Claims

1. A method of forming a high breaking capacity chip fuse comprising: providing a bottom insulative layer, a first intermediate insulative layer, a second intermediate insulative layer, and a top insulative layer disposed in a stacked arrangement; and disposing a fusible element between the first and second intermediate insulative layers, the fusible extending between electrically conductive first and second terminals at opposing longitudinal ends of the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer, wherein the first and second intermediate insulative layers entirely shield the bottom and top insulative layers from the fusible element; wherein each of the first and second intermediate insulative layers is formed of a single, unitary layer of ceramic having a plurality of hollow pores encased therein.

2. The method of claim 1, wherein the fusible element is one of a wire, a ribbon, a metal link, a spiral wound wire, a film, and electrically conductive core deposited on a substrate.

3. The method of claim 1, wherein the first intermediate insulative layer and the second intermediate insulative layer are more porous than the bottom insulative layer and the top insulative layer.

4. The method of claim 3, wherein the first intermediate insulative layer and the second intermediate insulative layer are at least 25% more porous than the bottom insulative layer and the top insulative layer.

5. The method of claim 3, wherein the first intermediate insulative layer and the second intermediate insulative layer are at least 50% more porous than the bottom insulative layer and the top insulative layer.

6. The method of claim 3, wherein the first intermediate insulative layer and the second intermediate insulative layer are at least 75% more porous than the bottom insulative layer and the top insulative layer.

7. The method of claim 3, wherein the first intermediate insulative layer and the second intermediate insulative layer are at least 100% more porous than the bottom insulative layer and the top insulative layer.

8. The method of claim 1, wherein the bottom insulative layer and the top insulative layer are formed of one of FR-4, glass, and ceramic.

9. The method of claim 1, further comprising forming the porous ceramic by mixing particles of one or more fugitive materials into a ceramic and then firing the ceramic to burn the particles of fugitive material away, leaving hollow pores within the ceramic.

10. The method of claim 9 wherein the fugitive materials include at least one of carbon and corn starch.

11. The method of claim 1, further comprising flatly bonding the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer to one another with an electrically insulating adhesive.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) By way of example, various embodiments of the disclosed system will now be described, with reference to the accompanying drawings, wherein:

(2) FIG. 1A is a perspective view illustrating a high breaking capacity chip fuse in accordance with an exemplary embodiment of the present disclosure;

(3) FIG. 1B is cross sectional view illustrating the high breaking capacity chip fuse shown in FIG. 1A.

DETAILED DESCRIPTION

(4) A high breaking capacity chip fuse in accordance with the present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the high breaking capacity chip fuse are presented. It will be understood, however, that the high breaking capacity chip fuse described below may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey certain exemplary aspects of the high breaking capacity chip fuse to those skilled in the art.

(5) Referring to FIGS. 1A and 1B, a perspective view and a cross sectional side view illustrating a high breaking capacity chip fuse 10 (hereinafter “the fuse 10”) in accordance with an exemplary, non-limiting embodiment of the present disclosure are shown. The fuse 10 may include a bottom insulative layer 12, a first intermediate insulative layer 14, a second intermediate insulative layer 16, and a top insulative layer 18 disposed in a stacked arrangement in the aforementioned order. The layers 12-18 may be flatly bonded to one another, such as with epoxy or other electrically insulating adhesive or fasteners. While the fuse 10 is shown and described herein as having only two intermediate insulative layers (the first and second intermediate insulative layers 14, 16), it is contemplated that the fuse 10 may be provided with additional intermediate insulative layers without departing from the scope of the present invention. For example, the fuse 10 may be provided with a third intermediate insulative layer disposed between the bottom insulative layer 12 and the first intermediate insulative layer 14, and/or a fourth intermediate insulative layer disposed between the top insulative layer 18 and the second intermediate insulative layer 16. The present disclosure is not limited in this regard.

(6) The fuse 10 may further include a fusible element 20 disposed between the first and second intermediate insulative layers 14, 16 (e.g., sandwiched between the first and second intermediate insulative layers 14, 16) and extending between electrically conductive first and second terminals 22, 24 at opposing longitudinal ends of the layers 12-18. The fusible element 20 may be formed of an electrically conductive material, including, but not limited to, tin or copper, and may be formed as a wire, a ribbon, a metal link, a spiral wound wire, a film, and electrically conductive core deposited on a substrate, etc. The fusible element 20 may be configured to melt and separate upon the occurrence of a predetermined fault condition in the fuse 10, such as an overcurrent condition in which an amount of current exceeding a predefined maximum current (i.e., a “rating” of the fuse 10) flows through the fusible element 20. As will be appreciated by those of ordinary skill in the art, the size, shape, configuration, and material of the fusible element 20 may all contribute to the rating of the fuse 10.

(7) The bottom insulative layer 12 and the top insulative layer 18 of the fuse 10 may be formed of any suitable dielectric material, including, but not limited to, FR-4, glass, ceramic (e.g., low temperature co-fired ceramic), etc., and may be generally non-porous. The first and second intermediate insulative layers 14, 16 of the fuse 10 may be formed of porous ceramic (e.g., low temperature co-fired ceramic) having pluralities of hollow pores 26 formed therein. The porous ceramic of the first and second intermediate insulative layers 14, 16 may be made by mixing granules or particles of one or more fugitive materials (e.g., carbon, corn starch, etc.) into the ceramic prior to firing/curing of the ceramic. During firing/curing, the particles of fugitive material may be burned away, leaving the hollow pores 26 within the ceramic. The present disclosure is not limited in this regard.

(8) In various embodiments, the first and second intermediate insulating layers 14, 16 may have porosities greater than the porosities of the bottom and top insulative layers 12, 18 of the fuse 10. In a particular embodiment, the first and second intermediate insulating layers 14, 16 may be 25% more porous than the bottom and top insulative layers 12, 18 of the fuse 10. In another embodiment, the first and second intermediate insulating layers 14, 16 may be 50% more porous than the bottom and top insulative layers 12, 18 of the fuse 10. In another embodiment, the first and second intermediate insulating layers 14, 16 may be 75% more porous than the bottom and top insulative layers 12, 18 of the fuse 10. In another embodiment, the first and second intermediate insulating layers 14, 16 may be 100% more porous than the bottom and top insulative layers 12, 18 of the fuse 10. The present disclosure is not limited in this regard.

(9) During operation of the fuse 10, if an overcurrent condition causes the fusible element 20 to melt and produce an explosion, the first and second intermediate insulative layers 14, 16, which are relatively weaker and more prone to breaking than the bottom insulative layer 12 and the top insulative layer 18 due to the provision of the pores 26, may fracture and may absorb the energy of the explosion (e.g., in the manner of crumple zones in an automobile), thereby preventing much of the energy from the explosion from being communicated to the bottom insulative layer 12 and the top insulative layer 18. Additionally, the vaporized material of the melted fusible element 20 may be rapidly cleared into the pores 26 of the fractured first and second intermediate insulative layers 14, 16, thereby preventing such vaporized material from feeding and prolonging electrical arcing across separated portions of the fusible element 20. Thus, the risk of the fuse 10 being ruptured is mitigated by the fracturing of the first and second intermediate insulative layers 14, 16, and the breaking capacity of the fuse 10 may therefore be relatively greater than the breaking capacity of chip fuses that lack the porous first and second intermediate insulative layers 14, 16 of the fuse 10 of the present disclosure.

(10) As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to “one embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

(11) While the present disclosure makes reference to certain embodiments, numerous modifications, alterations and changes to the described embodiments are possible without departing from the sphere and scope of the present disclosure, as defined in the appended claim(s). Accordingly, it is intended that the present disclosure not be limited to the described embodiments, but that it has the full scope defined by the language of the following claims, and equivalents thereof.