Abstract
The present disclosure relates to a front-end system for a radio device comprising: a charge generator circuit arranged for receiving a digital baseband signal, a first converter circuit arranged for calculating at least one charge value based on the digital baseband signal, a second converter circuit arranged for converting the at least one charge value into at least one electrical charge, and a modulator circuit arranged for generating a radio frequency signal based on the at least one electrical charge and at least one local oscillator signal.
Claims
1. A front-end system for a radio device comprising: a charge generator circuit arranged for receiving a digital baseband signal, and comprising a first converter circuit arranged for calculating at least one charge value based on the digital baseband signal, wherein the at least one charge value comprises a digital number, and a second converter circuit arranged for converting the at least one charge value into at least one electrical charge, and a modulator circuit arranged for generating a radio frequency signal based on the at least one electrical charge and at least one local oscillator signal.
2. The front-end system for a radio device according to claim 1, further comprising a charge reservoir connected between the second converter circuit and the modulator circuit, and wherein the charge reservoir comprises at least one capacitor.
3. The front-end system for a radio device according to claim 2, wherein the second converter circuit is arranged for converting the at least one charge value into the at least one electrical charge by connecting at least one bank of switchable capacitors to the charge reservoir, the at least one bank of switchable capacitors being pre-charged to at least one pre-determined voltage.
4. The front-end system for a radio device according to claim 2, wherein the second converter circuit is arranged for converting the at least one charge value into the at least one electrical charge by connecting, for a predetermined period of time, at least one bank of switchable resistors between at least one pre-determined reference voltage and the charge reservoir.
5. The front-end system for a radio device according to claim 1, wherein the second converter circuit is arranged for converting the at least one charge value into the at least one electrical charge by generating at least one current for a pre-determined period of time.
6. The front-end system for a radio device according to claim 1, wherein the modulator circuit comprises at least one switch, and is arranged for generating a radio frequency signal by transferring the at least one electrical charge to an output load via the at least one switch controlled by the at least one local oscillator signal.
7. The front-end system for a radio device according to claim 6, wherein the output load comprises a capacitor.
8. The front-end system for a radio device according to claim 1, wherein the digital baseband signal is a differential quadrature baseband signal.
9. The front-end system for a radio device according to claim 1, where the modulator circuit receives four non-overlapping local oscillator signals, and is arranged for generating the radio frequency signal based on the at least one electrical charge and the four non-overlapping local oscillator signals.
10. The front-end system for a radio device according to claim 1, further comprising a control unit connected to an input of the modulator circuit, and arranged to control the first converter circuit so that the at least one charge value is calculated by taking into account the electrical charge available at the input of the modulator circuit.
11. A radio network comprising the front-end system for the radio device.
12. A radio network system comprising the radio device according to claim 11.
13. A method for operating a front-end system for a radio device, the method comprising: receiving, by a first converter circuit, a digital baseband signal; calculating, by the first converter circuit, at least one charge value based on the digital baseband signal, wherein the at least one charge value comprises a digital number; converting, by a second converter circuit, the at least one charge value into at least one electrical charge; filtering, by a switched-capacitor resistor comprising a charge-reservoir capacitor and the second converter circuit to improve out-of-band noise emission, the at least one electrical charge; and generating, by a modulator circuit, a radio frequency signal based on the at least one electrical charge and at least one local oscillator signal.
Description
BRIEF DESCRIPTION OF THE FIGURES
(1) For a better understanding of the present disclosure, some example embodiments are described below in conjunction with the appended figures and figures description, wherein:
(2) FIG. 1 illustrates a block diagram of a front-end system according to one embodiment of the present disclosure.
(3) FIG. 2 illustrates a block diagram of a front-end system according to one embodiment of the present disclosure.
(4) FIG. 3 illustrates a block diagram of a front-end system according to one embodiment of the present disclosure.
(5) FIG. 4 illustrates a detailed block diagram of differential quadrature front-end system according to one embodiment of the present disclosure.
(6) FIG. 5 illustrates example implementations of a second converter circuit according to some embodiments of the present disclosure.
(7) FIG. 6 illustrates an example implementation of a second converter circuit according to one embodiment of the present disclosure.
(8) FIG. 7 illustrates an example implementation of a second converter circuit according to one embodiment of the present disclosure.
(9) FIG. 8 illustrates an example implementation of a second converter circuit according to one embodiment of the present disclosure.
(10) FIG. 9 illustrates an example implementation of a second converter circuit according to one embodiment of the present disclosure.
(11) FIG. 10 illustrates a detailed block diagram of a differential quadrature front-end system according to one embodiment of the present disclosure.
(12) FIG. 11 illustrates a simplified schematic of a front-end system according to the present disclosure.
(13) FIG. 12 illustrates a timing diagram of the operation of the front-end system of FIG. 11 according to the present disclosure.
DETAILED DESCRIPTION
(14) The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.
(15) Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the disclosure can operate in other sequences than described or illustrated herein.
(16) Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the disclosure described herein can operate in other orientations than described or illustrated herein.
(17) The term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting of only components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B.
(18) Embodiments of the present disclosure will be explained with reference to the examples shown in FIG. 1 to FIG. 12.
(19) FIG. 1 shows a front-end system for a radio device 100 which is arranged to convert a digital baseband signal BB to a radio frequency signal RF, wherein conversion is achieved by employing the principle of a charge transfer. The front-end system comprises a charge generator circuit 10 which is arranged for receiving a digital baseband signal BB and for converting that digital baseband signal BB into an electrical charge Q. The charge generator circuit 10 comprises a first converter circuit 11 and a second converter circuit 12. The first converter circuit 11 is arranged for calculating the necessary charge value q based on the digital baseband signal BB. The second converter circuit 12 is arranged for converting that charge value q into an electrical charge Q, thereby converting the charge value q, which is in fact a digital number—to an analog charge Q. The digital number is calculated such that the RF signal represents the digital baseband signal. The electrical charge Q is then transferred to an output load ZRF via a modulator circuit 20 in accordance with a local oscillator signal LO. As a result, the charge transferred to the output load ZRF defines the radio-frequency signal RF. The modulator circuit 20 thus generates a radio frequency signal RF based on said charge Q and the LO signal. The RF signal may be then fed to the antenna via a pre-amplifier and a power amplifier (not shown in the figures).
(20) According to some embodiments, depending on the circuit connected to the output of the modulation circuit 20, the output load ZRF may be equivalent to a capacitive load, i.e. CRF. The output load ZRF would be equivalent to a capacitive load CRF in the example case where the modulator circuit 20 is connected to a pre-amplifier or a power amplifier.
(21) According to one embodiment, the front-end system 100 is provided with a charge reservoir 30 that comprises a capacitor C, connected between the second converter circuit 12 and the modulator circuit 20, as shown in FIG. 2 and FIG. 3. The charge reservoir 30 in combination with the second converter circuit 12 realizes a switched-capacitor resistor, which introduces an intrinsic first-order low-pass filter (LPF) in the signal path. As a result, the electrical charge Q is filtered before being fed to the input of the modulator circuit 20, which improves the out-of-band noise emission of the front-end system. The capacitor C may be larger, equal or smaller than the output capacitor CRF, i.e. the capacitance of C may be higher, equal or lower than the CRF's capacitance. For example, to provide sufficient out-of-band filtering, in a radio device operating in Frequency Division Duplex (FDD) mode and employing the front-end system according to the present disclosure, the capacitor C should be larger than the capacitor CRF. Further, depending on the specific out-of-band noise requirements, the capacitor C may be hundreds of times larger than the output capacitor CRF.
(22) The front-end system 100 will be described in more details below with reference to a differential quadrature implementation.
(23) FIG. 4 shows a block diagram of a differential quadrature implementation of a front-end system for a radio device according to some embodiments. Differential quadrature digital baseband BB signals are received by the front-end system and respectively fed to the input of the first generator circuit 11. The first generator circuit 11 calculates a charge value q.sub.NNN for each corresponding baseband signal BB.sub.NNN. The subscript NNN denotes the respective phase of each differential quadrature baseband signal. An alternative notation would be using multibit digital signals D.sub.1, D.sub.Q representing the respective in-phase and quadrature signals. Four charge values (i.e. q.sub.000, q.sub.090, q.sub.180, q.sub.270) are thus calculated representing the each respective phase of the BB signal. The second converter circuit 12 then converts each charge value q.sub.NNN to an electrical charge Q.sub.NNN (i.e. Q.sub.000, Q.sub.090, Q.sub.180, Q.sub.270). In this implementation, the first converter circuit 11 has four output nodes 2, each providing a charge value q.sub.NNN. The second converter circuit 12 is provided with four input nodes 2 arranged for receiving a charge values q.sub.NNN at each of its inputs and is provided with four output nodes 3 (herein also referred as baseband nodes) each arranged to provide an electrical charge Q.sub.NNN. Similarly, the modulator circuit 20 is provided with a first set of four inputs arranged for receiving the four electrical charges Q.sub.NNN and a second set of four inputs arranged for receiving four non-overlapping LO signals (i.e. LO.sub.000, LO.sub.090, LO.sub.180, LO.sub.270), i.e. with four LO signals having a 25% duty cycle. The modulator circuit 20 comprises four switches 21 (or transistors arranged to act as switches) arranged to receive a respective LO signal at one of its terminals and a respective charge Q.sub.NNN at its other input terminal. Each switch 21 is thus switched ON or OFF based on the respective LO signal. As a result, the modulator circuit 20 effectively transfers the respective electrical charge Q.sub.NNN to the output capacitor CRF by connecting sequentially and according to the LO signals each respective baseband node 3 to the output capacitor CRF. The charge Q.sub.NNN transferred during each respective LO phase to the output capacitor CRF effectively moves the voltage at the output capacitor CRF (e.g. VRF) from one value to another. As the electrical charge Q.sub.NNN needed to charge the output capacitor CRF during the respective LO.sub.NNN phase corresponds to the charge value q.sub.NNN, which in turn corresponds to the digital baseband signal, the voltage at the output capacitor CRF represents the modulated BB signal, i.e. the RF signal. The charge value q.sub.NNN needed can be calculates as follows:
q.sub.NNN=(V.sub.BB,NNN−V.sub.BB,NNN-90)×C.sub.RF (1)
(24) According to one embodiment, the front-end system may be provided with a charge reservoir 30 which comprises four capacitors C.sub.NNN and connected between the second converter circuit 12 and the modulator circuit 20. In this case, charge value q.sub.NNN calculated by the first converter circuit 11 needs to include the amount of charge needed to charge or discharge the charge reservoir as well.
(25) According to one embodiment, the second converter circuit 12 may be arranged for converting the charge value q.sub.NNN into an electrical charge Q.sub.NNN by generating at least one current I.sub.NNN (i.e. I.sub.000, I.sub.090, I.sub.180, I.sub.270) for a pre-determined period of time. The second converter circuit may be for example implemented using current sources. Thus, by integrating the output of the current source during a certain period of time over a load, effectively an electrical charge Q is determined. FIG. 5 shows two example implementations of such converter circuit 12. In the top of the figure, a conventional DAC generating an output voltage signal V.sub.NNN followed by a transconductor GM is used. A digital scaling prior conversion may be required to set the correct overall gain, which takes into account the gains of each respective DAC and in addition the gain of the respective GM if needed. The bottom implementation of FIG. 5 uses a conventional DAC generating an output current signal I.sub.NNN. Similarly, a digital scaling prior conversion may be required to set the correct overall gain by taking into account the gain of the respective current DAC. According to some embodiments, in order to limit the current flow, as the currents I.sub.NNN are integrated during the full period of each respective LO signals, including the period of time when the respective LO switch is closed, the output of the generator circuit 10 can be enabled only during a portion of the time when the respective LO switch 21 is open. For example, each current DAC may be enabled by the LO signal which is used to control the respective LO switch 21 but shifted by 180°. The generated current I.sub.NNN is thus first integrated over the respective capacitor C.sub.NNN of the charge reservoir 30, thereby creating an electrical charge Q.sub.NNN at the respective node 3 of the charge reservoir 30, and then transferred to the output load C.sub.RF via the respective LO switch 21 of the modulation circuit 20.
(26) According to another embodiment, the second converter circuit 12 may be arranged for generating the required amount of electrical charge Q.sub.NNN by using two variable capacitors C1, C2 and capacitance calculation circuit 13, as shown in FIG. 6. The variable capacitors may be implemented as a bank of switchable unit capacitors C.sub.UNIT. Alternatively, the variable capacitors may be realized with simple charge-based DACs, each consisting of a bank of switchable unit capacitors C.sub.UNIT. The first bank of switchable unit capacitors (e.g. C1) is arranged to receive a first pre-determined voltage (e.g. V.sub.REFH) and the second bank of switchable capacitors (e.g. C2) is arranged to receive a second pre-determined voltage (e.g. V.sub.REFL). For example, the first voltage V.sub.REFH is higher than the second voltage V.sub.REFL. The size of the variable capacitors (i.e. their respective capacitance) must be such that when the respective LO.sub.NNN switch 21 closes, the correct amount of electrical charge Q.sub.NNN is transferred to the output load C.sub.RF. The electrical charge Q is first transferred to the charge reservoir 30 via an additional switch 31, provided between the output of circuit 12 and the charge reservoir 30, and then to the output load C.sub.RF via the modulation circuit 20. The capacitance calculating circuit 13 calculates digitally a capacitor value (i.e. C.sub.H and C.sub.L) for each capacitor bank (i.e. C1 and C2) based on the charge value q.sub.NNN. The capacitance of the variable capacitors C1, C2 is adjusted according to the calculated capacitor value (i.e. C.sub.H and C.sub.L), for example, by switching ON or OFF the unit capacitors in the respective capacitor bank. If a positive charge value q.sub.NNN is to be delivered, the switchable capacitor bank C1 is pre-charged to the first (high) voltage V.sub.REFH. Similarly, if a negative charge value q.sub.NNN is to be delivered, the capacitor bank C2 is pre-charged to the second (low) voltage V.sub.REFL. Alternatively, as shown in FIG. 7, one variable capacitor C1 may be used instead of two. In this case, the charge calculator circuit 13 calculates a total capacitance value C.sub.T. The capacitance of the capacitor bank C1 is adjusted according to the calculated capacitance value C.sub.T by switching ON or OFF the required number of unit capacitors. The capacitor bank C1 is then pre-charged either to the first or the second voltage in order to increase or decrease the electrical charge Q at the output load. As a result the voltage VRF at the output load is increased or decreased. In order to improve the overall power efficiency of the front-end system, the second converter circuit may be implemented using a multiple (more than two) variable capacitors each arranged to receive a different pre-determined voltage. Alternatively, it may be implemented using one variable capacitor arranged to receive multiple of pre-determined voltages.
(27) According to yet another embodiment, the converter circuit 12 may be arranged for converting the respective charge value q.sub.NNN into an electrical charge Q.sub.NNN by using two variable resistors R1, R2 and resistance calculation circuit 14, as shown in FIG. 8. Each variable resistor is connected between a pre-determined voltage (V.sub.REFH, V.sub.REFL) and the output load C.sub.RF for a pre-determined period of time. The required amount of electrical charge Q.sub.NNN is generated using the two variable resistors that control the current flowing to the output load. The variable resistors may be implemented as a bank of switchable unit resistors R.sub.UNIT. The first bank of switchable unit resistors (e.g. R1) is arranged to receive a first pre-determined voltage (e.g. V.sub.REFH) and the second bank of switchable resistors (e.g. R2) is arranged to receive a second pre-determined voltage (e.g. V.sub.REFL). The first voltage V.sub.REFH is higher than the second voltage V.sub.REFL. The size of the variable resistors (i.e. their respective resistance) must be such that when the respective LO switch 21 closes, the correct amount of electrical charge Q.sub.NNN is transferred to the output load C.sub.RF. The electrical charge Q is first transferred to the charge reservoir 30 via an additional switch 31, provided between the output of circuit 12 and the charge reservoir 30, and then to the output load C.sub.RF via the modulation circuit 20. The resistance calculation circuit 14 calculates a resistance value (i.e. R.sub.H and R.sub.L) for each resistor bank R1, R2 based on the charge value q.sub.NNN. The resistance of the variable resistors R1, R2 is adjusted according to the calculated resistance value (i.e. R.sub.H and R.sub.L), for example, by switching ON or OFF the unit resistors in the respective resistor bank. If a positive charge value q.sub.NNN is to be delivered, the switchable resistor bank R1 is connected to the first (high) voltage V.sub.REFH. Similarly, if a negative charge value q.sub.NNN is to be delivered, the resistor bank R2 is connected to the second (low) voltage V.sub.REFL. Alternatively, as shown in FIG. 9, one variable resistor R1 may be used instead of two. In this case, the resistance calculator circuit 14 calculates a total resistance value R.sub.T. The resistance of the resistor bank R1 is adjusted according to the calculated value R.sub.T by switching ON or OFF the required number of unit resistors. The resistor bank R1 is then connected to the first or the second voltage (V.sub.REFH or V.sub.REFL) and the charge reservoir capacitor C.sub.NNN or the output load C.sub.RF, in order to increase or decrease the electrical charge Q at the output load. As a result the voltage VRF at the output load is increased or decreased. In order to improve the overall power efficiency of the front-end system, the second converter circuit may be implemented using a multiple (more than two) variable resistors each arranged to be connected between a different pre-determined voltage and the charge reservoir 30 for a pre-determined period of time. Alternatively, it may be implemented using one variable resistor arranged to be connected between a multiple (more than two) different pre-determined voltages and the charge reservoir.
(28) According to one embodiment, the first converter circuit 11 is a digital circuit which may be realized using a processing unit. The first converter circuit 11 may be thus arranged to output a multi-bit digital signal representing the calculated charge value q. The multi-bit digital signal is then fed to the second converter circuit 12.
(29) According to one embodiment, the front-end system 100 may be provided with a control unit 40 connected between the input of the modulator circuit 20 and the first converter circuit 11, as shown in FIG. 10. The control unit is arranged to control the first converter circuit 11, so that the first converted circuit 11 calculates the charge value q.sub.NNN by taking into account the electrical charge Q.sub.NNN available at the input of the modulator circuit 20. The control unit is thus arranged to determine the amount of electrical charge Q.sub.NNN present at the respective baseband node 3, which may be converted to a digital value (i.e. q.sub.NNN) by an analog-to-digital converter (ADC) 41. The ADC 41 may be provided between the control unit 40 and the input of the modulation circuit 20 and may be part of the control unit 40. The control unit 40 thus provides the first converter circuit 11 with a correction value so that circuit 11 takes into account the electrical charge already available at the input of the modulator circuit when determining the charge value q.sub.NNN for the next baseband sample. As a result, the charge value (i.e. Δq.sub.NNN) for the next baseband symbol represents the difference between the electrical charge available at the input of the modulator circuit and the electrical charge required for the next baseband sample. In turn, the second converter circuit 12 generates the amount of electrical charge (i.e. ΔQ.sub.NNN) required to increase or decrease the electrical charge at the input of the modulator circuit.
(30) According to another embodiment, the control unit 40 may be further arranged to control the first converter circuit 11 so that each charge value q.sub.NNN is calculated by taking into account inaccuracies in the front-end system due to manufacture variabilities. In this case, the control unit is arranged to determine, for the current baseband sample, the presence of an error between the charge value q.sub.NNN calculated by the first converter circuit 11 and the actual amount of electrical charge Q.sub.NNN present at the input of the modulator circuit 20. In case of an error, the control unit 40 adjusts/corrects the first converter circuit 11 so that the error is compensated.
(31) The method for a front-end system for a radio device will be explained with reference to FIG. 11 and FIG. 12. FIG. 11 shows a simplified schematic representation of the front-end system 100 using a second convert circuit 12 of FIG. 10. For simplicity, the first converter circuit 11 is not shown in the figure. Herein, the second converter circuit is represented with one bank of switchable capacitor C1 and two switches, i.e. a pre-charge switch (SWcharge) and a share switch (SWshare), each controlled by controls signal CTRL1 and CTRL2. In the illustration, the capacitance value of the variable capacitor C1 is controlled by the CDAC signal. The capacitor C1 is pre-charged either to a high or a low supply voltage (i.e. VDD or GND) whether the electrical charge Q at the output load (i.e. a pre-power amplifier (PPA) in this case) is to increased or decreased. The charge reservoir 30 is illustrated by a capacitor C.sub.BB and the modulation circuit 20 by an LO switch 21. FIG. 12 shows the respective timing diagrams of the control signals, i.e. CTRL1, CTRL2, the LO signal and the voltage signals at the output of the second converter circuit 12 (i.e. VDAC node), at the output of the charge reservoir 30 (i.e. at baseband node 3), at the output load (i.e. RF node 5), respectively. Although the method is described with reference to capacitive implementation of the converter circuit 12, the skilled person will recognize that the same method applies for the other alternative implementation.
(32) According to some embodiments of the present disclosure, the voltages at the output node 5 (i.e. VRF) and at the baseband nodes 3 (i.e. VBB) are modified using digitally-controlled packets of electrical charge Q conveyed between one of the supply voltages (VDD or GND) and the RF node 5 through the charge reservoir capacitors (i.e. C.sub.BB). For every baseband I/Q sample (i.e. BBI, BBQ), the first converter circuit 11 determines a charge value q, which corresponds to a capacitance value (e.g. C.sub.DAC). If the variable capacitor C1 is realized using simple charge-based DACs, each consisting of a bank of switchable unit capacitors C.sub.UNIT, the charge values q can be a multi-bit digital signal which may be directly used to control the DACs. The capacitance of the bank of switchable capacitors C1 is tuned in accordance to the capacitance value C.sub.MAC, by switching ON or OFF a number of unit capacitors C.sub.UNIT. After tuning the capacitance, the capacitor C1 is first pre-charged to either high or low supply voltage whether an increase or decrease of the voltage at the RF node5 is required, by switching switch SWcharge. Capacitor C1 is then connected to the charge reservoir capacitor C.sub.BB, by switching switch SWshare, to deliver the correct amount of electrical charge Q corresponding to the charge value q to the inputs of the modulation circuit 20. The charge Q shared between these C1 and C.sub.BB capacitors brings the voltage VBB at node 3 to a voltage V.sub.N* calculated to be such that when the modulator switch is closed, the RF node 5 settles at the desired voltage V.sub.N, as shown in FIG. 12. The linear slope (shown as VBB.sub.IDEAL) observed in the voltage V.sub.BB results in a sin c.sup.2 transfer function that attenuates the sampling aliases. The two-phase operation (i.e. pre-charge and a share phase) of the capacitive DAC in combination with the charge reservoir capacitor C.sub.BB resembles a switched-capacitor resistor. This combination introduces an intrinsic first-order LPF in the signal path that improves the transmitter out-of-band noise emission. The charge Q is then transferred to the output node 5 via the LO switch 21 of the mixer 20. The total electrical charge needed (i.e. Q.sub.TOTAL) for the operation of the front-end system 100 consists of two components: (i) the baseband electrical charge Q.sub.BB that allows the voltage on all charge reservoir capacitors C.sub.BB to follow the baseband I/Q samples; and (ii) the electrical charge Q.sub.RF at the RF node 5 needed to move the input voltage of the PPA at every quadrature LO cycle. That is, Q.sub.TOTAL=Q.sub.BB+Q.sub.RF. This is realized with simple charge-based DACs (QDACs) 12, consisting of a bank of switchable unit capacitors C.sub.UNIT and baseband (filtering) capacitors C.sub.BB. The electrical charge Q.sub.BB on the nodes 3 and Q.sub.RF on the RF node 5 can be calculated as
Q.sub.BB[k]=ΔV.sub.BB.Math.C.sub.BB=(V.sub.BB[k]−V.sub.BB[k−1]).Math.C.sub.BB (2)
Q.sub.RF[k]=ΔV.sub.RF.Math.C.sub.GS-PPA=(V.sub.I/Q[k]−V.sub.Q/I[k]).Math.C.sub.GS-PPA (3)
(33) The total electrical charge Q.sub.TOTAL is then
Q.sub.TOTAL[k]=Q.sub.BB[k]+Q.sub.RF[k] (4)
(34) The capacitance C.sub.DAC that C1 needs to be tuned to so that C1 provides the required amount of charge Q is
(35)
(36) In the disclosed front-end system, the smallest amount of charge Q conveyable from supply voltage VDD to node 3 and, thus, the quantization noise, is determined by the ratio C.sub.UNIT/C.sub.BB. By decreasing C.sub.UNIT with respect to C.sub.BB, the effective number of bits (ENOB) can be increased without increasing the number of bits of the DACs in the first converter circuit 11. Herein, the number of bits defines the maximum amount of charge Q that can be transferred to the node 3 in a single LO period. Rather than signal-to-noise ratio (SNR), the number of bits determines the maximum product between amplitude and frequency that can be achieved in the DAC output. The front-end system provides a better quantization noise performance when compared to a conventional DAC with the same number of bits.
(37) According to the present disclosure, instead of sampling the value of the baseband voltage at the input of the modulator circuit as in conventional radio architectures, the front-end system for a radio device transfers an amount of electrical charge to the input of the modulator circuit directly in charge-domain. The transferred electrical charge is essentially equivalent to the voltage at the input of the modulation circuit (voltage-sampling mixer) in conventional radio architectures. In an example embodiment, the front-end system may operate with the minimum amount of electrical charge theoretically needed to provide the required voltage swings at the output load. In addition, it avoids the need of linear (feedback-based) voltage amplifiers to drive the input of the modulation circuit. The front-end system provides sufficient in-band signal accuracy as well as sufficient filtering to achieve the required out-of-band noise specifications. Furthermore, it benefits from technology scaling as it is mainly composed of transistors (acting as switches) and capacitors.
