Split-gate flash memory having mirror structure and method for forming the same

Abstract

Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove. Reliability and durability of the memory are improved.

Claims

1. A method for forming a split-gate flash memory having a mirror structure, comprising: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until a first groove which exposes the floating gate layer is formed; forming a protective sidewall on a sidewall of the first groove; forming a gate dielectric layer on the bottom and the sidewall of the first groove; forming two discrete control gates on the gate dielectric layer in the first groove, wherein the first groove after the two discrete control gates are formed serves as a second groove; etching the gate dielectric layer and the floating gate layer at the bottom of the second groove until a third groove which exposes the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; forming a second dielectric layer in the third groove; after the second dielectric layer is formed, removing the mask layer to form a fourth groove; removing the floating gate layer at bottom of the fourth groove; forming a tunnel dielectric layer on bottom and a sidewall of the fourth groove, on an upper surface of the control gate and on an upper surface of the second dielectric layer; forming a word line in the fourth groove; forming an interlayer dielectric layer to cover the word line and the tunnel dielectric layer; etching a portion of the second dielectric layer, a portion of the tunnel dielectric layer and a portion of the interlayer dielectric layer over the source to form a through hole that exposes the source; and forming a contact plug in the through hole.

2. The method according to claim 1, wherein the protective sidewall comprises silicon oxide.

3. The method according to claim 1, wherein thickness of the protective sidewall when the protective sidewall is formed is within a range from 200 Å to 250 Å; and when the fourth groove is formed, the protective sidewall is etched partially, and thickness of the protective sidewall after the fourth groove is formed is within a range from 150 Å to 200 Å.

4. The method according to claim 1, further comprising: before the gate dielectric layer is formed, etching a portion of the floating gate layer at the bottom of the first groove by using the mask layer as a mask, so that the first groove has a cambered bottom.

5. The method according to claim 1, wherein the second dielectric layer comprises silicon oxide.

6. The method according to claim 1, further comprising: after the source is formed, cleaning the third groove to remove the first dielectric layer at the bottom of the third groove.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1 to 21 schematically illustrate sectional views of intermediate structures of a method for forming a split-gate flash memory having a mirror structure according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

(2) As described in background, split-gate flash memories formed by existing methods have poor erasure ability. In existing techniques, a relatively high voltage needs to be applied between a word line and a control gate during an erasure process. However, in the existing split-gate flash memories, a dielectric layer between the word line and the control gate may not suffer the relatively high voltage, thus reliability and durability of the split-gate flash memories may be relatively poor.

(3) In embodiments of the present disclosure, a split-gate flash memory having a mirror structure and a method for forming the same are provided. In the split-gate flash memory, a protective sidewall is disposed between a word line and a control gate, which increases thickness of a dielectric layer between the word line and the control gate. As a result, the dielectric layer's ability of suffering a high voltage between the word line and the control gate during an erasure process may be enhanced, and further reliability and durability of the split-gate flash memory may be improved.

(4) In order to clarify the objects, characteristics and advantages of the disclosure, embodiments of present disclosure will be described in detail in conjunction with accompanying drawings.

(5) Referring to FIGS. 1 to 21, in an embodiment, a method for forming a split-gate flash memory having a mirror structure is provided.

(6) Referring to FIG. 1, a semiconductor substrate 100 is provided, a first dielectric layer 101 is formed on the semiconductor substrate 100, a floating gate layer 103 is formed on the first dielectric layer 101, and a mask layer 105 is formed on the floating gate layer 103.

(7) In some embodiments, the semiconductor substrate 100 may be a silicon substrate. In some embodiments, the semiconductor substrate 100 may include germanium-silicon, compounds of III to IV group elements or silicon carbide. In some embodiments, the semiconductor substrate 100 may have a stacked structure, or may be a Silicon-on-Insulator (SOI) substrate. In some embodiments, the semiconductor substrate 100 may have other semiconductor materials. An isolation structure may be formed between different regions in the semiconductor substrate 100. In some embodiments, the isolation structure may be a shallow trench isolation (STI) region or a field oxide layer.

(8) Referring to FIG. 2, a patterned photoresist layer 107 is formed on the mask layer 105, and the mask layer 105 is etched by taking the patterned photoresist layer 107 as a mask until a first groove 109 which exposes the floating gate layer 103 is formed.

(9) In some embodiments, the first dielectric layer 101 may include silicon oxide. In some embodiments, the floating gate layer 103 may include polysilicon. In some embodiments, the mask layer 105 may include silicon nitride.

(10) In above embodiments, the patterned photoresist layer 107 is used as the mask to etch the mask layer 105. In some embodiments, the mask layer 105 may be etched by other methods to form the first groove 109. That is to say, although the above embodiments provide a method for forming the first groove 109, the present disclosure is not limited thereto.

(11) Referring to FIG. 3, a portion of the floating gate layer 103 at the bottom of the first groove 109 is etched by taking the remained mask layer 105 as a mask, so that the first groove 109 becomes a first groove 111 having a cambered bottom.

(12) In some embodiments, the cambered bottom means the bottom of the first groove 111 exhibits a camber in a sectional view. Specifically, from a center of the bottom of the first groove 111 to edges of the bottom of the first groove 111, depth of the first groove 111 becomes smaller gradually, as shown in FIG. 3. The cambered bottom of the first groove 111 may enable a floating gate to be formed subsequently to have a small tip (as shown in FIG. 14). The floating gate having the small tip may improve erase ability of the flash memory.

(13) In some embodiments, the portion of the floating gate layer 103 at the bottom of the first groove 109 may be etched using an isotropy etching process.

(14) Referring to FIGS. 4 and 5, a protective sidewall 115 is formed on a sidewall of the first groove 111.

(15) Referring to FIG. 4, a protective sidewall material layer 113 is formed on the sidewall and the bottom of the first groove 111, and the protective sidewall material layer 113 is etched (by an anisotropy blank and dry etching process) to form the protective sidewall 115 on the sidewall of the first groove 111, as shown in FIG. 5.

(16) In some embodiments, the protective sidewall 115 may include silicon oxide. On one hand, the protective sidewall 115 including silicon oxide has enough dielectric function. On the other hand, if silicon oxide is used as the material of the protective sidewall 115, etching selectivity of the protective sidewall 115 to the mask layer 105 is relatively high when the mask layer 105 is removed, so that the protective sidewall 115 is prevented from being greatly removed by etching. Besides, process for forming silicon oxide is mature and simple, requires relatively low cost, and has wide step coverage.

(17) In some embodiments, a high Temperature Oxide layer (HTO) Chemical vapor deposition (CVD) process may be used to form the protective sidewall material layer 113, which may improve the step coverage of the protective sidewall material layer 113 and make the thickness of the protective sidewall to be formed relatively uniform from top to bottom.

(18) In some embodiments, thickness of the protective sidewall 115 may be within a range from 200 Å to 250 Å. Although selecting silicon oxide as the protective sidewall 115 can ensure a relatively high etching selectivity of the protective sidewall 115 to the mask layer 105, it is impossible that the protective sidewall 115 is not etched at all. That is to say, the thickness of the protective sidewall 115 may be decreased during the process for etching the mask layer 105. Besides, when the floating gate layer 103 under the mask layer 105 is etched subsequently, the protective sidewall 115 is further etched, which may further decrease the thickness of the protective sidewall 115. Therefore, when forming the protective sidewall 115, it is necessary to control the thickness of the protective sidewall 115 over 200 Å, so that the thickness of the protective sidewall 115 finally remained can meet requirements. Meanwhile, if the thickness of the protective sidewall 115 finally remained is too great, thickness of a gate dielectric layer to be formed subsequently may not meet requirements. Therefore, when forming the protective sidewall 115, it is also necessary to control the thickness of the protective sidewall 115 less than 250 Å.

(19) Referring to FIG. 6, a gate dielectric layer 117 is formed on the bottom and the sidewall of the first groove 111. As described above, the protective sidewall 115 is formed on the sidewall of the first groove 111, thus, the gate dielectric layer 117 also covers the protective sidewall 115.

(20) In some embodiments, an oxide-nitride-oxide (ONO) layer is employed as the gate dielectric layer 117, which, compared with other materials, may result in better dielectric performance of the gate dielectric layer 117. In some embodiments, the gate dielectric layer 117 may have a single-layer structure or a multiple-layer structure. When the gate dielectric layer 117 is a single layer, it may include silicon oxide or silicon nitride.

(21) It should be noted that, in some embodiments, the floating gate layer 103 at the bottom of the first groove 109 may be not etched. Instead, the protective sidewall 115 is formed directly on the sidewall of the first groove 109, and the gate dielectric layer 117 is formed to cover the bottom and the sidewall of the first groove 109.

(22) Referring to FIGS. 7 and 8, two discrete control gates 121 are formed on the gate dielectric layer 117 in the first groove 111, where remained portion of the first groove 111 serves as a second groove 123.

(23) Referring to FIG. 7, in some embodiments, a gate material layer 119 is formed to cover the bottom and the sidewall of the first groove 111, and the gate material layer 119 is etched to form the two discrete control gates 121 as shown in FIG. 8. Therefore, it can be seen from above that a mirror structure is formed here.

(24) In some embodiments, the two discrete control gates 121 cover the gate dielectric layer 117 formed on two sidewalls of the first groove 111, respectively. And the remained portion of the first groove 111 between the two discrete control gates 121 serves as the second groove 123.

(25) In some embodiments, both the gate material layer 119 and the gate dielectric layer 117 on the mask layer 105 are removed.

(26) In some embodiments, the control gates 121 may include polysilicon.

(27) Referring to FIG. 9, the gate dielectric layer 117 and the floating gate layer 103 at the bottom of the second groove 123 are etched until a third groove 125 which exposes the first dielectric layer 101 is formed.

(28) In some embodiments, the gate dielectric layer 117 and the floating gate layer 103 may be etched using an anisotropy dry etching process.

(29) Referring to FIG. 10, a source 127 is formed in the semiconductor substrate 100 under the third groove 125.

(30) In some embodiments, the source 127 may be formed using a heavily-doped injection process. The first dielectric layer 101 at the bottom of the third groove 125 may not influence the formation of the source 127. On the contrary, the first dielectric layer 101 at the bottom of the third groove 125 can prevent a surface of the semiconductor substrate 100 from being affected by ion injection, which may benefits the formation of the source 127.

(31) Optionally, referring to FIG. 11, in some embodiments, after the source 127 is formed, the third groove 125 may be cleaned to remove the first dielectric layer 101 at the bottom of the third groove 125, so that a second dielectric layer to be formed subsequently may fill the third groove 125 from the surface of the semiconductor substrate 100.

(32) Referring to FIGS. 12 and 13, a second dielectric layer 131 is formed in the third groove 125.

(33) Referring to FIG. 12, in some embodiments, a second dielectric material layer 129 is formed in the third groove 125. Referring to FIG. 13, the second dielectric material layer 129 is etched to remove a portion of the second dielectric material layer 129 on an upper surface of the mask layer 105 and on an upper surface of the control gates 121, to form the second dielectric layer 131.

(34) In some embodiments, the second dielectric layer 131 may include silicon oxide.

(35) In some embodiments, the second dielectric layer 131 is formed on the first dielectric layer 101. As described above, in some embodiments, the first dielectric layer 101 at the bottom of the third groove 125 may be removed, thus, the second dielectric layer 131 may be formed directly on the semiconductor substrate 100.

(36) Referring to FIG. 14, after the second dielectric layer 131 is formed, the mask layer 105 is removed to form a fourth groove 133.

(37) In some embodiments, the mask layer 105 may be removed by following steps: forming a protective layer to protect formed structures and expose the mask layer 105; and removing the mask layer 105 using an anisotropy dry etching process.

(38) Referring to FIG. 15, a portion of the floating gate layer 103 at the bottom of the fourth groove 133 is removed, where remained portion of the floating gate layer 103 serves as a floating gate 1031.

(39) In some embodiments, the portion of the floating gate layer 103 may be etched together with the mask layer 105. In some embodiments, the portion of the floating gate layer 103 may be etched by a dependent anisotropy dry etching process.

(40) As described above, thickness of the protective sidewall 115 is within a range from 200 Å to 250 Å. When forming the fourth groove 133 and etching the portion of the floating gate layer 103 at the bottom of the fourth groove 133, the protective sidewall 115 may be etched partially. The thickness of the remained protective sidewall 115 may be within a range from 150 Å to 200 Å. On one hand, it is necessary to control the thickness of the remained protective sidewall 115 over 150 Å, so that the protective sidewall 115 can protect the gate dielectric layer 117 not to be affected by etching, and the protective sidewall 115 together with the gate dielectric layer 117 can suffer a relatively high working voltage between the control gates 121 and word lines to be formed subsequently. Meanwhile, if the thickness of the remained protective sidewall 115 is too great, thickness of the gate dielectric layer 117 may be limited and cannot meet requirements. Therefore, it is also necessary to control the thickness of the remained protective sidewall 115 less than 200 Å. When the thickness of the remained protective sidewall 115 is within the range from 150 Å to 200 Å, thickness of the gate dielectric layer 117 (for example, an ONO layer) may be about 140 Å, so that the protective sidewall 115 together with the gate dielectric layer 117 can suffer the relatively high working voltage between the control gates 121 and the word lines during an erase process.

(41) The protective sidewall 115 being etched partially when the fourth groove 133 is formed and the portion of the floating gate layer 103 at the bottom of the fourth groove 133 is etched may have following advantages. When the protective sidewall 115 is partially etched, the tip mentioned in the description of forming the first groove 111 may be exposed, as shown in FIG. 15. As having the tip, when an erase operation is performed, the floating gate 1031 may use the tip to perform corona discharging, which may improve the erase ability of the flash memory.

(42) Besides, forming the protective sidewall 115 can prevent the gate dielectric layer 117 from being affected by processes for forming the fourth groove 133 and etching the portion of the floating gate layer 103 at the bottom of the fourth groove 133, so that the gate dielectric layer 117 can retain well, and reliability and durability of the flash memory may be improved.

(43) Referring to FIG. 16, a tunnel dielectric layer 135 is formed on bottom and a sidewall of the fourth groove 133, on the upper surface of the control gates 121, and on an upper surface of the second dielectric layer 131.

(44) In some embodiments, before forming the tunnel dielectric layer 135, the fourth groove 133 may be cleaned, so that the first dielectric layer 101 at the bottom of the fourth groove 133 is cleaned and the tunnel dielectric layer 135 to be formed subsequently may be formed in contact with the semiconductor substrate 100. In some embodiments, the first dielectric layer 101 at the bottom of the fourth groove 133 may not be removed.

(45) In some embodiments, the tunnel dielectric layer 135 may include silicon oxide. Process for forming the tunnel dielectric layer 135 is well known in the art, and not described in detail here.

(46) Referring to FIGS. 17 and 18, a word line 139 is formed in the fourth groove 133.

(47) Referring to FIG. 17, in some embodiments, a word line material layer 137 is formed to fill the fourth groove 133 and cover the tunnel dielectric layer 135. Afterward, referring to FIG. 18, the word line material layer 137 is etched using a planarization process or an etching process, to form the word line 139.

(48) In some embodiments, the word line 139 may include polysilicon. Other processes for forming the word line 138 that are well known in the art are also possible.

(49) Referring to FIGS. 19 to 21, an interlayer dielectric layer 143 is formed to cover the word line 139 and the tunnel dielectric layer 135, a portion of the second dielectric layer 131, a portion of the tunnel dielectric layer 135 and a portion of the interlayer dielectric layer 143 over the source 127 are etched to form a through hole 145 that exposes the source 127, and a contact plug 141 is formed in the through hole 145 so that the contact plug 141 can be electrically connected with the source 127.

(50) From above, in embodiments of the present disclosure, the semiconductor substrate 100 is provided, the first dielectric layer 101 is formed on the semiconductor substrate 100, the floating gate layer 103 is formed on the first dielectric layer 101, and the mask layer 105 is formed on the floating gate layer 103. The mask layer 105 is etched until the first groove 111 which exposes the floating gate layer 103 is formed (referring to FIG. 3). The protective sidewall 115 is formed on the sidewall of the first groove 111, and the gate dielectric layer 117 is formed on the bottom and the sidewall of the first groove 111. Two discrete control gates 121 are formed on the gate dielectric layer 117 in the first groove 111, where remained portion of the first groove 111 serves as the second groove 123 (referring to FIG. 8). The gate dielectric layer 117 and the floating gate layer 103 at the bottom of the second groove 123 are etched until the third groove 125 which exposes the first dielectric layer 101 is formed (referring to FIG. 9). The second dielectric layer 131 is formed in the third groove 125, and the source 127 is formed in the semiconductor substrate 100 under the third groove 125 (referring to FIG. 10). Based on the above process, the protective sidewall 115 is remained between the word line 139 and the control gates 121. Due to the protective sidewall 115, thickness of a dielectric layer between the word line 139 and the control gates 121 is increased, so that the dielectric layer can suffer a relatively high working voltage between the word line 139 and the control gates 121 during the erase process, and this may further improve the reliability and the durability of the flash memory formed.

(51) In an embodiment, a split-gate flash memory having a mirror structure is provided. The split-gate flash memory may be formed by the method described above. Therefore, above-mentioned information can be referred.

(52) Referring to FIG. 21, in some embodiments, the split-gate flash memory may include a semiconductor substrate 100, a source 127 in the semiconductor substrate 100, a second dielectric layer 131 disposed over the source 127, a first dielectric layer 101 disposed on the semiconductor substrate 100 on two sides of the second dielectric layer 131, a floating gate 1031 disposed on the first dielectric layer 101, a gate dielectric layer 117 disposed on the floating gate 1031, a control gate 121 disposed on the gate dielectric layer 117, a tunnel dielectric layer 135 disposed on a sidewall of the floating gate 1031, on a sidewall of the gate dielectric layer 117 and on an upper surface of the control gate 121, and a word line 139 disposed on a sidewall of the tunnel dielectric layer 135. The split-gate flash memory may further include a protective sidewall 115 disposed between the sidewall of the tunnel dielectric layer 135 and the sidewall of the gate dielectric layer 117, an interlayer dielectric layer 143 covering the tunnel dielectric layer 135, and a contact plug 141 which penetrates the interlayer dielectric layer 143, the tunnel dielectric layer 135 and the second dielectric layer 131, where the contact plug 141 is electrically connected with the source 127.

(53) In some embodiments, the protective sidewall 115 may include silicon oxide. Thickness of the protective sidewall 115 may be within a range from 150 Å to 200 Å. Reasons for the material and the numerical values can be referred to above description.

(54) In the split-gate flash memory, as the protective sidewall 115 is disposed between the word line 139 and the control gate 121, the thickness of the dielectric layer between the word line 139 and the control gate 121 is increased, so that the dielectric layer can suffer a relatively high working voltage between the word line 139 and the control gates 121 during an erase process, and this may further improve reliability and durability of the split-gate flash memory.

(55) Although the present disclosure has been disclosed above with reference to preferred embodiments thereof, it should be understood that the disclosure is presented by way of example only, and not limitation. Those skilled in the art can modify and vary the embodiments without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is subject to the scope defined by the claims.