DELAY CELL CIRCUITS

Abstract

A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

Claims

1. A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series, wherein each delay cell comprises: first and second inverter sub-cells, each of said inverter sub-cells comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node, wherein each of said transistors has a back-gate terminal and is arranged such that a respective threshold voltage of said transistor is linearly dependent on a respective voltage applied to the back-gate terminal of said transistor; wherein the back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell; and wherein a control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of at least one transistor.

2. The time delay circuit as claimed in claim 1, wherein the transistors comprise ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB-FDSOI) transistors.

3. The time delay circuit as claimed in claim 1, comprising a delay line circuit.

4. The time delay circuit as claimed in claim 1, comprising a ring oscillator circuit comprising a plurality of differential delay cells arranged in a ring, each having a positive input, a negative input, a positive output, and a negative output, wherein the positive output of each differential delay cell is connected to the negative input of the next differential delay cell in the ring.

5. The time delay circuit as claimed in claim 1, arranged such that: the back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell; and a control signal varies the time delay of the delay cell by adjusting a voltage supplied to the back-gate terminal of the NMOS transistor in each inverter sub-cell.

6. The time delay circuit as claimed in claim 1, arranged such that: the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell; and a control signal varies the time delay of the delay cell by adjusting a voltage supplied to the back-gate terminal of the PMOS transistor in each inverter sub-cell.

7. The time delay circuit as claimed in claim 1, further comprising a frequency control portion comprising first and second frequency control sub-cells, wherein each of said frequency control sub-cells comprises a respective PMOS transistor and an NMOS transistor; wherein each of said transistors has a back-gate terminal and is arranged such that a respective threshold voltage of said transistor is linearly dependent on a respective voltage applied to the back-gate terminal of said transistor; wherein the back-gate terminal of each of the PMOS and NMOS transistors in each inverter sub-cell is connected to the drain node of the other sub-cell; and wherein the frequency control portion is arranged such that first and second control signals vary the time delay of the delay cell, wherein the first control signal adjusts a respective voltage at the back-gate terminals of the PMOS transistors in the first and second frequency control sub-cells, and wherein the second control signal adjusts a respective voltage at the back-gate terminals of the NMOS transistors in the first and second frequency control sub-cells.

8. The time delay circuit as claimed in claim 7, wherein the respective PMOS and NMOS transistors in each of the first and second frequency control sub-cells are arranged in series such that their respective drain terminals are connected at a drain node; wherein the drain node of the first inverter sub-cell is connected to the drain node of the first frequency control sub-cell, and wherein the drain node of the second inverter sub-cell is connected to the drain node of the second frequency control sub-cell; and wherein the gate terminals of the PMOS and NMOS transistors of the first inverter and first frequency control sub-cells are connected together, and wherein the gate terminals of the PMOS and NMOS transistors of the second inverter and second frequency control sub-cells are connected together.

9. The time delay circuit as claimed in claim 7, wherein the frequency control portion is arranged such that: the PMOS transistor of the first frequency control sub-cell has its drain terminal connected to the source terminal of the PMOS transistor of the first inverter sub-cell; the NMOS transistor of the first frequency control sub-cell has its drain terminal connected to the source terminal of the NMOS transistor of the first inverter sub-cell; the PMOS transistor of the second frequency control sub-cell has its drain terminal connected to the source terminal of the PMOS transistor of the second inverter sub-cell; and the NMOS transistor of the second frequency control sub-cell has its drain terminal connected to the source terminal of the NMOS transistor of the second inverter sub-cell; wherein the gate terminals of the PMOS and NMOS transistors of the first frequency control sub-cell are connected to the gate terminals of the PMOS and NMOS transistors of the first inverter sub-cell; and wherein the gate terminals of the PMOS and NMOS transistors of the second frequency control sub-cell are connected to the gate terminals of the PMOS and NMOS transistors of the second inverter sub-cell.

10. A differential delay cell having a time delay, said delay cell comprising: first and second inverter sub-cells, each of said inverter sub-cells comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node, wherein each of said transistors has a back-gate terminal and is arranged such that a respective threshold voltage of said transistor is linearly dependent on a respective voltage applied to the back-gate terminal of said transistor; wherein the back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell; and wherein a control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of at least one transistor.

11. A ring oscillator circuit comprising: a plurality of differential delay cells arranged in a ring, each having a differential output connected to a differential input of the next differential delay cell in the ring; wherein each differential delay cell comprises first and second inverter sub-cells, each of said inverter sub-cells comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node, wherein each of said transistors has a back-gate terminal and is arranged such that a respective threshold voltage of said transistor is linearly dependent on a respective voltage applied to the back-gate terminal of said transistor; wherein the back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell; and wherein a control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of at least one transistor.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0089] Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0090] FIGS. 1A and 1B are a circuit diagram and a schematic diagram of an inverter sub-cell respectively;

[0091] FIG. 2 is a schematic diagram of a delay cell;

[0092] FIG. 3 is a circuit diagram of an asymmetric pseudo-differential delay cell in accordance with an embodiment of the present invention;

[0093] FIG. 4 is a circuit diagram of an asymmetric pseudo-differential delay cell in accordance with an alternative embodiment of the present invention;

[0094] FIG. 5 is a circuit diagram of a delay line that uses the pseudo-differential delay cell of FIG. 3;

[0095] FIGS. 6A and 6B are circuit diagrams of ring oscillators that use the pseudo-differential delay cell of FIG. 3;

[0096] FIG. 7 is a graph illustrating how the frequency of the oscillators of FIGS. 6A and 6B depend on the control voltage;

[0097] FIG. 8 is a graph illustrating how the frequency of the oscillators of FIGS. 6A and 6B depends on the control voltage and load capacitance;

[0098] FIG. 9 is a graph illustrating the dependence of the intersection level of the oscillators' differential outputs on the control voltage;

[0099] FIGS. 10A-C are circuit and schematic diagrams of an inverter sub-cell for use in a symmetric pseudo-differential delay cell;

[0100] FIG. 11 is a circuit diagram of a symmetric pseudo-differential delay cell in accordance with a further embodiment of the present invention;

[0101] FIG. 12 is a circuit diagram of another symmetric pseudo-differential delay cell in accordance with another embodiment of the present invention;

[0102] FIG. 13 is a schematic diagram of a pseudo-differential delay cell that uses the topology of either FIG. 11 or FIG. 12;

[0103] FIG. 14 is a circuit diagram of a delay line that uses the pseudo-differential delay cell of FIG. 11 or FIG. 12; and

[0104] FIGS. 15A and 15B are circuit diagrams ring oscillators that use the pseudo-differential delay cell of FIG. 11 or FIG. 12 with an odd and even number of cells respectively.

DETAILED DESCRIPTION

[0105] FIGS. 1A and 1B are a circuit diagram and a schematic diagram of an inverter sub-cell 2 respectively. As can be seen in FIG. 1A, the inverter sub-cell is constructed from a PMOS UTBB-FDSOI transistor 4 and an NMOS UTBB-FDSOI transistor 6, arranged in series. It will be appreciated that while UTBB-FDSOI transistors are used in the specific embodiments of the invention described below, other transistor technologies having the required characteristics of a threshold voltage that is linearly dependent on a voltage applied to its back-gate terminal could be used instead.

[0106] The transistors 4, 6 are connected at their respective gate terminals to an input terminal supplied with an input voltage vi, and at their respective drain terminals to an output terminal that produces an output voltage vo.

[0107] The source terminal of the PMOS transistor 4 is connected to the supply voltage Vdd, and the source terminal of the NMOS transistor 6 is connected to the ground rail. It will, of course, be appreciated that different supply rails or connections could be used as appropriate, for example by connecting the source terminal of the NMOS transistor 6 to a negative supply rail instead of to ground.

[0108] A positive control voltage vbgp is applied to the back-gate terminal of the PMOS transistor 4, and a negative control voltage vbgn is applied to the back-gate terminal of the NMOS transistor 6. By varying each of these control voltages vbgp, vbgn, the speed of the transistors 4, 6—and thus the inverter sub-cell 2—can be controlled.

[0109] By combining two of these inverter sub-cells 2, a pseudo-differential delay cell 8 may be constructed, as illustrated in FIG. 2, which shows the diagrammatic symbol for such a cell 8. Differential input voltages vip, vin are applied the two sub-cells 2 such that each sub-cell 2 receives one of the input voltages vip, vin, as is more clearly illustrated in e.g. FIGS. 3 and 4 below. The delay cell 8 also produces differential output voltages von, vop, where each sub-cell 2 produces one of the output voltages von, vop, as discussed in further detail later. A control voltage vctrl is supplied to a control input, i.e. to the back-gates of the transistors 4, 6 in each sub-cell 2, which controls the time delay of each sub-cell 2, and thus of the the delay cell 8.

[0110] It will be understood that the term ‘time delay’ as used herein, means the time difference between when a change is made to the input of an element (i.e. a sub-cell 2 or delay cell 8)— that is, to the appropriate input voltage vi, vip, vin—and when the change is effected at the corresponding output, i.e. the output voltage vo, von, vop of that element.

[0111] FIG. 3 is a circuit diagram of an asymmetric pseudo-differential delay cell 8 in accordance with an embodiment of the present invention. As discussed above, the delay cell 8 is constructed from two inverter sub-cells 2a, 2b.

[0112] Each of the inverter sub-cells 2a, 2b is constructed from a respective PMOS UTBB-FDSOI transistor 4a, 4b and a respective NMOS UTBB-FDSOI transistor 6a, 6b. These pairs of transistors 4a, 6a and 4b, 6b are arranged in series such that their respective drain terminals are connected at a respective drain node 10a, 10b. The source terminals of the PMOS transistors 4a, 4b are connected to the positive supply rail Vdd and the source terminals of the NMOS transistors 6a, 6b are connected to the ground rail.

[0113] The drain node 10a of the first inverter sub-cell 2a produces the negative output voltage von, while the drain node 10b of the second inverter sub-cell 2b produces the positive output voltage vop, i.e. there is a ‘cross-over’ from the positive and negative inputs to the negative and positive outputs.

[0114] The respective back-gate terminal of each of the PMOS UTBB-FDSOI transistors 4a, 4b in each inverter sub-cell 2a, 2b is connected to the drain node 10a, 10b of the other sub-cell 2a, 2b. This cross-coupling provides the pseudo-differential behaviours of the delay cell 8.

[0115] The back-gate terminals of each of the NMOS UTBB-FDSOI transistors 6a, 6b in each inverter sub-cell 2a, 2b are connected to a control terminal that applies a control voltage vctrl to these back-gate terminals. This control voltage vctrl varies the time delay of the delay cell 8 by adjusting the voltage supplied to the back-gate terminals of the NMOS UTBB-FDSOI transistors 6a, 6b. This process is described in further detail below with reference to FIGS. 7 to 9.

[0116] FIG. 4 is a circuit diagram of an asymmetric pseudo-differential delay cell 8′ in accordance with an alternative embodiment of the present invention. It will be appreciated that elements having like reference numerals appended with a prime symbol correspond to those elements having the same reference numeral without the prime symbol described above with reference to FIGS. 1 to 3.

[0117] The structure of the delay cell 8′ of FIG. 4 is similar to that of the delay cell 8 of FIG. 3, except that the roles of the PMOS and NMOS transistors are reversed.

[0118] Specifically, in the delay cell 8′ of FIG. 4, the respective back-gate terminal of each of the NMOS UTBB-FDSOI transistors 6a′, 6b′ in each inverter sub-cell 2a′, 2b′ is connected to the drain node 10a′, 10b′ of the other sub-cell 2a′, 2b′ and provides the pseudo-differential behaviours of the delay cell 8′.

[0119] The back-gate terminals of each of the PMOS UTBB-FDSOI transistors 4a′, 4b′ in each inverter sub-cell 2a′, 2b′ are connected to a control terminal that applies a control voltage vctrl to these back-gate terminals. This control voltage vctrl varies the time delay of the delay cell 8′ by adjusting the voltage supplied to the back-gate terminals of the PMOS UTBB-FDSOI transistors 4a′, 4b′.

[0120] Contrary to the delay cell 8 of FIG. 3, in the delay cell 8′ of FIG. 4, the respective back-gate terminals of the NMOS UTBB-FDSOI transistor in each inverter sub-cell is connected to the drain node 10a′, 10b′ of the other sub-cell 2a′, 2b′.

[0121] FIG. 5 is a circuit diagram of a delay line 12 that uses the pseudo-differential delay cell 8 of FIG. 3. As can be seen in FIG. 5, the delay line 12 is constructed from N delay cells 8a, 8b, 8n arranged in series. For clarity of illustration, the individual components of the delay cells 8a, 8b, 8n are not labelled, however the components of each delay cell 8a, 8b, 8n has the same structure and function as those described above in relation to the delay cell 8 of FIG. 3.

[0122] The N delay cells 8a, 8b, 8n are arranged in series such that the negative and positive outputs of each delay cell 8a, 8b . . . are connected to the positive and negative inputs of the next delay cell 8b, 8n in the chain. The differential output—i.e. the difference between the negative outputs ph1, ph2, . . . , phn and positive outputs ph1, ph2, . . . , phn—of each delay cell stage 8a, 8b, 8n is a time-delayed version of the differential input to that delay cell stage 8a, 8b, 8n.

[0123] By varying the value of the control voltage vctrl, the time delay introduced by each delay cell 8a, 8b, . . . , 8n is varied, and thus the total propagation delay of the delay line 12 is also varied.

[0124] FIGS. 6A and 6B are circuit diagrams of ring oscillators 14, 14′ that use the pseudo-differential delay cell of FIG. 3. It will be appreciated that, like the delay line 12 of FIG. 5, the number N of stages may be selected as appropriate, where an odd number N of cells may be used as per the topology of FIG. 6A, and an even number N of cells may be used as per the topology of FIG. 6B, as outlined below.

[0125] As can be seen in FIG. 6A, the ring oscillator 14 is constructed from an odd number N of delay cells 8a, 8b, 8n arranged in series, in a loop. For clarity of illustration, the individual components of the delay cells 8a, 8b, 8n are not labelled, however the components of each delay cell 8a, 8b, 8n has the same structure and function as those described above in relation to the delay cell 8 of FIG. 3.

[0126] Unlike the delay line 12 of FIG. 5, in the ring oscillator 14 the N delay cells 8a, 8b, . . . , 8n are arranged in a loop, i.e. the output of the ‘last’ delay cell 8n is connected back to the input of the ‘first’ delay cell 8a. It will of course be appreciated that the terms ‘first’ and ‘last’ are used to provide contrast to the delay cells in the delay line 12, as there is no ‘first’ or ‘last’ delay cell by virtue of it being a loop. The inverting output of each delay cell stage 8a, 8b, . . . , 8n is connected to the non-inverting input of the next delay cell stage 8a, 8b, . . . , 8n in the loop. Similarly, the non-inverting output of each delay cell stage 8a, 8b, . . . , 8n is connected to the inverting input of the next delay cell stage 8a, 8b, . . . , 8n in the loop

[0127] The loop of the ring oscillator 14 is ‘unstable’ and, assuming a sufficiently high gain for each stage, the output of each delay cell stage 8a, 8b, 8n alternates between a high value and a low value, providing a substantially square waveform at each output.

[0128] Conversely, the ring oscillator 14′ of FIG. 6B uses an even number N of delay cells 8a, 8b, . . . , 8n arranged in series, in a loop. In this arrangement, the inverting output of all but the last delay cell stage 8a, 8b, . . . , 8n-1 is connected to the non-inverting input of the next delay cell stage 8b, 8c, . . . , 8n in the loop; and the non-inverting output of all but the last delay cell stage 8a, 8b, . . . , 8n-1 is connected to the inverting input of the next delay cell stage 8b, 8c, . . . , 8n in the loop.

[0129] However, when using an even number N of delay cells 8a, 8b, 8n, the inverting and non-inverting outputs of one of the delay cells are ‘crossed over’ so that they are connected to inverting and non-inverting inputs respectively (rather than to their opposite type as in the rest of the cases). In this example, the inverting and non-inverting outputs of the ‘last’ delay cell stage 8n are respectively connected to the inverting and non-inverting outputs of the first delay cell stage 8a. It will, of course, be appreciated that the term ‘last’ is arbitrary in a loop structure, and any selected one of the even number N of delay cells 8a, 8b, 8n may have its outputs ‘crossed over’ in this way.

[0130] By varying the value of the control voltage vctrl, the time delay introduced by each delay cell 8a, 8b, . . . , 8n is varied, and thus the frequency of the ring oscillator 14 is also varied.

[0131] FIG. 7 is a graph illustrating how the frequency of the ring oscillators 14, 14′ of FIGS. 6A and 6B depends on the control voltage. It can be readily seen that the value of the control voltage V.sub.ctrl can take any value between 0 V and V.sub.DD, i.e. full rail-to-rail control is available. This is also shown in the time domain, in the plots in the graph of FIG. 8.

[0132] As the control voltage V.sub.ctrl is increased, the frequency of the ring oscillator 14 increases. Advantageously, this increase in frequency is highly linear with the change in control voltage, making control of the oscillator frequency far simpler than is typical of prior art arrangements.

[0133] Additionally, decreasing the load capacitance C.sub.Load (not shown) connected across the output of the ring oscillator 14 leads to an increase in the frequency of the ring oscillator 14. It will be appreciated that this load capacitance C.sub.Load may be seen as the total device and additional load capacitance on each node.

[0134] FIG. 9 is a graph illustrating the dependence of the intersection level of the differential outputs of the ring oscillators 14, 14′ on the control voltage V.sub.ctrl. Those skilled in the art will appreciate that the graph of FIG. 9 demonstrates that the crossing/intersection level of the single-ended output signals maintain levels near the oscillator common mode level, i.e. V.sub.DD/2, across a wide range of tuning conditions.

[0135] FIGS. 10A-C are circuit and schematic diagrams of an inverter sub-cell 102 for use in a symmetric pseudo-differential delay cell. Specifically, FIG. 10A shows a circuit diagram and symbol for the inverter sub-cell 102; FIG. 10B shows a small signal model of the inverter sub-cell 102; and FIG. 100 shows a simplified small signal model of the inverter sub-cell 102.

[0136] As can be seen in FIG. 10A, the inverter sub-cell 102 is constructed from PMOS and NMOS UTBB-FDSOI transistors 104, 106 arranged in series such that their drain terminals are connected at a drain node 110 that supplies the output voltage v.sub.out. The gate terminals of the transistors 104, 106 are connected together and receive the input voltage yin.

[0137] In this arrangement, the back-gate terminals of the two transistors 104, 106 are connected together and both receive the same back-gate control voltage v.sub.bg. This arrangement is used as a building block in the delay cell arrangements of FIGS. 11 and 12 as described below.

[0138] FIG. 11 is a circuit diagram of a symmetric pseudo-differential delay cell 108 in accordance with a further embodiment of the present invention. As can be seen in FIG. 11, there are two ‘portions’ of the delay cell 108: a pseudo-differential coupling portion 109 and a frequency control portion 111.

[0139] The pseudo-differential coupling portion 109 is constructed from a pair of inverter sub-cells 102a, 102b, where each inverter sub-cell 102a, 102b is constructed from respective PMOS UTBB-FDSOI transistors 104a, 104b and NMOS UTBB-FDSOI transistors 106a, 106b arranged in series such that their drain terminals are connected together at respective drain nodes 110a, 110b.

[0140] The back-gate terminals of these transistors 104a, 104b, 106a, 106b are cross-coupled such that the back-gate terminals of the PMOS and NMOS transistors 104a, 106a in the first inverter sub-cell 102a are connected to the drain node 110b of the second inverter sub-cell 102b; and the back-gate terminals of the PMOS and NMOS transistors 104b, 106b in the second inverter sub-cell 102b are connected to the drain node 110a of the first inverter sub-cell 102a. Thus both types of transistors in the first and second inverter sub-cells 102a, 102b provide the pseudo-differential behaviour.

[0141] The gate terminals of the transistors 104a, 106a of the first inverter sub-cell 102a are connected together and supplied with the positive input voltage vip to the delay cell 108, and the gate terminals of the transistors 104b, 106b of the second inverter sub-cell 102b are connected together and supplied with the negative input voltage vin to the delay cell 108.

[0142] The drain nodes 110a, 110b of the two inverter sub-cells 102a, 102b are arranged to provide the negative voltage output von and positive voltage output vop respectively.

[0143] The frequency control portion 111 is also constructed from a pair of inverter sub-cells 103a, 103b, where each inverter sub-cell 103a, 103b is constructed from respective PMOS UTBB-FDSOI transistors 105a, 105b and NMOS UTBB-FDSOI transistors 107a, 107b arranged in series such that their drain terminals are connected together at respective drain nodes 113a, 113b.

[0144] The drain node 113a of the third inverter sub-cell 103a is connected to the drain node 110a of the first inverter sub-cell 102a within the pseudo-differential coupling portion 109, and thus to the output terminal that provides the negative voltage output von. Similarly, the drain node 113b of the fourth inverter sub-cell 103b is connected to the drain node 110b of the second inverter sub-cell 102b within the pseudo-differential coupling portion 109, and thus to the output terminal that provides the positive voltage output vop.

[0145] The back-gate terminals of the PMOS UTBB-FDSOI transistors 105a, 105b in the inverter sub-cells 103a, 103b in the frequency control portion 111 are connected to a first ‘positive’ control voltage vbgp; and the back-gate terminals of the NMOS UTBB-FDSOI transistors 107a, 107b in the inverter sub-cells 103a, 103b in the frequency control portion 111 are connected to a second ‘negative’ control voltage vbgn.

[0146] Thus in this symmetric arrangement, the pseudo-differential portion 109 and frequency control portion 111 are in parallel to one another, such that the pseudo-differential portion 109 cross-couples the inputs to the delay cell 108 while the frequency control portion 111 controls the time delay of the delay cell 108.

[0147] In order to effect this control of the time delay of the delay cell 108, the two control signals vbgp, vbgn are controlled ‘inversely’ of one another, i.e. as one is increased the other is decreased. Specifically, as the positive control signal vbgp is increased and the negative control signal vbgn is decreased, the frequency of the delay cell 108—i.e. the reciprocal of the time delay of the delay cell—increases. Conversely, as the positive control signal vbgp is decreased and the negative control signal vbgn is increased, the frequency of the delay cell 108 decreases.

[0148] FIG. 12 is a circuit diagram of another symmetric pseudo-differential delay cell 208 in accordance with another embodiment of the present invention.

[0149] The choice between the ‘parallel’ topology of FIG. 11 and the ‘telescopic’ topology of FIG. 12 may be determined by design considerations. The delay cell 108 of FIG. 11 that uses the parallel topology may be faster but have a higher power consumption than the delay cell 208 of FIG. 12 that uses the telescopic topology.

[0150] As can be seen in FIG. 12, there are two ‘portions’ of the delay cell 208: a pseudo-differential coupling portion 209 and a frequency control portion 211.

[0151] The pseudo-differential coupling portion 209 is constructed from a pair of inverter sub-cells 202a, 202b, where each inverter sub-cell 202a, 202b is constructed from respective PMOS UTBB-FDSOI transistors 204a, 204b and NMOS UTBB-FDSOI transistors 206a, 206b arranged in series such that their drain terminals are connected together at respective drain nodes 210a, 210b.

[0152] The back-gate terminals of these transistors 204a, 204b, 206a, 206b are cross-coupled such that the back-gate terminals of the PMOS and NMOS transistors 204a, 206a in the first inverter sub-cell 202a are connected to the drain node 210b of the second inverter sub-cell 202b; and the back-gate terminals of the PMOS and NMOS transistors 204b, 206b in the second inverter sub-cell 202b are connected to the drain node 210a of the first inverter sub-cell 202a. Thus both types of transistors in the first and second inverter sub-cells 202a, 202b provide the pseudo-differential behaviour.

[0153] The gate terminals of the transistors 204a, 206a of the first inverter sub-cell 202a are connected together and supplied with the positive input voltage vip to the delay cell 208, and the gate terminals of the transistors 204b, 206b of the second inverter sub-cell 202b are connected together and supplied with the negative input voltage vin to the delay cell 208.

[0154] The drain nodes 210a, 210b of the two inverter sub-cells 202a, 202b are arranged to provide the negative voltage output von and positive voltage output vop respectively.

[0155] In the telescopic topology of FIG. 12, the frequency control portion 211 is ‘stacked’ around the frequency control portion 209, i.e. the frequency control PMOS UTBB-FDSOI transistors 205a, 205b and NMOS UTBB-FDSOI transistors 207a, 207b that provide control to each of the inverter sub-cells 202a, 202b are positions above and below the corresponding PMOS transistors 204a, 204b and NMOS transistors 206a, 206b respectively, as shown in FIG. 12.

[0156] The back-gate terminals of the PMOS UTBB-FDSOI transistors 205a, 205b in the frequency control portion 211 are connected to a first ‘positive’ control voltage vbgp; and the back-gate terminals of the NMOS UTBB-FDSOI transistors 207a, 207b in the frequency control portion 211 are connected to a second ‘negative’ control voltage vbgn.

[0157] Thus in this symmetric arrangement, the pseudo-differential portion 209 and frequency control portion 211 are stacked telescopically, where the pseudo-differential portion 209 cross-couples the inputs to the delay cell 208 while the frequency control portion 211 controls the time delay of the delay cell 208.

[0158] As in the parallel topology of FIG. 11, the two control signals vbgp, vbgn are controlled ‘inversely’ of one another. Thus, as the positive control signal vbgp is increased and the negative control signal vbgn is decreased, the frequency of the delay cell 208—i.e. the reciprocal of the time delay of the delay cell—increases. Conversely, as the positive control signal vbgp is decreased and the negative control signal vbgn is increased, the frequency of the delay cell 208 decreases.

[0159] FIG. 13 is a schematic diagram showing a circuit symbol for a pseudo-differential delay cell 108, 208 that uses the topology of either FIG. 11 or FIG. 12. The same symbol is used for both topologies, as the connections to the cells 108, 208 are the same, regardless of whether the parallel topology of FIG. 11 or telescopic topology of FIG. 12 is used.

[0160] FIG. 14 is a circuit diagram of a delay line that uses the pseudo-differential delay cell of FIG. 11 or FIG. 12. For clarity of illustration, the individual components of the delay cells 108a-n, 208a-n are not labelled, however the components of each delay cell 108a-n, 208a-n has the same structure and function as those described above in relation to the delay cell 108a-n, 208a-n of FIG. 11 or 12 as appropriate.

[0161] The N delay cells 108a-n, 208a-n are arranged in series such that the negative and positive outputs of each delay cell 108a-(n−1), 208a-(n−1) are connected to the positive and negative inputs of the next delay cell 108b-n, 208b-n in the chain. The differential output—i.e. the difference between the negative outputs ph1, ph2, . . . , phn and positive outputs ph1, ph2, . . . , phn—of each delay cell stage 108a-n, 208a-n is a time-delayed version of the differential input to that delay cell stage 108a-n, 208a-n.

[0162] By varying the value of the two control voltages vbgp, vbgn, the time delay introduced by each delay cell 108a-n, 208a-n is varied, and thus the total propagation delay of the delay line 112 is also varied.

[0163] FIGS. 15A and 15B are circuit diagrams ring oscillators 112, 112′ that use the pseudo-differential delay cells 108, 208 of FIG. 11 or FIG. 12 with an odd and even number of cells respectively. It will be appreciated that, like the ring oscillators of FIGS. 6A and 6B, the number N of stages may be selected as appropriate, where an odd number N of cells may be used as per the topology of FIG. 14A, and an even number N of cells may be used as per the topology of FIG. 14B, as outlined below.

[0164] As can be seen in FIG. 14A, the ring oscillator 114 is constructed from an odd number N of the delay cells 108a, 108b, . . . , 108n of FIG. 11, or delay cells 208a, 208b, . . . , 208n of FIG. 12, arranged in series, in a loop. For clarity of illustration, the individual components of the delay cells 108a-n, 208a-n are not labelled, however the components of each delay cell 108a-n, 208a-n has the same structure and function as those described above in relation to the delay cells 108, 208 of FIGS. 11 and 12 as appropriate.

[0165] In the ring oscillator 114 with an odd number of cells shown in FIG. 15A, the output of the ‘last’ delay cell 108n, 208n is connected back to the input of the ‘first’ delay cell 108a, 208a. It will of course be appreciated that the terms ‘first’ and ‘last’ are used to provide contrast to the delay cells in the delay line 112, as there is no ‘first’ or ‘last’ delay cell by virtue of it being a loop. The inverting output of each delay cell stage 108a-n, 208a-n is connected to the non-inverting input of the next delay cell stage 108a-n, 208a-n in the loop. Similarly, the non-inverting output of each delay cell stage 108a-n, 208a-n is connected to the inverting input of the next delay cell stage 108a-n, 208a-n in the loop

[0166] Conversely, the ring oscillator 114′ of FIG. 15B uses an even number N of delay cells 108a-n, 208a-n arranged in series, in a loop. In this arrangement, the inverting output of all but the last delay cell stage 108a-(n−1), 208a-(n−1) is connected to the non-inverting input of the next delay cell stage 108b-n, 208b-n in the loop; and the non-inverting output of all but the last delay cell stage 108a-(n−1), 208a-(n−1) is connected to the inverting input of the next delay cell stage 108b-n, 208b-n in the loop.

[0167] However, when using an even number N of delay cells 108a-n, 208a-n, the inverting and non-inverting outputs of one of the delay cells are ‘crossed over’ so that they are connected to inverting and non-inverting inputs respectively (rather than to their opposite type as in the rest of the cases). In this example, the inverting and non-inverting outputs of the ‘last’ delay cell stage 108n, 208n are respectively connected to the inverting and non-inverting outputs of the first delay cell stage 108a, 208a. It will, of course, be appreciated that the term ‘last’ is arbitrary in a loop structure, and any selected one of the even number N of delay cells 108a-n, 208a-n may have its outputs ‘crossed over’ in this way.

[0168] The loops of these ring oscillators 114, 114′ are ‘unstable’ and, assuming a sufficiently high gain for each stage, the output of each delay cell stage 108a-n, 208a-n alternates between a high value and a low value, providing a substantially square waveform at each output.

[0169] By varying the value of the two control voltages vbgp, vbgn, the time delay introduced by each delay cell 108a-n, 208a-n is varied, and thus the frequency of the ring oscillator 114, 114′ is also varied.

[0170] Thus it will be appreciated by those skilled in the art that embodiments of the present invention provide improved time delay circuits, including delay line and ring oscillator circuits, where linear control of the time delay is provided through a voltage applied to the back-gate of a suitable transistor (including but not limited to a UTBB-FDSOI transistor).

[0171] Those skilled in the art will appreciate that the specific embodiments described herein are merely exemplary and that many variants within the scope of the invention are envisaged.