Current detection circuit

Abstract

To provide a current detection circuit which suppresses a change in characteristics of a PMOS transistor on the non-inversion input terminal side of a differential amplifier due to NBTI and causes no change in threshold value at which an output voltage of the current detection circuit is inverted. A voltage limiting circuit which limits a voltage drop is provided between a non-inversion input terminal of a differential amplifier and a source of a PMOS transistor on the inversion input terminal side.

Claims

1. A current detection circuit comprising: a sense resistor provided in a power supply line; and a differential amplifier which detects a current flowing through the power supply line by a voltage across the sense resistor, wherein the sense resistor is connected to an inversion input terminal and a non-inversion input terminal of the differential amplifier at both ends, wherein the differential amplifier includes a first resistor, a first PMOS transistor, and a first current source which are connected in series between the inversion input terminal and GND, wherein the differential amplifier includes a second resistor, a second PMOS transistor, and a second current source which are connected in series between the non-inversion input terminal and GND, wherein the first PMOS transistor has a gate and a drain connected to a gate of the second PMOS transistor, wherein the second PMOS transistor has a drain connected to an output terminal of the differential amplifier, and wherein a voltage limiting circuit which limits a voltage drop is provided between the non-inversion input terminal and a source of the first PMOS transistor.

2. The current detection circuit according to claim 1, wherein the voltage limiting circuit is an NMOS transistor which has a gate and a drain connected to the non-inversion input terminal, and a source connected to the source of the first PMOS transistor.

3. The current detection circuit according to claim 1, wherein the voltage limiting circuit is a third PMOS transistor which has a source connected to the non-inversion input terminal, and a gate and a drain connected to the source of the first PMOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram of a current detection circuit according to a first embodiment;

(2) FIG. 2 is a circuit diagram of a current detection circuit according to a second embodiment;

(3) FIG. 3 is a circuit diagram of a related art current detection circuit; and

(4) FIG. 4 is a waveform illustrating the operation of a current detection circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) The present embodiments will hereinafter be described with reference to the accompanying drawings.

First Embodiment

(6) FIG. 1 is a circuit diagram of a current detection circuit according to a first embodiment.

(7) The current detection circuit according to the first embodiment is equipped with a resistor 101 as a sense resistor, and a differential amplifier 120. The differential amplifier 120 is equipped with resistors 106 and 107, PMOS transistors 108 and 109, current sources 110 and 111, and an NMOS transistor 112.

(8) The resistor 101 converts a current flowing through a power supply line 100 into a voltage. The differential amplifier 120 detects the voltage generated in the resistor 101.

(9) The resistor 101 is connected to a non-inversion input terminal 103 and an inversion input terminal 102 of the differential amplifier 120 at both ends thereof.

(10) The resistor 106 has one terminal connected to the inversion input terminal 102, and the other terminal connected to a source of the PMOS transistor 108. The resistor 107 has one terminal connected to the non-inversion input terminal 103, and the other terminal connected to a source of the PMOS transistor 109. The PMOS transistor 108 has a gate and a drain connected to one terminal of the current source 110 and a gate of the transistor 109. The PMOS transistor 109 has a drain connected to one terminal of the current source 111 and an output terminal 104. The NMOS transistor 112 has a gate and a drain connected to the non-inversion input terminal 103, and a source connected to the source of the PMOS transistor 108, A substrate is connected to GND.

(11) FIG. 4 illustrates operating waveforms where assuming that the voltage of the non-inversion input terminal 103 is a constant voltage, the resistance value of the resistor 101 is R.sub.S, and the current flowing through the resistor 101 is I.sub.S, the current I.sub.S is changed. When the resistors 106 and 107 are equal in resistance value as R, the PMOS transistors 108 and 109 are equal in characteristics, the current sources 110 and 111 are equal in current value as I, and the voltage of the non-inversion input terminal 103 is defined as VIN+, a source voltage V.sub.S1 of the PMOS transistor 109 is expressed as follows:
V.sub.S1=(VIN+)−I×R

(12) Also assuming that a source-gate voltage of the PMOS transistor 108 is V.sub.SG11, a gate voltage V.sub.G1 of the PMOS transistors 108 and 109 when the current I.sub.S is changed is expressed as follows:
V.sub.G1=(VIN+)−I.sub.S×R.sub.S−I×R−V.sub.SG11

(13) From the above, a source-gate voltage V.sub.SG12 of the PMOS transistor 109 is expressed as follows:
V.sub.SG12=V.sub.S1−V.sub.G1=I.sub.S×R.sub.S+V.sub.SG11

(14) It is understood that when the current I.sub.S is increased to plus, the gate voltage V.sub.G1 drops, and the source-gate voltage V.sub.SG12 increases.

(15) Here, since the NMOS transistor 112 is connected, the voltage drop of the gate voltage V.sub.G1 is limited. The NMOS transistor 112 has transistor characteristics which allow a sufficient current to flow. Assuming that the threshold voltage of the NMOS transistor 112 is Vth, the following equation is established:
V.sub.G1′=(VIN+)−Vth−V.sub.SG11

(16) Thus, the voltage drop is limited by this voltage. From the above, the source-gate voltage V.sub.SG12 of the PMOS transistor 109 is represented by the following equation:
V.sub.SG12′=V.sub.S1−V.sub.G1′=Vth+V.sub.SG11−I×R

(17) Thus, the source-gate voltage V.sub.SG12 is prevented from becoming a voltage not greater than a constant value regardless of the current I.sub.s even when the current I.sub.S is increased to plus.

(18) Thus, since a change in the characteristics of the PMOS transistor 109 of the differential amplifier due to NBTI is suppressed, the current detection circuit does not change the threshold value at which its output voltage is inverted. On the other hand, when the current I.sub.S is increased to minus, it does not affect the circuit operation of the current detection circuit.

(19) FIG. 2 is a circuit diagram of a current detection circuit according to a second embodiment. A difference from the current detection circuit according to the first embodiment is that a PMOS transistor 212 is provided instead of the NMOS transistor 112. The PMOS transistor 212 has a source connected to a non-inversion input terminal 103, and a gate and a drain connected to a source of a PMOS transistor 108. A substrate is connected to the highest power supply within the circuit.

(20) Since the PMOS transistor 212 is connected, a voltage drop of a gate voltage V.sub.G1 of the PMOS transistor 108 and a PMOS transistor 109 is limited. The PMOS transistor 212 has transistor characteristics which allow a sufficient current to flow. Assuming that the threshold voltage of the NMOS transistor 112 is |Vth|, the following equation is established:
V.sub.G1′=(VIN+)−|Vth|−V.sub.SG11

(21) Thus, the voltage drop is limited by this voltage. From the above, a source-gate voltage V.sub.SG12 of the PMOS transistor 109 is represented by the following equation:
V.sub.SG12′=V.sub.S1−V.sub.G1′=|Vth|+V.sub.SG11−I×R

(22) Thus, the source-gate voltage V.sub.SG12 of the PMOS transistor 109 is prevented from becoming a voltage not greater than a constant value regardless of the current I.sub.S even when the current I.sub.S is increased to plus.

(23) Thus, since a change in the characteristics of the PMOS transistor 109 of a differential amplifier due to NBTI is suppressed, the current detection circuit does not change the threshold value at which its output voltage is inverted. On the other hand, when the current I.sub.S is increased to minus, it does not affect the circuit operation of the current detection circuit.

(24) As described above, according to the current detection circuit of the present embodiment, an effect is brought about that since it is possible to limit the voltage drop at the gate of the PMOS transistor according to the voltage of the non-inversion input terminal, the change in the characteristics of the PMOS transistor on the non-inversion input terminal side of the differential amplifier due to NBTI is suppressed, and hence the threshold value at which the output voltage of the current detection circuit is inverted is not changed.