BACKSIDE EMITTER SOLAR CELL STRUCTURE HAVING A HETEROJUNCTION AND METHOD AND DEVICE FOR PRODUCING THE SAME

Abstract

A backside emitter solar cell structure having a heterojunction, and a method and a device for producing the same. A backside intrinsic layer is first formed on the back side of the substrate, then a frontside intrinsic layer and a frontside doping layer are formed on the front side of the substrate, and finally a backside doping layer is formed on the back side of the substrate.

Claims

1. A device for producing a backside emitter solar cell structure with a heterojunction, wherein the solar cell structure includes: an absorber made of a crystalline semiconductor substrate having a doping of a first conductivity type; at least one frontside intrinsic layer formed on a front side of the absorber and made of an intrinsic, amorphous semiconductor material; at least one backside intrinsic layer formed on a back side of the absorber and made of an intrinsic, amorphous semiconductor material; at least one frontside doping layer formed on the at least one frontside intrinsic layer from an amorphous semiconductor material having a doping of the first conductivity type which is higher than the doping of the absorber; an emitter of at least one backside doping layer formed on the at least one backside intrinsic layer and made of an amorphous semiconductor material having a doping of a second conductivity type, which is opposite to the first conductivity type; at least one electrically conductive, transparent frontside conduction layer formed on the at least one frontside doping layer; at least one electrically conductive, transparent backside conduction layer formed on the at least one backside doping layer; a frontside contact formed on the at least one frontside conduction layer; and a backside contact formed on the at least one backside conduction layer; and the device for producing the backside emitter solar cell structure comprising: no more than three layer deposition strands for producing the at least one frontside intrinsic layer on the front side of the semiconductor substrate, the at least one backside intrinsic layer on the back side of the semiconductor substrate, the at least one frontside doping layer on the at least one frontside intrinsic layer, and the at least one backside doping layer on the at least one backside intrinsic layer; said layer deposition strands including a first layer deposition strand having at least one layer deposition reactor for producing the at least one backside intrinsic layer on the back side of the semiconductor substrate; said layer deposition strands including a second layer deposition strand having at least one layer deposition reactor for producing the at least one frontside intrinsic layer on the front side of the semiconductor substrate and for producing the at least one frontside doping layer on the at least one frontside intrinsic layer; and said layer deposition strands including a third layer deposition strand having at least one layer deposition reactor for producing the at least one backside doping layer on the at least one backside intrinsic layer; and at least one substrate transport and turning system between said first and second layer deposition strands and between said second and third layer deposition strands.

2. The device according to claim 1, wherein: said first layer deposition strand has a backside intrinsic layer deposition reactor for producing the at least one backside intrinsic layer on the back side of the semiconductor substrate; the second layer deposition strand has a single frontside layer deposition reactor for producing the at least one frontside intrinsic layer on the frontside of the semiconductor substrate and the at least one frontside doping layer on the at least one frontside intrinsic layer; the third layer deposition strand has a backside doping layer deposition reactor for producing the at least one backside doping layer on the at least one backside intrinsic layer; and the at least one substrate transport and turning system is disposed upstream of said frontside layer deposition reactor before or in said second layer deposition strand.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0100] FIGS. 1a to 1i: schematically represent partial steps of a process sequence of an embodiment of the method according to the invention for producing a backside emitter solar cell structure having heterojunction using cross-sectional views of the layer sequence generated in each case;

[0101] FIG. 2 schematically shows a layer stack formed on a side edge of an intermediate product of a backside emitter solar cell structure having heterojunction according to the invention after the formation of the intrinsic and amorphous semiconductor layers;

[0102] FIG. 3 schematically shows a possible basic structure of a partial region of a device according to the invention for producing backside emitter solar cell structures having a heterojunction; and

[0103] FIG. 4 schematically shows a further possible basic structure of a partial region of the device according to the invention for producing backside emitter solar cell structures having a heterojunction.

DETAILED DESCRIPTION OF THE INVENTION

[0104] FIG. 1a to 1i schematically show partial steps of a process sequence of an embodiment of the method according to the invention for producing a backside emitter solar cell structure 1 having a heterojunction, as is shown schematically in cross-section, for example, in FIG. 1i, using cross-sections of each layer sequence produced. The layer thicknesses of the layers shown in the individual figures are not shown to scale. Although the ratio of the respective layer thicknesses to one another is also not shown to scale, if one layer is shown thinner than another, this is typically also thinner in reality.

[0105] In the figures, the side of the respective layer structure shown above is the front side and the side shown below is the back side of the respective layer structure. The front side is the side into which light is provided in the finished backside emitter solar cell structure 1.

[0106] FIG. 1 a schematically shows a crystalline semiconductor substrate 2, on the front side and back side of which air oxide layers 21, 22 are formed. The semiconductor substrate 2 has a doping of a first conductivity type. In the exemplary embodiment shown, the semiconductor substrate 2 is an n-doped silicon substrate, but in other embodiments of the invention can also be formed from another semiconductor material and/or have a p-type doping. The n-doping is preferably a phosphorus doping, but can also be formed with at least one other and/or at least one additional dopant.

[0107] The air oxide layers 21, 22 in the example shown are SiO.sub.2 layers having a thickness between 0.2 and 3.0 nm.

[0108] The air oxide layers 21, 22 automatically form in the atmosphere on the previously cleaned semiconductor substrate 2. The semiconductor substrate 2 forms an absorber in the finished backside emitter solar cell structure 1.

[0109] FIG. 1b shows the semiconductor substrate 2 from FIG. 1a after a further method step, in which the semiconductor substrate 2 is loaded into a device for producing backside emitter solar cell structures 1 having heterojunction. Portions of examples of such devices 30, 40 are shown in FIGS. 3 and 4.

[0110] During charging, both sides of the semiconductor substrate 2 are exposed to the atmosphere at temperatures of typically below 200° C., so that air oxide layers 23, 24, that is to say here SiO.sub.2 layers having a thickness of 0.2 to 3.0 nm, again form on the front side and the back side of the semiconductor substrate 2 or the air oxide layers 21, 22 grow by the thickness of the air oxide layers 23, 24.

[0111] In a further process step of the method according to the invention, shown schematically in FIG. 1c, at least one backside intrinsic layer 3 made of an intrinsic, amorphous semiconductor material is deposited on the back side of the semiconductor substrate 2 having the air oxide layers 21, 22, 23, 24. The at least one backside intrinsic layer 3 is preferably deposited using a PECVD method.

[0112] In the step shown in FIG. 1d, by transporting and turning the layer structure from FIG. 1c to the next layer deposition reactor, air oxide layers 25, 26 are in turn formed on the front side and back side of the layer structure from FIG. 1c. The air oxide layers 25, 26 in the example shown are SiO.sub.2 layers having a thickness of 0.2 to 3.0 nm. The air oxide layer 25 grows directly on the air oxide layers 21, 23 that already exist on the front side. The air oxide layer 26 grows on the deposited backside intrinsic layer 3.

[0113] After the backside intrinsic layer 3 has been deposited, at least one frontside intrinsic layer 4 made of at least one amorphous intrinsic semiconductor material and at least one frontside doping layer 5 made of at least one amorphous semiconductor material having a doping of the first conductivity type which is higher than the doping of the semiconductor substrate 2, are deposited on the front side of the semiconductor substrate 2 with the layers 21, 23, 25 thereon. This can be seen in FIG. 1e. Since the semiconductor substrate 2 is n-doped in the exemplary embodiment shown, the frontside doping layer 5 is also n-doped, preferably doped with phosphorus.

[0114] The frontside intrinsic layer 4 can be deposited separately from the frontside doping layer 5 in different layer deposition reactors. However, it is particularly advantageous if, as has been done in the exemplary embodiment shown, the frontside doping layer 5 is deposited directly after the frontside intrinsic layer 4 in one and the same layer deposition reactor without intermediate substrate handling. In this case, formation of air oxide between the frontside intrinsic layer 4 and the frontside doping layer 5 is avoided.

[0115] In the case of the substrate handling required after this layer deposition or these layer depositions, during which a substrate transport to the next layer deposition reactor takes place and the substrate is turned again, the layer structure produced and shown schematically in FIG. 1e again reaches the atmosphere, which in turn causes air oxide layers 27, 28 on both sides of the layer structure grow, which is shown in FIG. 1f. The air oxide layers 27, 28 in the exemplary embodiment are SiO.sub.2 layers having a layer thickness between 0.2 and 3.0 nm.

[0116] After a further substrate handling, a backside doping layer 6 is produced from an amorphous semiconductor material having a doping of a second conductivity type, which is opposite to the first conductivity type, on the back side of the layer arrangement shown in FIG. 1f. This is shown in FIG. 1g. In the exemplary embodiment shown, the backside doping layer 6 is a p-doped, amorphous silicon layer. Specifically, the p-type doping used in the example is a boron-type doping, but can be a different doping in other exemplary embodiments of the invention. The backside doping layer 6 forms the electrical contacting provided thereon, which is described below, and forms the emitter of the backside emitter solar cell structure 1 to be formed having a heterojunction.

[0117] The layer structure from FIG. 1g is subsequently transported to at least one further layer deposition reactor, the layer structure being again exposed to atmospheric conditions during the transport. Approximately 0.2 to 3.0 nm thin air oxide layers 29, 30 are again formed on the front side and the back side of the layer structure, which can be seen in FIG. 1h.

[0118] Thereafter, as is shown schematically in FIG. 1i, electrically conductive, transparent frontside and backside conduction layers 7, 8 are produced on the front side and the back side of the layer structure from FIG. 1h. The electrically conductive, transparent frontside and backside conduction layers 7, 8 preferably consist of electrically conductive, transparent oxide (TCO). In the exemplary embodiment shown, the electrically conductive, transparent frontside and backside conduction layers 7, 8 are indium tin oxide layers (ITO layers).

[0119] In the exemplary embodiment shown, the electrically conductive, transparent backside conduction layer 8 is deposited on the at least one backside doping layer 6 at a distance from the side edge 50 of the semiconductor substrate 2. The backside doping layer 6 can be deposited, for example, via a mask. As a result, an edge region 51 on the back side of the backside emitter solar cell structure 1 having a heterojunction from the electrically conductive, transparent backside conductor layer 8 remains uncoated. Due to the structured deposition, there is no electrical contact between the electrically conductive, transparent backside conduction layer 8 and the frontside conduction layer 7, not even during the deposition of the electrically conductive, transparent backside conduction layer 8.

[0120] Finally, frontside and backside contacts 9, 10 are produced on the electrically conductive, transparent frontside and backside conduction layers 7, 8, respectively. In the exemplary embodiment shown, the frontside and backside contacts 9, 10 are made of silver and are provided in finger shape on the front side and back side of the solar cells. However, they can also be formed from another, electrically conductive material and/or applied in a different form.

[0121] As can be seen from the above statements, with each substrate transport air oxide layers 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 arise, which form barriers between the semiconductor substrate 2 and the intrinsic layers 3, 4 deposited thereon, between the backside intrinsic layer 4 and the backside doping layer 6 as well as between the frontside and backside doping layers 5, 6 and the respectively frontside and backside conduction layers 7, 8 deposited thereon. These barriers hinder the conductor carrier transport and thus deteriorate the solar cell properties of the backside emitter solar cell structure 1 to be formed having a heterojunction. As described above, by depositing the frontside doping layer 5 directly after the frontside intrinsic layer 4 in the same layer deposition reactor, such a barrier formation between the frontside intrinsic layer 4 and the frontside doping layer 5 could be avoided.

[0122] Furthermore, the process step sequence according to the invention, in which the boron-doped backside doping layer 6 is deposited as the last of the amorphous semiconductor layers, limits the outdiffusion of boron, which has a higher diffusion coefficient than the phosphorus contained in the frontside doping layer 5, from the backside doping layer 6 to a minimum. This also advantageously influences the solar cell properties of the backside emitter solar cell structure 1 to be formed having a heterojunction.

[0123] As can be seen schematically in FIG. 2, the procedure according to the invention also has further advantageous effects. FIG. 2 schematically shows an intermediate product of the backside emitter solar cell structure 1 according to the invention having a heterojunction from FIG. 1i. While in FIGS. 1a to 1i the layer sequences forming at the solar cell edge have been omitted for the sake of clarity, this layer sequence is shown in FIG. 2 after the amorphous semiconductor layers 3, 4, 5 and 6 have been deposited and before the formation of the further layers 7, 8, 9, 10 particularly large.

[0124] Starting from the n-doped semiconductor substrate 2 in the illustrated embodiment, a n-i-i-n.sup.+-p layer sequence results at the edge of the solar cell. In contrast, in the prior art, the conventional process sequence results in an n-i-n.sup.+-i-p layer sequence. The double intrinsic layer 3, 4 on the edge or on the side edge of the semiconductor substrate 2 seems to protect the formed structure particularly against the formation of shunt resistances and leakage currents at the edge of the solar cell.

[0125] FIGS. 3 and 4 schematically show partial areas of possible system concepts or devices 30, 40 for the production of backside emitter solar cell structures 1 having a heterojunction, as described above. The device 30, which is shown schematically in regions in FIG. 3, and the device 40, which is shown in regions in FIG. 4, each have three layer deposition strands 31, 32 and 42, 33 for the formation of the amorphous semiconductor layers 3, 4, 5, 6.

[0126] In a first layer deposition strand 31, at least one layer deposition reactor 36 is provided for producing the at least one backside intrinsic layer 3 on the back side of the semiconductor substrate 2.

[0127] In a second layer deposition strand 32 or 42, there is at least one layer deposition reactor 39, 41; 44 for producing the at least one frontside intrinsic layer 4 on the front side of the semiconductor substrate 2 and for producing the at least one frontside doping layer 5 on the at least one frontside intrinsic layer 4. In the device 40, the second layer deposition strand 42 has only a single frontside layer deposition reactor 44 for producing the at least one frontside intrinsic layer 4 on the front side of the semiconductor substrate 2 and the at least one frontside doping layer 5 on the at least one frontside intrinsic layer 4.

[0128] In a third layer deposition strand 33, at least one layer deposition reactor 43 is provided for producing the at least one backside doping layer 6 on the at least one backside intrinsic layer 3.

[0129] A substrate transport and turning system 37 is provided in each case between the first layer deposition strand 31 and the second layer deposition strand 32 or 42 and between the second layer deposition strand 32 or 42 and the third layer deposition strand 33. In the devices 30, 40, only a single substrate transport and turning system 37 is provided, which is located in front of the frontside layer deposition reactor(s) 39, 41 and 44, respectively.

[0130] A lock device 45 is provided between and in front of the individual layer deposition reactors.

[0131] A loading and unloading device 35 is provided at the beginning of each layer deposition strand 31, 32 and 42, 33.