ARRANGEMENT AND METHOD FOR PERFORMING A VECTOR-MATRIX MULTIPLICATION BY MEANS OF CAPACITIVE OR RESISTIVE SYNAPTIC COMPONENTS

Abstract

A method and arrangement for performing a vector-matrix multiplication by synaptic components includes—a matrix arrangement of components in a differential arrangement, which are periodically charged and discharged; and—a clock generator, which connects the bit lines alternately to a charge integration amplifier or to a ground by means of a changeover switch. The method and arrangement addresses the problem of implementing a switched capacitor arrangement which uses capacitive, resistive or capacitive-resistive components and which uses different variations of an alternating voltage signal as an input variable. The word lines of the matrix are connected to one or more oscillators and the clock generator either reacts to rising or falling voltages of the oscillators or reacts to a positive or negative value range of the voltage of the oscillators.

Claims

1. An arrangement for performing a vector-matrix multiplication by means of synaptic components, comprising a matrix arrangement of capacitive synaptic components or resistive synaptic components or mixed capacitive-resistive synaptic components in a differential arrangement, with periodic charging and discharging, and a clock generator, wherein: the clock generator is designed to alternately connect the bit lines to a charge integration amplifier or ground via a changeover switch or is designed to alternately connect the bit lines to a non-inverting input and an inverting input of the charge integration amplifier via a changeover switch, the word lines are electrically connected to one or more oscillators, the clock generator is designed to react to a rising or falling edge of the voltage of the oscillator or to the positive and negative value range of the voltage of the oscillator.

2. The arrangement as claimed in claim 1, wherein, in the case of capacitive synaptic components, in particular positively defined capacitances and negatively defined capacitances, the clock generator is designed to react to a rising or falling edge of the voltage of the oscillator.

3. The arrangement as claimed in claim 1, wherein, in the case of capacitive synaptic components, in particular positively defined capacitances and negatively defined capacitances, the bit line is connected to ground via a fixed capacitance and the clock generator is designed to react to the positive and negative value range of the voltage of the oscillator.

4. The arrangement as claimed in claim 1, wherein, in the case of resistive synaptic components, in particular positively defined resistances and negatively defined resistances, the clock generator is designed to react to the positive and negative value range of the voltage of the oscillator.

5. The arrangement as claimed in claim 1, wherein the charge integration amplifier is constructed from a current mirror mirroring the charge to be measured to the integration capacitance.

6. The arrangement as claimed in claim 1, wherein, in the charge integration amplifier, the integration capacitance is connected to the changeover switch via a gate circuit.

7. The arrangement as claimed in claim 1, wherein, in the charge integration amplifier, the integration capacitance is directly connected to the changeover switch.

8. The arrangement as claimed in claim 1, wherein, in the charge integration amplifier, the integration capacitance appears in an enlarged form at the input of the charge integration amplifier via the Miller effect.

9. The arrangement as claimed in claim 1, wherein the oscillators have an energy store which can recover the charges stored in the capacitive synaptic components for further use.

10. The arrangement as claimed in claim 9, wherein the energy store is implemented by means of an inductance.

11. A method using the arrangement as claimed in claim 2, wherein periodic AC voltages are applied to the word lines, and wherein: the AC voltages have a fixed phase relationship, in the case of an alternating connection between ground and the input of the charge integration amplifier, the bit line of the positively provided capacitances is connected to the input of a charge integration amplifier when there is a positive gradient in the positively defined AC voltage signal of the word line, and is otherwise connected to ground, the bit line of the capacitances provided as negative is connected to the input of the charge integration amplifier when there is a negative gradient in the positively defined AC voltage signal of the word line, and is otherwise connected to ground, in the case of an alternating connection between the inverting input and the non-inverting input of the charge integration amplifier the positively provided capacitances are connected to the non-inverting input of a charge integration amplifier when there is a positive gradient in the positively defined AC voltage signal of the word line, and are otherwise connected to the inverting input, and the negatively provided capacitances are connected to the non-inverting input of a charge integration amplifier when there is a negative gradient in the positively defined AC voltage signal of the word line, and are otherwise connected to the inverting input, and wherein, in the case of a negatively defined AC voltage signal, the positive and negative gradients are swapped in time on the word line.

12. A method using the arrangement as claimed in claim 3, wherein periodic AC voltages are applied to the word lines, and wherein: the AC voltages have a fixed phase relationship, in the case of an alternating connection between ground and the input of the charge integration amplifier the positively provided capacitances or resistances are connected to the input of a charge integration amplifier when there is a positive value range in the positively defined AC voltage signal of the word line, and are otherwise connected to ground, the bit line of the capacitances or resistances provided as negative is connected to the input of the charge integration amplifier when there is a negative value range in the positively defined AC voltage signal of the word line, and is otherwise connected to ground, in the case of an alternating connection between the inverting input and the non-inverting input of the charge integration amplifier the positively provided capacitances or resistances are connected to the non-inverting input of a charge integration amplifier when there is a positive value range in the positively defined AC voltage signal of the word line, and are otherwise connected to the inverting input, and the negatively provided capacitances or resistances are connected to the non-inverting input of a charge integration amplifier when there is a negative value range in the positively defined AC voltage signal of the word line, and are otherwise connected to the inverting input, and wherein, in the case of a negatively defined AC voltage signal, the positive and negative value ranges are swapped in time on the word line.

13. A method using the arrangement as claimed in claim 1, wherein periodic AC voltages are applied to the word lines, and wherein: in the case of mixed capacitive-resistive synaptic components and in the case of an alternating connection between ground and the input of the charge integration amplifier the bit line of the capacitive-resistive components provided as positive is connected to the input of the charge integration amplifier at any time for a period of half a period duration of the positively defined AC voltage signal and is connected to ground for a subsequent period of half a period duration of the positively defined AC voltage signal, the periods for a connection between the bit line and the charge integration amplifier and between the bit line and ground are swapped in the case of the negatively provided capacitive-resistive components, in the case of an alternating connection between the inverting input and the non-inverting input of the charge integration amplifier the bit line of the capacitive-resistive components provided as positive is connected to the non-inverting input of the charge integration amplifier at any time for a period of half a period duration of the positively defined AC voltage signal and is connected to the inverting input for a subsequent period of half a period duration of the positively defined AC voltage signal, the periods for a connection between the bit line and the non-inverting input of the charge integration amplifier and between the bit line and the inverting input are swapped in the case of the negatively provided capacitive-resistive components, and wherein, in the case of a negatively defined AC voltage signal on the word line, the two periods are likewise swapped.

14. The method as claimed in one of claim 11, wherein: the AC voltage signals (12) are harmonic, and positive and negative AC voltage signals (14, 16) are phase-shifted through 180°.

15. The method as claimed in one of claim 11, wherein: the input variable can be represented either as a variable number of periods, or as a phase shift, or as an amplitude change, or as a frequency change of the AC voltage signal, or as a changed DC component of the AC voltage signal, or as a combination of the changes mentioned above.

16. The method as claimed in claim 13, wherein the weights in a mixed capacitive-resistive matrix can also be set by means of the complex and real parts for a constant impedance and cause a phase shift of the AC voltage signal.

17. The method as claimed in one of claim 11, wherein a plurality of AC voltage signals are applied to the word lines in a parallel manner and differ in terms of the frequency, and a plurality of charge integration amplifiers which are each responsible for the individual frequency bands are respectively situated on the bit lines.

18. The method as claimed in claim 17, wherein the charge integration amplifier selects the appropriate frequency at the input using a bandpass filter and is constructed, for example, in the form of a lock-in amplifier.

19. The method as claimed in one of claim 11, wherein the frequency of the applied AC voltage signal is minimized in the case of capacitive synaptic components to such an extent that resistive losses in the supply lines of the matrix arrangement and in the capacitive synaptic component itself are smaller by at least one order of magnitude than the capacitive energy supply.

Description

[0044] The invention shall be explained in more detail below on the basis of a plurality of exemplary embodiments. In the associated drawings:

[0045] FIG. 1: shows a circuit design with an oscillator, a clock generator, a changeover switch, a charge integration amplifier and a capacitive matrix as well as the alternating signals applied to the word lines

[0046] FIG. 2: shows a circuit design and alternating signal relationships for a resistive matrix

[0047] FIG. 3: shows a circuit design and alternating signal relationships for a capacitive matrix with a charge integration amplifier having an inverting input and a non-inverting input

[0048] FIG. 4: shows a circuit design and alternating signal relationships for a capacitive matrix with an additional fixed capacitance on each bit line

[0049] FIG. 5: shows harmonic alternating signals for a capacitive matrix

[0050] FIG. 6: shows harmonic alternating signals for a mixed capacitive-resistive matrix

[0051] FIG. 7: shows a charge integration amplifier with a current mirror

[0052] FIG. 8: shows a charge integration amplifier with a gate circuit

[0053] FIG. 9: shows the influence of the phase shift on the integrated charge for an arbitrary alternating signal, and the variation of the number of periods and the amplitude

[0054] FIG. 10: shows the influence of the phase shift on the integrated charge for a harmonic alternating signal, and the variation of the number of periods and the amplitude

[0055] FIG. 11: shows the application of a plurality of alternating signals in different frequency bands.

[0056] As illustrated in FIG. 1, a plurality of AC voltages (12) which differ in terms of the phase, amplitude or the number of periods are applied to the word lines (3). Since there is a capacitive matrix arrangement (2) in this case, the capacitive synaptic components (2) react to rising or falling edges and the clock generator (5) outputs a positive signal when there is a rising edge in the positively defined AC voltage signal (14). In this case, the changeover switch (S1) will connect the positively defined synaptic components (13) to the charge integration amplifier (9). The changeover switch (S2) connects the negatively defined synaptic components (15) to ground (8) in this position, that is to say S1 and S2 switch in an opposite manner. The negatively defined synaptic components (15) are connected to the charge integration amplifier (9) when there is a falling edge in the positively defined AC voltage signal (14). Overall, this results in a positively defined AC voltage signal causing a charge in the charge integration amplifier (9) for the positively defined synaptic components (13) and causing a discharge for the negatively defined synaptic components (15). For negatively defined AC voltage signals (16), the rising and falling edges are swapped in time, that is to say the positively defined synaptic components (13) cause a discharge, while the negatively defined synaptic components (15) cause a charge. This achieves a four-quadrant multiplication. The AC voltage signals are realized by means of oscillators (4). FIG. 1 likewise illustrates, by way of example, a smaller number of periods for the negatively defined AC voltage signal (16) than for the positively defined AC voltage signals (14). This is a possible way of setting the magnitude of the input signal with respect to the word line (3) since, in this example, the positively defined synaptic components (13) are charged more frequently than discharged.

[0057] FIG. 2 explains the case for resistive synaptic components (19). In this case, the components cause a charge and a discharge for AC voltage signals (12) in the positive and negative value range. Accordingly, the clock generator (5) reacts to the positive and negative value range of the AC voltage signal, rather than to the rising or falling edge, in the resistive case. Otherwise, the method of operation of the changeover switches (6) is identical to FIG. 1.

[0058] FIG. 3 shows the case for a charge integration amplifier (9) having a non-inverting input (26) and an inverting input (27). In this case, switching back and forth between the two inputs is carried out, as a result of which both phases are used and the effective gain is doubled.

[0059] FIG. 4 illustrates the case in which the capacitive matrix with a fixed capacitance (28) on the bit line (7) is connected to ground. This may be the parasitic bit line capacitance, for example. As a result, the voltage drop across this capacitance is switched to the charge integration amplifier (9), with the result that the clock generator (5) reacts to the positive and negative value range of the AC voltage signal (12).

[0060] FIG. 5 illustrates the same principle for a harmonic signal.

[0061] FIG. 6 shows the scheme for a mixed capacitive-resistive matrix. In this case, the clock generator (5) reacts with any phase to the AC voltage signal (12). The capacitive-resistive components (20) result in a phase shift of the charge and discharge that can be set in any desired manner. Therefore, the weight value cannot only be set by means of the absolute impedance value, but also by means of the complex and real parts of the impedance.

[0062] FIG. 7 shows a charge integration amplifier (9) having a current mirror topology. The current mirror has a low input impedance and mirrors the charge (10) to an integration capacitor (11).

[0063] FIG. 8 shows a charge integration amplifier (9) having a gate circuit which likewise has a low input impedance.

[0064] FIG. 9 shows the possibilities for representing an input value for the AC voltage signal (12). One possibility is to change the amplitude (25); furthermore, the number of periods can be changed, as already explained. In both cases, more or fewer charges are accumulated on the charge integration amplifier (9) over a period. Furthermore, the phase (24) can also be changed since the AC voltage signal (12) is always integrated only over certain periods of time, as illustrated. In the uppermost case, the complete rising edge is integrated. For the AC voltage signals (12) underneath, the integration period (represented as a dashed line), which is covered by the rising edge, becomes shorter and shorter. As a result, the accumulated charge likewise becomes lower.

[0065] FIG. 10 shows the same relationship as in FIG. 7 but only with a harmonic signal, wherein the integration period can now comprise the rising and falling edges. The lowermost curve represents a phase shift of 180° and comprises the falling edge, whereas the uppermost curve comprises the rising edge. The middle curve comprises the falling edge and the rising edge in equal parts, with the result that the integration value is zero in this case.

[0066] FIG. 11 shows the application of a plurality of AC voltage signals (12) at once to the word lines (3) with a different frequency. There is a separate charge integration amplifier (9) for each frequency band, as a result of which a plurality of vectors can be multiplied by the same weights. This case is particularly relevant in convolutional neural networks.

LIST OF REFERENCE SIGNS

[0067] 1 Capacitive synaptic component [0068] 2 Matrix arrangement [0069] 3 Word lines [0070] 4 Oscillator [0071] 5 Clock generator [0072] 6 Changeover switch [0073] 7 Bit lines [0074] 8 Ground [0075] 9 Charge integration amplifier [0076] 10 Charge [0077] 11 Integration capacitor [0078] 12 AC voltage signal [0079] 13 Positively defined capacitive synaptic component [0080] 14 Positively defined AC voltage signal [0081] 15 Negatively defined capacitive synaptic component [0082] 16 Negatively defined AC voltage signal [0083] 17 Positively defined resistive synaptic component [0084] 18 Negatively defined resistive synaptic component [0085] 19 Resistive synaptic component [0086] 20 Mixed capacitive-resistive synaptic component [0087] 21 Positively defined capacitive-resistive synaptic component [0088] 22 Negatively defined capacitive-resistive synaptic component [0089] 23 Number of periods [0090] 24 Phase shift [0091] 25 Amplitude change [0092] 26 Non-inverting input [0093] 27 Inverting input [0094] 28 Fixed capacitance