LC RESONANT CLOCK RESOURCE MINIMIZATION USING COMPENSATION CAPACITANCE

Abstract

VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.

Claims

1. A VLSI clock distribution network, comprising: a VLSI substrate; a clock distribution capacitor C.sub.clk fabricated on said VLSI substrate, said capacitor C.sub.clk having a lead connected to ground and an open lead; a decoupling capacitor C.sub.d fabricated on said VLSI substrate; a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor; a buffer fabricated on said VLSI substrate, said buffer driving said capacitor C.sub.clk and said inductor L at a clock frequency; and a compensation capacitor C.sub.c in parallel with said capacitor C.sub.clk; wherein said clock distribution network is resonant at said clock frequency, and wherein said clock frequency is determined as: $f_{\mathrm{clk}}^{\prime }=\frac{1}{2.Math.\pi }.Math.\sqrt{\frac{C_{\mathrm{clk}}+C_c+C_d}{L\left(C_{\mathrm{clk}}+C_d\right).Math.C_d}}.$

2. The VLSI clock distribution network according to claim 1, wherein said capacitor C.sub.clk is fabricated as a MOS capacitor.

3. The VLSI clock distribution network according to claim 1, wherein said capacitor C.sub.d is fabricated as a MOS capacitor.

4. The VLSI clock distribution network according to claim 1, wherein said capacitor C.sub.c is fabricated as a MOS capacitor.

5. The VLSI clock distribution network according to claim 1, wherein said inductor L is a spiral wound inductor.

6. The VLSI clock distribution network according to claim 1, wherein said inductor L has an inductance approximately equal to: $L=0.0002.Math..Math.l.Math.〚\ln .Math.\frac{2.Math.l}{w+t}+0.5+\frac{w+t}{3.Math.l}〛.Math..Math.\mathrm{nH}.$

7. A VLSI clock distribution network, comprising: a VLSI substrate; a clock distribution capacitor C.sub.clk fabricated on said VLSI substrate, said capacitor C.sub.clk having a lead connected to ground and an open lead; a decoupling capacitor C.sub.d fabricated on said VLSI substrate; a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor; a buffer fabricated on said VLSI substrate, said buffer driving said capacitor C.sub.clk and said inductor L at a clock frequency; and a compensation capacitor C.sub.c in parallel with said inductor L; wherein said clock distribution network is resonant at said clock frequency, and wherein said clock frequency is determined as: $f_{\mathrm{clk}}^{\prime }=\frac{1}{2.Math.\pi }.Math.\sqrt{\frac{C_{\mathrm{clk}}+C_d}{L.Math..Math.C_{\mathrm{clk}}.Math.C_d+C_c\left(C_{\mathrm{clk}}+C_d\right).Math.}}.$

8. The VLSI clock distribution network according to claim 7, wherein said capacitor C.sub.clk is fabricated as a MOS capacitor.

9. The VLSI clock distribution network according to claim 8, wherein said capacitor C.sub.d is fabricated as a MOS capacitor.

10. The VLSI clock distribution network according to claim 8, wherein said capacitor C.sub.c is fabricated as a MOS capacitor.

11. The VLSI clock distribution network according to claim 7, wherein said inductor L is a spiral wound inductor.

12. The VLSI clock distribution network according to claim 7, wherein said inductor L has an inductance approximately equal to: $L=0.0002.Math..Math.l.Math.〚\ln .Math.\frac{2.Math.l}{w+t}+0.5+\frac{w+t}{3.Math.l}〛.Math..Math.\mathrm{nH}.$

13. A VLSI clock distribution network, comprising: a VLSI substrate; a clock distribution capacitor C.sub.clk fabricated on said VLSI substrate, said capacitor C.sub.clk having a lead connected to ground and an open lead; a decoupling capacitor C.sub.d fabricated on said VLSI substrate; a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor; a buffer fabricated on said VLSI substrate, said buffer driving said capacitor C.sub.clk and said inductor L at a clock frequency; and a compensation capacitor C.sub.c in parallel with said capacitor C.sub.clk; wherein said clock distribution network is resonant at said clock frequency, and wherein said clock frequency is determined as: $f_{\mathrm{clk}}^{\prime }=\frac{1}{2.Math.\pi }.Math.\sqrt{\frac{C_{\mathrm{clk}}+C_c+C_d}{L\left(C_{\mathrm{clk}}+C_d\right).Math.C_d}}.$

14. A frequency scalable VLSI clock distribution network having a selectable resonant frequency, comprising: a VLSI substrate having a ground; an amplifier fabricated on said VLSI substrate; a clock distribution capacitor C.sub.clk fabricated on said VLSI substrate, said capacitor C.sub.clk having a lead connected to ground and an open lead; a decoupling capacitor C.sub.d fabricated on said VLSI substrate; a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor; a first compensation capacitor C.sub.c1 connected to ground; a first pass switch disposed between said first compensation capacitor C.sub.c1 and said lead; wherein said selectable resonant frequency changes when said first pass switch closes.

15. The frequency scalable VLSI clock distribution network according to claim 14, further including a second compensation capacitor C.sub.c2; a second pass switch; wherein said second pass switch and said capacitor C.sub.c2 are in series; wherein said series combination of said second pass switch and said capacitor C.sub.c2 are in parallel with said inductor; and wherein said selectable resonant frequency changes when said second pass switch closes.

16. The VLSI clock distribution network according to claim 15, wherein said capacitor C.sub.clk is fabricated as a MOS capacitor.

17. The VLSI clock distribution network according to claim 15, wherein said capacitor C.sub.d is fabricated as a MOS capacitor.

18. The VLSI clock distribution network according to claim 15, wherein said capacitor C.sub.c is fabricated as a MOS capacitor.

19. The VLSI clock distribution network according to claim 15, wherein said inductor L is a spiral wound inductor.

20. The VLSI clock distribution network according to claim 19, wherein said inductor L has an inductance approximately equal to: $L=0.0002.Math..Math.l.Math.〚\ln .Math.\frac{2.Math.l}{w+t}+0.5+\frac{w+t}{3.Math.l}〛.Math..Math.\mathrm{nH}.$

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The advantages and features of the present invention will become better understood with reference to the following detailed description and claims when taken in conjunction with the accompanying drawings, in which like elements are identified with like symbols, and in which:

[0032] FIG. 1 illustrates a prior art distributed LC resonant clock network 2;

[0033] FIG. 2 illustrates a spiral inductor 14 suitable for use in the present invention;

[0034] FIG. 3 illustrates a MOS capacitor 20 suitable for use in the present invention;

[0035] FIG. 4 is a schematic depiction of a distributed LC resonant clock network 50 that is in accord with the present invention;

[0036] FIG. 5 illustrates the Miller Effect in distributed LC resonant clock network 50;

[0037] FIG. 6 illustrates a distributed LC resonant clock network 100 that provides for selectable frequency scaling; and

[0038] FIG. 7 illustrates a VLSI device 200 including a VLSI chip that carries LC resonant clocks in accord with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0039] The presently disclosed subject matter now will be described more fully hereinafter with reference to the accompanying drawings in which one embodiment is shown. However, it should be understood that this invention may take different forms and thus the invention should not be construed as limited to the specific embodiment set forth herein.

[0040] All publications mentioned herein, specifically including “DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS,” a patent application filed on Jun. 22, 2011 under Attorney Docket No.:SC2011-196_PROV having inventors Dr. Matthew Guthaus and Xuchu Hu, are incorporated by reference for all purposes to the extent allowable by law.

[0041] In addition, in the figures like numbers refer to like elements throughout. Additionally, the terms “a” and “an” as used herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.

[0042] FIG. 7 illustrates a VLSI device 200 including a VLSI chip 204. The VLSI device 200 further includes a protective package 202 that spaces the VLSI chip 204 above internal contacts (shown as ball contacts) as well as external ball contacts 208. The VLSI chip 204 is suitable for carrying the LC resonant tanks that form the VLSI clocks.

[0043] FIG. 4 illustrates a distributed LC resonant clock network 50 that is in accord with the present invention and which illustrates two different topologies for insertion of a compensation capacitance C.sub.c 54. One position is in parallel with C.sub.clk 56 while the other in parallel with L 58. In addition, FIG. 4 includes a signal source 60 operating at f.sub.0, an amplifier 62, and a decoupling capacitor C.sub.d 66.

[0044] If C.sub.c 54 is in parallel with C.sub.clk 56 the size of the inductance L 58 can be reduced to obtain the same frequency f.sub.0 according to the formula:

[00008]$f_0=\frac{1}{2.Math.\pi .Math.\sqrt{\mathrm{LC}}}$

[0045] However, if C.sub.c 54 is in parallel with L 58 the often undesired Miller Effect can be used to good effect. Its application is shown in FIG. 5 which suggests that C.sub.c 54 can be divided as C.sub.c1 and C.sub.c2 in parallel with, and thus adding to C.sub.clk 56 and C.sub.d 66, respectively. This reduces the size of both L 58 and C.sub.d 66 to obtain the same operating frequency f.sub.0. In this manner the impact of a relatively small capacitor can be magnified to great advantage in distributed LC resonant clock network while still retaining the required very high frequency operation.

[0046] If both the parallel and series tank circuits are considered in the distributed LC resonant clock network 2 of FIG. 1 the resonant clock frequency becomes:

[00009]$f_{\mathrm{clk}}=\frac{1}{2.Math.\pi }.Math.\sqrt{\frac{C_{\mathrm{clk}}+C_d}{{\mathrm{LC}}_{\mathrm{clk}}.Math.C_d}}$

[0047] If as usual C.sub.d=10C.sub.clk this reduces to:

[00010]$f_{\mathrm{clk}}=\sqrt{\frac{11}{10}}\times \frac{1}{2.Math.\pi .Math.\sqrt{{\mathrm{LC}}_{\mathrm{clk}}}}$

[0048] The result is a 4.9% increase in resonant frequency due to the parasitic series LC.sub.d tank. That fact alone can be utilized to reduce the required inductor size of L 58 and save area at a fixed frequency f.sub.0.

[0049] Referring again to FIG. 4, if C.sub.c 54 is added in parallel with C.sub.clk 56 the resonant frequency will add C.sub.c 54 to C.sub.clk 54 to give a resonant frequency of:

[00011]$f_{\mathrm{clk}}^{\prime }=\frac{1}{2.Math.\pi }.Math.\sqrt{\frac{C_{\mathrm{clk}}+C_c+C_d}{L\left(C_{\mathrm{clk}}+C_d\right).Math.C_d}}$

[0050] The result is a decrease in resonant frequency given by:

[00012]$\frac{f_{\mathrm{clk}}^{\prime }}{f_{\mathrm{clk}}}=\sqrt{\frac{1+\frac{C_c}{C_{\mathrm{clk}}+C_d}}{1+\frac{C_c}{C_{\mathrm{clk}}}}}$

[0051] Now if C.sub.c 54 is added in parallel with L 58 the resonant frequency is:

[00013]$f_{\mathrm{clk}}^{\prime }=\frac{1}{2.Math.\pi }.Math.\sqrt{\frac{C_{\mathrm{clk}}+C_d}{L.Math..Math.C_{\mathrm{clk}}.Math.C_d+C_c\left(C_{\mathrm{clk}}+C_d\right).Math.}}$

[0052] The result is a decrease in resonant frequency found by.

[00014]$\frac{f_{\mathrm{clk}}^{\prime }}{f_{\mathrm{clk}}}=\sqrt{\frac{1}{1+\frac{C_c}{C_{\mathrm{clk}}}+\frac{C_c}{C_d}}}$

[0053] This result is even better as far as reducing the size of the inductor than putting C.sub.c in parallel with C.sub.clk 56.

[0054] A specific example may be helpful. If C.sub.c=0.5×C.sub.clk and C.sub.d=10×C.sub.clk, then the resulting clock f′.sub.clk given C.sub.c 54 is in parallel with C.sub.clk 56 in FIG. 4 is:

[00015]$f_{\mathrm{clk}}=\sqrt{\frac{11}{15}}÷2.Math.\pi .Math.\sqrt{{\mathrm{LC}}_{\mathrm{clk}}}$

[0055] Now, if Cc 54 is in parallel with L 58 then:

[00016]$f_{\mathrm{clk}}=\sqrt{\frac{11}{15.5}}÷2.Math.\pi .Math.\sqrt{{\mathrm{LC}}_{\mathrm{clk}}}$

[0056] This suggests that in the tank network of FIG. 4 that f′.sub.clk when C.sub.c 54 is in parallel with L 58 has a 3.8% lower frequency (in this example) than when in parallel with C.sub.clk 56. Again, this can be used to reduce the size of the inductor L 58.

[0057] Still referring to FIG. 4 while taking into consideration of the Miller Effect in FIG. 5, a significant difference in the topologies is the addition of C.sub.c2 to C.sub.d 66 when the compensation capacitor C.sub.c 54 is in parallel with L 58. In this case, the decoupling resonant frequency is:

[00017]$f_d=\frac{1}{2.Math.\pi .Math.\sqrt{L\left(\mathrm{Cd}+C_c\right)}}$

[0058] which is a factor

[00018]$\frac{1}{\sqrt{C_c}}$

lower than the case without C.sub.c 54. Consequently, it offers the advantage of sharing C.sub.c 54 directly from C.sub.d 66 for the same f.sub.d.

[0059] Based on the basic resonant frequency formula:

[00019]$f_0=\frac{1}{2.Math.\pi .Math.\sqrt{\mathrm{LC}}}$

[0060] L 58 can be reduced by adding C.sub.c 54 and considering the Miller Approximation to get C.sub.c1 and C.sub.c2. If C.sub.c1+C.sub.clk=α.sub.1xC.sub.clk, where α.sub.1 is the ratio or capacitive effect between C.sub.c1+C.sub.clk and C.sub.clk, then L 58 can be reduced as L×α.sub.1 for the same resonant frequency. The result is:

[00020]$L^{\prime }=\frac{L}{{\alpha }_1}=\frac{L}{{\left(\frac{f_{\mathrm{clk}}}{f_{\mathrm{clk}}^{\prime }}\right)}^2}$

[0061] α1 therefore represents the capacitive effect between C.sub.c1, while L′ and f′.sub.clk are the inductance and resonant frequency after adding the effect of C.sub.c 54. A higher α1 means a better capacitive effect and a lower resonant frequency f′.sub.clk.

[0062] Experimental results confirm the foregoing. Smaller inductors L 58 can be used to produce a fixed resonant frequency f.sub.0 by incorporating a compensation capacitance C.sub.c 54 in parallel with C.sub.clk 56 with L 58, or with both. In addition, a fixed inductor L 58 and fixed C.sub.clk 56 can be used to produce a scaled frequency by incorporating C.sub.c 54 in parallel with C.sub.clk 56, with L 58, or with both. Significant on-chip area can be saved by incorporating C.sub.c 54. All of these results are highly beneficial and useful when incorporating distributed LC resonant clocks.

[0063] Incorporating compensation capacitors C.sub.c 54 also enables dynamic frequency scaling. This enables a new, useful and unobvious enhancement to distributed LC resonant clocks.

[0064] Reference FIG. 6 for a distributed LC resonant clock network 100 suitable for selectable frequency scaling. The distributed LC resonant clock network 100 includes a signal source 102 that operates at f.sub.0, an amplifier 104, a first compensation capacitor C.sub.c 106, a second compensation capacitor C.sub.c 108, a capacitor C.sub.clk 110, an inductor L 112 and a decoupling capacitor C.sub.d 114. In addition, the distributed LC resonant clock network 100 includes a first pass switch 120 and a second pass switch 122 for selectively connecting the first and second compensation capacitors C.sub.c 106, 108, respectively into the network 100.

[0065] The distributed LC resonant clock network 100 enables multiple selectable (i.e. scalable) resonant frequencies selected by enabling or disabling the first pass switch 120 and the second pass switch 122. The selectable (scalable) resonant frequencies are selected in accord with the frequencies provide above. Both compensation capacitors C.sub.c 106, 108 can be disabled, resulting in the resonant frequency provided above without the use of compensation capacitances. If only compensation capacitor Cc 106 is enabled by turning on pass switch 120 the result is the resonant frequency provided above with a compensation capacitor C.sub.c 106 in parallel with C.sub.clk 110. Compensation capacitor C.sub.c 108 could be enabled by turning on pass switch 122, resulting in the resonant frequency provided above with compensation capacitor C.sub.c 108 in parallel with L. Both compensation capacitors C.sub.c 106, 108 could be enable by turning on pass switches 120, 122, resulting in the resonant frequency provided above with compensation capacitors C.sub.c 106, 108 in parallel with both C.sub.clk and L. Four different selectable resonant frequencies can be selected by selectively turning on pass transistors 120 and 122.

[0066] It is to be understood that while the figures and the above description illustrates the present invention, they are exemplary only. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. Others who are skilled in the applicable arts will recognize numerous modifications and adaptations of the illustrated embodiments that remain within the principles of the present invention. Therefore, the present invention is to be limited only by the appended claims.