MULTI-VOLTAGE BOOTSTRAPPING DRIVERS

Abstract

A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.

Claims

1. A bootstrapping gate driver for a high side FET having a drain terminal connected to a supply voltage, a source terminal connected to an output, and a gate terminal, the bootstrapping gate driver comprising: an input for receiving a control signal; and a plurality of bootstrap capacitors electrically connected in parallel between the voltage source and ground when the control signal corresponds to a charging phase, thereby charging the capacitors, the plurality of bootstrap capacitors being electrically connected in series between the gate and the source of the high side FET when the control signal corresponds to a driving stage; whereby the voltage between the gate and the drain of the high side FET is equal to or greater than the supply voltage when the control signal corresponds to the driving stage.

2. The bootstrapping gate driver of claim 1, further comprising a resistor electrically connected between the voltage source and the gate of the high side FET to decrease static current consumption.

3. The bootstrapping gate driver of claim 1, further comprising a low side FET for turning off the high side FET, the low side FET having a drain terminal connected to the source of the high side FET and the output, a gate terminal connected to the input, and a source terminal connected to ground.

4. The bootstrapping gate driver of claim 2, comprising an initial stage and a secondary stage, wherein the initial stage includes a first one of said plurality of bootstrap capacitors and the resistor, and the secondary stage includes a second one of said plurality of bootstrap capacitors and a FET.

5. The bootstrapping gate driver of claim 4, wherein the bootstrapping gate driver is cascaded and comprises a second secondary stage comprising circuitry substantially similar to the secondary stage, including a third one of said plurality of bootstrap capacitors.

6. The bootstrapping gate driver of claim 5, wherein the second secondary stage of the cascaded bootstrapping driver comprises a FET that is smaller than the high side FET, and the secondary stage comprises a FET that is smaller than the FET of the second secondary stage, and wherein the bootstrap capacitor of the initial stage is smaller than the bootstrap capacitors of the secondary stage and the second secondary stage.

7. The bootstrapping gate driver of claim 6, wherein the FETs of the bootstrapping gate driver are gallium nitride (GaN) FETs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify correspondingly throughout and wherein:

[0027] FIG. 1 is a schematic of a conventional bootstrapping gate driver circuit.

[0028] FIG. 2 is a schematic of a conventional cascaded bootstrapping gate driver circuit.

[0029] FIG. 3 is a schematic of a multi-voltage bootstrapping gate driver circuit in accordance with a first embodiment of the present invention.

[0030] FIG. 4 is a schematic of a cascaded multi-voltage bootstrapping gate driver circuit in accordance with a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.

[0032] FIG. 3 illustrates a bootstrapping gate driver 390 according to a first embodiment of the present invention. The system 300 includes the bootstrapping gate driver 390, a high side (pull-up) FET 394, a low side (turn-off) FET 392, and an output to be connected to a load (not shown). Turn-off FET 392 and high side FET 394 (and all FETs in the circuits described below) are preferably enhancement mode gallium nitride (GaN) FETs, which are monolithically integrated with cascaded bootstrapping gate driver 390 onto a single semiconductor die. Because GaN FETs are able to carry large currents, support high voltages, and switch more quickly than conventional FETs, gate driver circuit 300 provides quicker turn-on and turn-off times than a similar circuit implementing other transistors, such as MOSFETs.

[0033] Bootstrapping gate driver 390 is coupled to a gate terminal of high side FET 394. The drain terminal of high side FET 394 is coupled to a supply voltage source 310 which provides a supply voltage V.sub.dd, and the source terminal of high side FET 394 is coupled to load 396 at output node 398. Bootstrapping gate driver 390 receives a control signal via the input and drives high side FET 394 based on the input (logic low or logic high). A logic high input is indicative that high side FET 394 is to be turned off, and a logic low input is indicative that high side FET 394 is to be turned on.

[0034] In a driving mode, when the input is a logic low, high side FET 394 acts as a closed switch, connecting the output (and an associated load, not shown) to supply voltage V.sub.dd based on the output from bootstrapping gate driver 390. The drain terminal of turn-off FET 392 is coupled to the output, and the source terminal of turn-off FET 392 is coupled to ground. The gate terminal of turn-off FET 392 receives a control signal on the input. In response to the input being logic high, turn-off FET 392 acts as a closed switch, connecting the output to ground, speeding a decrease in a voltage on the output from approximately Vdd to ground.

[0035] Bootstrapping gate driver 390 includes an initial bootstrapping stage 350 and a secondary bootstrapping stage 385. The initial bootstrapping stage 350 includes FETs 320 and 335, a resistor 330, and a capacitor 345. The secondary bootstrapping stage 385 includes FETs 355, 365, and 375 and capacitor 380. FETs 320, 335, 355, 365, and 375 are preferably enhancement mode GaN FET semiconductor devices, which are monolithically integrated onto a single semiconductor die with the other components of system 300. As described previously herein with reference to turn-off FET 392 and high side FET 394, GaN FETs switch more quickly than conventional FETs and allow bootstrapping gate driver 390 to turn high side FET 394 on and off more quickly than a similar system implementing other transistors, such as MOSFETs.

[0036] In initial bootstrapping stage 350, the gate terminal of FET 320 receives the input control signal, and the source terminal of FET 320 is coupled to ground. The drain terminal of FET 320 is coupled to resistor 330 at node 325. Resistor 330 is further coupled to the source terminal of FET 335 at node 340. The gate terminal and the drain terminal of FET 335 are coupled to supply voltage V.sub.dd, configuring FET 335 as a diode. Capacitor 345 is coupled to node 340 and to node 360 in the secondary bootstrapping stage 385.

[0037] The secondary bootstrapping stage 385 is similar to initial bootstrapping stage 350 but substitutes FET 365 for resistor 330. FET 365 is smaller than high side FET 394, and the gate terminal of FET 365 is driven by initial bootstrapping stage 350. The gate terminal of FET 355 receives the input control signal, and the source terminal of FET 355 is coupled to ground. The drain terminal of FET 355 is coupled to the source terminal of FET 365 at node 360. The gate terminal of FET 365 is coupled to node 325 in initial bootstrapping stage 350, and the drain terminal of FET 365 is coupled to the source terminal of FET 375 at node 370. The gate terminal and the drain terminal of FET 375 are coupled to supply voltage source 310, configuring FET 375 as a diode. Capacitor 380 is coupled to output node 398. The gate terminal of high side FET 394 is coupled to node 360.

[0038] In response to the input being logic high, FETs 320, 355 and 392 act as closed switches. FET 320, acting as a closed switch, connects node 325 to ground, decreasing the voltage on node 325. FET 355, acting as a closed switch, connects node 360 to ground, decreasing the voltage on node 360. The decreasing voltage on node 325 at the gate terminal of FET 365 and on node 360 at the source terminal of FET 365 turns off FET 365. Turn-off FET 392, acting as a closed switch, connects the output to ground, decreasing the voltage on the output. The decreasing voltage on node 325 at the gate terminal of high side FET 394 and on the output at the source terminal of high side FET 394 turns off high side FET 394, disconnecting the output from the supply voltage source 310. Charge is stored in capacitor 345 from the supply voltage V.sub.dd through diode-connected FET 335 and FET 355. Similarly, charge is stored in capacitor 380 from the supply voltage V.sub.dd through diode-connected FET 375 and turn-off FET 392. The voltages across capacitors 345 and 380 are increased to approximately V.sub.dd−V.sub.Th, due to the threshold voltage drop across the diode-connected FET 335 or 375, respectively. Static current is drawn only through resistor 330 and FETs 335 and 320.

[0039] In response to the input being logic low, FETs 320, 355, and 392 act as open switches. FET 392, acting as an open switch, disconnects the output from ground, allowing the voltage on the output to increase. FET 320, acting as an open switch, disconnects node 325 from ground. The initial voltage on node 340 is approximately equal to V.sub.dd−V.sub.Th, due to the threshold voltage drop across FET 335, and increases the voltage on node 325 through resistor 330. As the voltage on node 325 increases above V.sub.Th, FETs 365 and 394 turn on. FET 355, acting as an open switch, disconnects node 360 from ground, allowing the voltage on node 360 to increase as FET 365 turns on and current flows from supply voltage V.sub.dd through FETs 375 and 365 to node 360. High side FET 394 acts as a closed switch and connects the output to supply voltage source V.sub.dd. As the voltage on the output increases, charge stored in capacitor 380 increases the voltage on node 370 proportionally, such that the voltage on node 370 is approximately equal to the voltage on output plus V.sub.dd−V.sub.Th. Because FET 365 is on, the voltage on node 360 is substantially equal to the voltage on node 370 and increases proportional to the increase in voltage on the output. As the voltage on node 360 increases, energy stored in capacitor 345 increases the voltage on node 340 proportionally, such that the voltage on node 340 is approximately equal to the voltage stored on capacitor 380 plus the voltage stored on capacitor 345, which are connected in series. The increase in voltage on node 340 increases the voltage on node 325 through resistor 330. The increase in voltage on node 325, which is electrically connected to the gate terminal of FET 365 and to the gate terminal of high side FET 394 keeps those FETs on. Keeping FET 365 turned on keeps node 370 and node 360 electrically connected together, such that the V.sub.GS of high side FET 394 is substantially equal to the voltage across capacitor 380 added to the voltage across capacitor 345, and high side FET 394 remains turned on. No static current is drawn.

[0040] In response to the input being logic low and FET 365 acting as a closed switch that electrically connects node 370 and node 360, the charge on capacitor 380 and the charge on capacitor 345 is redistributed between capacitor 380, 345 and the gate-to-source capacitance of high side FET 394. The resulting V.sub.GS of high side FET 394 is equal to the voltage across capacitor 380 plus the voltage across capacitor 340

[0041] By using a bootstrapping driver with multiple bootstrap capacitors, the total capacitance required in the bootstrapping driver circuit of FIG. 1 is advantageously reduced and the gate-to-source voltage of high side FET 394, which is normally equal to or less than V.sub.d, is equal to or even higher than V.sub.dd, as explained below.

[0042] For a logic high input (i.e., the charging phase of the bootstrapping driver), the output, node 360 and node 325 are at ground since FETs 320, 355 and 392 are on. Both bootstrap capacitors 345 and 380 are charged to about V.sub.dd through FETs 375 & 392 and FETs 335 & 355, respectively, if the threshold voltages, V.sub.TH of FETs 335 and 375 are approximately zero.

[0043] For a logic low input driving phase of the bootstrapping driver), node 325 is pulled up to node 340 via resistor 330 and hence, FETs 365 and 394 start to turn on. The gate-to-source voltage on high side FET 394 will be charged by the voltage across bootstrap capacitor 380 added to the voltage across bootstrap capacitor 345. The gate-to-source voltage on high side FET 394 can be derived as:

V.sub.GS_394=3V.sub.dd.Math.C.sub.380.Math.C.sub.345/[(C.sub.380+C.sub.345)(C.sub.GS_394+C.sub.345)]

[0044] The total required bootstrap capacitance, C.sub.T, is equal to C.sub.380+C.sub.345.

[0045] If the gate-to-source voltage on high side FET 394 (V.sub.GS_394) is desired to be equal to V.sub.dd with bootstrap capacitors having the same capacitance (C.sub.380=C.sub.345=C.sub.Bootstrap), then C.sub.Bootstrap will be equal to twice the gate-to-source capacitance of high side FET 394 (C.sub.GS_394) and the total bootstrap capacitance C.sub.T will be equal to 4.Math.C.sub.GS_394, which is 55% less than the total required capacitance (9.Math.C.sub.GS_394 to achieve V.sub.GS_394=0.9.Math.V.sub.dd) in the bootstrap driver circuit of FIG. 1. In addition, the resulting gate-to-source capacitance of high side FET 394 V.sub.GS_394 (=V.sub.dd) is even higher than the one in FIG. 1 (V.sub.GS_394=0.9.Math.V.sub.dd), further improving pull-up speed.

[0046] In general, N integer number of bootstrap capacitors can be used. Then V.sub.GS_294=N.Math.V.sub.dd.Math.C.sub.Bootstrap/(C.sub.Bootstrap+N.Math.C.sub.GS_394) and C.sub.T=N.Math.C.sub.Bootstrap can be derived.

[0047] Nevertheless, to achieve V.sub.GS_394=V.sub.dd with minimum total required capacitance C.sub.T, N=2 is optimal. If V.sub.GS_394=1.5.Math.V.sub.dd is desired, the optimal N will be equal to 3 with a minimum C.sub.T of 9.Math.C.sub.GS_394.

[0048] FIG. 4 illustrates a system 400 according to a second embodiment of the present invention, which includes cascaded bootstrapping gate driver 490, a high side FET 494, a low side (turn-off) FET 492, and an output to be connected to a load (not shown).

[0049] To achieve low power dissipation, in the second embodiment of the invention, the cascaded bootstrapping technique of FIG. 2 is combined into the multi-voltage bootstrapping drivers of FIG. 3 as shown, where like reference numbers in the 400′s of FIG. 4 represent corresponding elements in the 300's of FIG. 3, with A and B suffixes added to represent the elements inside two bootstrapping stages in the multi-voltage bootstrapping stage. More specifically, since the combined capacitance for FET 365 and high side FET 394 in the gate driver of FIG. 3 can be quite large, a very small resistor 330 is required to pull the voltage at node 325 up to the voltage at node 340 in the circuit and hence, high DC power dissipation results when the input is logic high.

[0050] In the cascaded bootstrapping gate driver of FIG. 4, resistor 330 of FIG. 3 is replaced with a FET 465B to address the above-described logic high input issue. FET 465B has a much smaller size than high side FET 494 and FET 465A. (In an alternative embodiment of the circuit of FIG. 4, the gate of FET 465A can be connected to the gate of FET 465B). FET 465B of bootstrapping stage 485B is driven by the circuitry of the preceding stage 450. Since the size of FET 465B is much less that the size of high side FET 494 and FET 465A, bootstrap capacitor 445 can be much smaller than bootstrap capacitors 480A and 480B. Resistor 430 can thus be much larger than resistor 330 to reduce current consumption with a far lower penalty on the turn-on time of FET 465B due to the smaller size of FET 465B. Additional cascaded stages can be used, in the manner described in U.S. Pat. No. 10,790,811, which is incorporated by reference. In other words, the same concept of using multiple-bootstrap capacitors can also be applied to replace a single bootstrap capacitor in each cascaded stage, such that the total capacitance requirements in the cascaded stages can also be reduced.

[0051] In summary, the multi-voltage bootstrapping driver of the present invention has the following features and advantages over the prior art: [0052] For a conventional bootstrapping driver, the gate-to-source voltage of the pull-up FET can only be equal to or less than the supply voltage. It also requires large bootstrap capacitor. [0053] In the bootstrapping driver of the present invention, the gate-to-source voltage of the pull-up FET is set equal to or higher than the supply voltage. [0054] In accordance with the present invention, multiple bootstrap capacitors are charged in parallel and connected in series to achieve multiple voltages applied to the gate and source terminals of the pull-up driving FET for logic high output. [0055] To achieve a gate-to-source voltage equal to the supply voltage, the total required capacitance is 55% less than the conventional bootstrapping driver that can only achieve 90% of the supply voltage on the gate-to-source voltage. Therefore, the present invention reduces the overall die area significantly. [0056] The present invention can be combined with cascaded bootstrapping technique disclosed and claimed in U.S. Pat. No. 10,790,811 to achieve low power consumption.

[0057] The proposed technique can be further combined with the active bootstrapping circuitry of co-pending U.S. application Ser. No. 18/062,660 (in addition to the combination of the cascaded bootstrapping circuitry) to further maximize the voltages stored on the bootstrap capacitors to improve the robustness of the overall bootstrapping driver for different process, voltage and temperature variations.

[0058] The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.