NON-OVERLAPPED-EXTENSION-IMPLANTATION NONVOLATILE MEMORY DEVICE CAPABLE OF BEING TREATED WITH ANTI-FUSE OPERATION

Abstract

The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation. Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer. The most important is that, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.

Claims

1. A non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation, comprising: a silicon substrate; a gate oxide layer, being formed on the silicon substrate; a gate layer, being formed on the gate oxide layer; a first diffusion region, being formed in the silicon substrate; a lightly doped drain (LDD) region, being formed in the silicon substrate and adjacent to the first diffusion region; wherein the gate oxide layer has an overlapped oxide segment between the gate layer and the LDD region; a second diffusion region, being formed in the silicon substrate opposite to the first diffusion region; and a non-lightly doped drain (non-LDD) region, being formed in the silicon substrate and adjacent to the second diffusion region; moreover, the non-LDD region oppositely locating below the gate layer; wherein a high electric filed would be induced in the overlapped oxide segment by forming a voltage difference between the gate layer and the silicon substrate; therefore, the high electric filed would make the overlapped oxide segment occur oxide breakdown, so as to carry out the anti-fuse operation on the NOI nonvolatile memory device.

2. The NOI nonvolatile memory device of claim 1, wherein a first ions implanted in the first diffusion region is different from a second ions implanted in the second diffusion region on polarity.

3. The NOI nonvolatile memory device of claim 1, wherein a plurality of first ions implanted in the first diffusion region is different from a plurality of second ions implanted in the second diffusion region on ion concentration.

4. The NOI nonvolatile memory device of claim 1, further comprising a metal compound layer, formed on the gate layer, the first diffusion layer and a second diffusion layer.

5. The NOI nonvolatile memory device of claim 1, wherein each of two sidewalls of the gate layer are formed with a sidewall spacer.

6. The NOI nonvolatile memory device of claim 4, wherein the manufacturing material of the metal compound layer is selected from the group consisting of: metal silicide, metal germanide and combination of the aforesaid two materials.

7. A non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation, comprising: a silicon substrate; a gate oxide layer, being formed on the silicon substrate; a gate layer, being formed on the gate oxide layer; a diffusion region, being formed in the silicon substrate; a non-lightly doped drain (non-LDD) region, being formed in the silicon substrate and adjacent to the diffusion region; moreover, the non-LDD region oppositely locating below the gate layer; and a shallow trench isolation (STI) oxide region, being formed in the silicon substrate opposite to the diffusion region; wherein the gate oxide layer has an overlapped oxide segment locating between the gate layer and the STI oxide region; wherein a high electric filed would be induced in the overlapped oxide segment by forming a voltage difference between the gate layer and the silicon substrate; therefore, the high electric filed would make the overlapped oxide segment occur oxide breakdown, so as to carry out the anti-fuse operation on the NOI nonvolatile memory device.

8. The NOI nonvolatile memory device of claim 7, wherein the diffusion region is provided with a plurality of ions having polarity therein through ion implantation process.

9. The NOI nonvolatile memory device of claim 7, further comprising a metal compound layer, formed on the gate layer, the first diffusion layer and a second diffusion layer.

10. The NOI nonvolatile memory device of claim 7, wherein each of two sidewalls of the gate layer are formed with a sidewall spacer.

11. The NOI nonvolatile memory device of claim 9, wherein the manufacturing material of the metal compound layer is selected from the group consisting of: metal silicide, metal germanide and combination of the aforesaid two materials.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention as well as a preferred mode of use and advantages thereof will be best understood by referring to the following detailed description of an illustrative embodiment in conjunction with the accompanying drawings, wherein:

[0027] FIG. 1 shows a schematic cross-sectional view of a conventional anti-fuse memory device;

[0028] FIG. 2 shows a schematic cross-sectional view of a conventional MOSFET device;

[0029] FIG. 3 shows a schematic cross-sectional diagram of a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation according to the present invention;

[0030] FIG. 4 shows a schematic diagram of an anti-fuse operation applied to the NOI nonvolatile memory device;

[0031] FIG. 5 shows a schematic diagram of a read operation applied to the NOI nonvolatile memory device;

[0032] FIG. 6 shows a schematic cross-sectional diagram of a second embodiment for the NOI nonvolatile memory device capable of being treated with anti-fuse operation according to the present invention;

[0033] FIG. 7 shows a schematic diagram of an anti-fuse operation applied to the second embodiment of the NOI nonvolatile memory device; and

[0034] FIG. 8 shows a schematic diagram of a read operation applied to the second embodiment of the NOI nonvolatile memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] To more clearly describe a non-overlapped-extension-implantation (NOI) nonvolatile memory device according to the present invention, embodiments of the present invention will be described in detail with reference to the attached drawings hereinafter.

[0036] For facilitating the engineers skilled in nonvolatile memory fields be able to easily understand the NOI nonvolatile memory provided by the present invention, a standard MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device must be introduced in advance. Please refer to FIG. 2, there is shown a schematic cross-sectional view of a conventional MOSFET device. As shown in FIG. 2, the conventional MOSFET device 1′ consists of: a substrate 10′, a gate oxide layer 11′, a gate layer 12′, a source region 13′, a drain region 14′, and two sidewall spacers 15′; wherein an active region 101′ is further formed in the substrate 10′.

[0037] It is well known that a drain current and a source current of the MOSFET device 1′ can be read out by treating the MOSFET device 1′ with a forward-read operation and a reverse-read operation. Herein, the apply voltage conditions for the forward-read operation and the reverse-read operation are listed in following Table (1).

TABLE-US-00001 TABLE (1) forward-read operation reverse-read operation Gate Voltage V.sub.G′ ≧ V.sub.th (threshold V.sub.G′ ≧ V.sub.th (threshold voltage) (V.sub.G′) voltage) Substrate Voltage V.sub.B′ = GND V.sub.B′ = GND (V.sub.B′) Drain Voltage V.sub.D′ = constant voltage V.sub.D′ = GND (V.sub.D′) Source Voltage V.sub.S′ = GND V.sub.S′ = constant voltage (V.sub.S′)

[0038] In follows, it will detailedly introduce the NOI nonvolatile memory device provided by the present invention. Please refer to FIG. 3, where a schematic cross-sectional diagram of the NOI nonvolatile memory device is shown. As shown in FIG. 3, the NOI nonvolatile memory device 1 is consisted of: a silicon substrate 10, a gate oxide layer 11 formed on the silicon substrate 10, a gate layer 12 formed on the gate oxide layer 11, a first diffusion region 13a, a lightly doped drain (LDD) region 131b, a second diffusion region 13b, and a non-lightly doped drain (non-LDD) region 131a. In which, an active region 101 is formed in the silicon substrate 10, and the first diffusion region 13a and the second diffusion region are also formed in the silicon substrate 10 opposite to each other. The same to the MOSFET device, each of the first diffusion region 13a and the second diffusion region 13b are a high-concentration ion implantation region, i.e., the Drain region and the Source region.

[0039] In addition, the LDD region 131b is formed in the silicon substrate and adjacent to the first diffusion region 13a, wherein the gate oxide layer 11 has an overlapped oxide segment 111 between the gate layer 12 and the LDD region 131b. Differing from the conventional MOSFET device, this NOI nonvolatile memory device 1 has a non-lightly doped drain (non-LDD) region 131a formed in the silicon substrate 10. The non-LDD region 131a is a non-overlapped-extension-implantation region and adjacent to the second diffusion region 13b, moreover, the non-LDD region 131a is also oppositely locates below the gate layer 12.

[0040] The same to conventional MOSFET device, there are two sidewall spacers 15 respectively formed on the two sidewalls of the gate layer 12. Moreover, a metal compound layer (not shown) is formed on the gate layer 12, the first diffusion region 13a, and the second diffusion region 13b. The manufacturing material of the said metal compound can be metal silicide, metal germanide and combination of the aforesaid two materials.

[0041] Particularly, this NOI nonvolatile memory device 1 can be written with at least one bit through an anti-fuse operation. Moreover, the bit stored in the NOI nonvolatile memory device 1 can be read out through a read operation. Herein, the apply voltage conditions for the anti-fuse operation and the read operation are listed in following Table (2).

TABLE-US-00002 TABLE (2) anti-fuse operation read operation Gate Voltage V.sub.G = V.sub.pp V.sub.G = V.sub.DD (V.sub.G) (programming voltage) (constant voltage) Substrate Voltage V.sub.B = GND V.sub.B = GND (V.sub.B) Drain Voltage V.sub.D = floating V.sub.D = GND (V.sub.D) Source Voltage V.sub.S = GND V.sub.S = floating (V.sub.S)

[0042] Please refer to FIG. 4, which illustrates a schematic diagram of the anti-fuse operation applied to the NOI nonvolatile memory device is illustrated. As FIG. 4 shows, when the NOI nonvolatile memory device 1 is treated with the anti-fuse operation, a high electric filed would be induced in the overlapped oxide segment 111 because a voltage difference is applied between the gate layer 12 and the silicon substrate 10; therefore, the high electric filed would make the overlapped oxide segment 111 occur oxide breakdown, so as to carry out the anti-fuse operation on the NOI nonvolatile memory device 1.

[0043] Herein, it needs to further explain that, because a loose-coupling fringing capacitor is physically formed between the first diffusion region 13a and the gate layer 12, the high electric filed would be prevented from being coupled into a non-overlapped oxide segment of the gate oxide layer 11 locating over the non-LDD region 131a. Therefore, non-overlapped oxide segment of the gate oxide layer 11 is protected from occurring oxide breakdown when the NOI nonvolatile memory device 1 is treated with the anti-fuse operation.

[0044] After the NOI non-volatile memory device 1 is written with one bit, the programmed bit can further be read out through the read operation. Please refer to FIG. 5, which shows a schematic diagram of the read operation applied to the NOI nonvolatile memory device 1. As shown in FIG. 5, a read current of the NOI nonvolatile memory device 1 can be read out after the read operation is applied to the NOI nonvolatile memory device 1. Furthermore, the bit stored in the NOI nonvolatile memory device 1 can be recognized as bit “0” or bit “1” by comparing the read current with a reference current.

[0045] Therefore, through above descriptions, the non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation proposed by the present invention has been introduced completely and clearly; in summary, the present invention includes the advantages of:

[0046] (1) Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer.

[0047] (2) Moreover, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.

[0048] Continuously, a second embodiment for the NOI nonvolatile memory device will be introduced in following paragraphs. Please refer to FIG. 6, where a schematic cross-sectional diagram of the second embodiment for NOI nonvolatile memory device is shown. As shown in FIG. 6, the second embodiment of the NOI nonvolatile memory device 1 is consisted of: a silicon substrate 10, a gate oxide layer 11 formed on the silicon substrate 10, a gate layer 12 formed on the gate oxide layer 11, a diffusion region 13, a non-lightly doped drain (non-LDD) region 131, and a shallow trench isolation (STI) oxide region 14. In which, an active region 101 is formed in the silicon substrate 10, and the diffusion region 13 and the STI oxide region 14 are formed in the silicon substrate 10 opposite to each other. The same to the MOSFET device, the diffusion region 13 is a high-concentration ion implantation region, i.e., the Drain region or the Source region.

[0049] As shown in FIG. 6, the gate oxide layer 11 has an overlapped oxide segment 111 locating between the gate layer 12 and the STI oxide region 14. On the other hand, it is able to say that, the STI oxide region 14 has an overlapped portion oppositely locating below the gate layer 12. Differing from the conventional MOSFET device, this NOI nonvolatile memory device 1 has a non-lightly doped drain (non-LDD) region 131 formed in the silicon substrate 10; moreover, the non-LDD region 131 is adjacent to the diffusion region 13 and oppositely locates below the gate layer 12. The same to conventional MOSFET device, there are two sidewall spacers 15 respectively formed on the two sidewalls of the gate layer 12.

[0050] The same to above-described embodiment, the second embodiment of the NOI nonvolatile memory device 1 can be written with at least one bit through an anti-fuse operation. Moreover, the bit stored in the NOI nonvolatile memory device 1 can be read out through a read operation. Herein, the apply voltage conditions for the anti-fuse operation and the read operation are listed in following Table (3).

TABLE-US-00003 TABLE (3) anti-fuse operation read operation Gate Voltage V.sub.G = V.sub.pp V.sub.G = V.sub.DD (V.sub.G) (programming voltage) (constant voltage) Substrate Voltage V.sub.B = GND V.sub.B = GND (V.sub.B) Drain Voltage V.sub.D = GND V.sub.D = V.sub.read (V.sub.D) (read voltage) Source Voltage V.sub.S = floating V.sub.S = floating (V.sub.S)

[0051] With reference to FIG. 7, where a schematic diagram of the anti-fuse operation applied to the second embodiment of the NOI nonvolatile memory device is illustrated. As FIG. 7 shows, when the NOI nonvolatile memory device 1 is treated with the anti-fuse operation, a high electric filed would be induced in the overlapped oxide segment 111 because a voltage difference is applied between the gate layer 12 and the silicon substrate 10; therefore, the high electric filed would make the overlapped oxide segment 111 occur oxide breakdown, so as to carry out the anti-fuse operation on the NOI nonvolatile memory device 1.

[0052] Herein, it needs to further explain that, because a loose-coupling fringing capacitor is physically formed between the diffusion region 13 and the gate layer 12, the high electric filed would be prevented from being coupled into a non-overlapped oxide segment of the gate oxide layer 11 locating over the non-LDD region 131. Therefore, non-overlapped oxide segment of the gate oxide layer 11 is protected from occurring oxide breakdown when the NOI nonvolatile memory device 1 is treated with the anti-fuse operation.

[0053] After the NOI non-volatile is written with one bit, the programmed bit can further be read out through the read operation. Please refer to FIG. 8, which shows a schematic diagram of the read operation applied to the NOI nonvolatile memory device. As shown in FIG. 8, a read current of the NOI nonvolatile memory device 1 can be read out after the read operation is applied to the NOI nonvolatile memory device 1. Furthermore, the bit stored in the NOI nonvolatile memory device 1 can be recognized as bit “0” or bit “1” by comparing the read current with a reference current.

[0054] The above description is made on embodiments of the present invention. However, the embodiments are not intended to limit scope of the present invention, and all equivalent implementations or alterations within the spirit of the present invention still fall within the scope of the present invention.