Optical electronics device

Abstract

An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.

Claims

1. A device comprising: a semiconductor layer; a transparent layer over the semiconductor layer; a patterned metal layer on a side of the transparent layer, the patterned metal layer having a window aperture; a device layer; and a dielectric layer between the device layer and the semiconductor layer, a cavity extending from the semiconductor layer and through the dielectric layer.

2. The device of claim 1, wherein the dielectric layer is a first dielectric layer, the device further comprising a second dielectric layer between the semiconductor layer and the transparent layer.

3. The device of claim 2, further comprising an anti-reflective layer between the patterned metal layer and the second dielectric layer.

4. The device of claim 3, wherein the anti-reflective layer is a first anti-reflective layer, the side of the transparent layer is a first side of the transparent layer, and the device further comprising a second anti-reflective layer on a second side of the transparent layer opposite the first side.

5. The device of claim 2, wherein the second dielectric layer has vertical sidewalls.

6. The device of claim 1, further comprising a mircroelectromecanical system (MEMS) device on the device layer in the cavity, wherein the cavity forms an aperture over the MEMS device.

7. The device of claim 6, wherein sidewalls of the cavity slope inwardly through the semiconductor layer toward the aperture.

8. The device of claim 1, wherein the dielectric layer is silicon dioxide.

9. The device of claim 1, further comprising a metal layer on sidewalls of the cavity.

10. The device of claim 1, wherein further comprising a sealing layer between the device layer and the dielectric layer.

11. A device comprising: a semiconductor layer; a transparent layer over the semiconductor layer; a patterned metal layer on a side of the transparent layer, the patterned metal layer having a window aperture; a dielectric layer between the transparent layer and the semiconductor layer, a cavity extending from the semiconductor layer and through the dielectric layer; and a device layer below the semiconductor layer, a microelectromechanical system (MEMS) device on the device layer in the cavity.

12. The device of claim 11, wherein the dielectric layer is a first dielectric layer, the device further comprising a second dielectric layer between the semiconductor layer and the device layer.

13. The device of claim 11, further comprising an anti-reflective layer between the patterned metal layer and the dielectric layer.

14. The device of claim 13, wherein the anti-reflective layer is a first anti-reflective layer, the first anti-reflective layer is on a first the side of the transparent layer, and a second anti-reflective layer on a second side of the transparent layer opposite the first side.

15. The device of claim 12, wherein the second dielectric layer has vertical sidewalls.

16. A device comprising: a semiconductor layer; a first dielectric layer on the semiconductor layer; a transparent layer over the first dielectric layer; a patterned metal layer between the first dielectric layer and the transparent layer, the patterned metal layer having a window aperture; and a second dielectric layer below the semiconductor layer, a cavity extending from the first dielectric layer through the semiconductor layer and through the second dielectric layer.

17. The device of claim 16, further comprising an anti-reflective layer between the patterned metal layer and the first dielectric layer.

18. The device of claim 17, wherein the anti-reflective layer is a first anti-reflective layer, the first anti-reflective layer is on a first side of the transparent layer, and the device further comprising a second anti-reflective layer on a second side of the transparent layer opposite the first side.

19. The device of claim 16, wherein the second dielectric layer has vertical sidewalls.

20. The device of claim 17, further comprising: a device layer below the second dielectric layer; and a mircroelectromecanical system (MEMS) device on the device layer in the cavity, wherein the cavity forms an aperture over the MEMS device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of an example optical electronics device.

(2) FIGS. 2 and 3 are overall flow and flow chart diagrams for an example flow for the fabrication of an assembly like that of the optical electronics device shown in FIG. 1

(3) FIGS. 4A-4K are cross-sectional views illustrating details of steps in an example fabrication method like that shown in FIGS. 2 and 3.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(4) An approach to optical electronic device packaging is described which includes selective removal of material from one wafer of a bonded wafer pair. The method reduces fabrication steps by bonding together material to be removed from one wafer with an etch stop on its partner wafer.

(5) In one aspect, a method of fabricating an optical electronics device includes providing a first wafer having a semiconductor substrate with a first dielectric layer formed over a first surface of the semiconductor substrate and providing a second wafer having a transparent substrate with an anti-reflective coating formed over a first surface of the transparent substrate. A first oxide layer is formed over the anti-reflective coating. The first oxide layer of the second wafer is bonded to the first wafer on a side of the first wafer opposite the first dielectric layer. Portions of the first dielectric layer are removed down to the semiconductor substrate to define first ends for the cavity. Portions of the semiconductor substrate are selectively etched down to the first oxide layer to define the cavity through the semiconductor substrate. The first oxide layer is selectively etched down to the anti-reflective coating to define second ends of the cavity, the anti-reflective coating serving as an etch stop relative to an etchant used to etch the first oxide layer.

(6) The described approach enables the use of a standard anti-reflective (AR) coated window wafer to create a hermetic window assembly in a cost-effective manner.

(7) FIG. 1 illustrates an example optical electronics device 100 resulting from a fabrication method in which a cover or window wafer 200 bonded to a semiconductor interposer wafer 300 is bonded to a MEMS device wafer 400, then singulated. The example optical electronics device 100 may be a packaged MEMS device such as a digital micromirror device (DMD) having micromirror micromechanical elements 102 formed over associated CMOS fabricated integrated circuit microelectronic elements 104 at respective die areas of MEMS device wafer 400 (elements 102, 104 shown only schematically).

(8) Window wafer 200 has a transparent substrate 202 with top and bottom surfaces coated with anti-reflective coating (ARC) layers 204, 206. Transparent substrate 202 may be glass, quartz, or other material that allows for transmission of electromagnetic radiation. Wafer 200 optionally includes a chrome or other opaque material layer 212 patterned to define a window aperture 208 over elements 102 at each die area location. Patterned layer 212 underlies ARC layer 204. Window wafer 200 is bonded (e.g., fusion bonded or direct bonded) to interposer wafer 300 at a silicon dioxide layer 214 formed over layer 204, as indicated by dashed lines in FIG. 1.

(9) Interposer wafer 300 has a silicon semiconductor substrate 302 with a dielectric layer 306 formed on a bottom surface. An optional silicon dioxide layer 304 may be formed on a top surface of the semiconductor substrate 302. If layer 304 is included, both layers 304 and 306 may comprise silicon dioxide layer. If layer 304 is not included, dielectric layer 306 may comprise silicon dioxide, silicon nitride, or some other etch resistant dielectric material. A top side of interposer wafer 300 opposite dielectric layer 306 is bonded to window wafer 200 at silicon dioxide layer 214 (see bond 320 indicated by dashed lines in FIG. 1). One or more bonding layers 502 may be formed on bottom surfaces of interposer wafer 300 for bonding to corresponding one or more bonding layers 504 formed peripherally of micromechanical elements 102 on upper surfaces of MEMS device wafer 400.

(10) The bonded structure 100 (comprising a singulated die area of bonded wafers 200, 300, 400) includes a cavity 314 enclosing micromechanical elements 102 at the die area. Cavity 314 has one end defined by a top surface area of MEMS device wafer 400 containing elements 102 and circumferentially surrounded by joined bonding layers 502, 504. An opposite end of cavity 314 is defined by a top surface area of window wafer 200 providing an exposed area of ARC layer 204 forming aperture 208 and circumferentially surrounded by sidewalls of an opening formed through layer 214. A main part of cavity 314 is defined by a hole through interposer wafer 300 circumferentially surrounded by sidewalls of openings formed through each of optional oxide layer 304, silicon substrate 302, and oxide layer 306. The sides of the opening through substrate 302 are sloped inwardly in the direction of aperture 208. The sidewalls of the opening through layer 214 and the hole through interposer wafer 300 are may be metallized by an optional metal layer 334 which assists in establishing a hermetic seal for the contained elements 102.

(11) FIGS. 2 and 3 summarize an example flow for the fabrication of an assembly like the optical electronics device shown in FIG. 1. FIGS. 4A-4K illustrate more details of steps in the example flow.

(12) The example flow is described in the context of a specific example embodiment for the fabrication of packaged MEMS devices such as digital micromirror devices (DMDs) having micromirror micromechanical elements 102 formed in arrays over associated SRAM cell microelectronic elements 104 arranged in corresponding arrays at respective die areas of a CMOS integrated circuit wafer 400. Similar steps may be applied for the fabrication of other optical electronics devices.

(13) The example process involves etching a bonded wafer pair where the etch stop is buried under the bonding oxide. The bonded wafer pair comprises an interposer wafer and a window wafer which is transparent to at least some wavelengths of electromagnetic radiation at wavelengths of 400 nm to 20,000 nm. In specific cases, the etch stop may be a metal fluoride. The etch stop layer may be the terminal layer of an antireflection coating.

(14) In contrast to previous approaches (see, e.g., the pre-patterned silicon interposer described in previously referenced U.S. Pat. Nos. 7,109,120; 7,118,234; 7,160,791 and 7,833,879), the example approach bonds a completed window wafer to a mechanical spacer interposer wafer and then forms pockets or cavities, taking advantage of the thin film structure to stop etches appropriately. Prior approaches have bonded the window to a pre-pocketed interposer. Forming the pockets after bonding the interposer and the window wafers enables inexpensive bulk and low temperature bonding processes to be used, thereby lowering total cost of assembly.

(15) FIG. 4A shows an interposer wafer 300 usable for providing a cavity defining spacer and supporting structure for the wafer scale hermetic packaging of MEMS devices having microelectronic and micromechanical elements 102, 104 formed using integrated circuit fabricating techniques. The core of interposer wafer 300 may be a double-side polished, high resistivity (>10 Ohms/cm) CZ prime (100) silicon substrate 302 having, for example, an about 500μ thickness. Dielectric layer 306 is formed on a bottom surface of substrate 302. An optional oxide layer 304 may be formed on a top surface of substrate 302. If both dielectric layer 306 and oxide layer 304 are present, dielectric layer 306 and oxide layer 304 comprises silicon dioxide layer and are thermally grown by oxidizing (or, if preferred, are deposited using a CVD or other deposition process) to a thickness of about 1,000 Å to 1μ over each of top and bottom surfaces of the substrate 302. If oxide layer 304 is not included, dielectric layer 306 may alternatively comprise silicon nitride or other etch resistant dielectric. In preparation for wafer-to-wafer bonding the interposer and window wafers, top optional oxide layer 304 may be subjected to a CMP polish.

(16) FIG. 4B illustrates the formation of one or more layers 502 of sealing material over the dielectric layer 306 on interposer wafer 300 in preparation for later joining the bottom surface of interposer wafer 300, after bonding to window wafer 300, to MEMS wafer 400. The one or more sealing material layers 502 are patterned into a grid configuration 503 (inset FIG. 4B) corresponding to a matching grid formation of one or more layers 504 (FIG. 1) of sealing material formed at locations peripherally surrounding mechanical elements 102 of respective die areas on MEMS wafer 400. (See, for example, peripheral metallization bonding layer 172A deposited on light absorbing metallic layer 170 for bonding glass substrate 116 to corresponding peripheral metallization bonding layer 172B of semiconductor substrate 114 in previously referenced U.S. Pat. No. 7,787,170). A hardmask layer 308 of oxide hardmask material is blanket deposited over the patterned one or more sealing layers 502, over the dielectric layer 306.

(17) FIG. 4C shows a cover or window wafer 200 having a glass, quartz or other transparent material (such as one that allows for the transmission of electromagnetic radiation) substrate 202 whose top surface is coated with an anti-reflective coating (ARC) layer 204 and whose bottom surface is coated with an ARC layer 206. Window wafer 200 optionally includes a chrome or other opaque material layer 212 formed on the upper surface before deposition of ARC layer 204 and patterned to define window apertures 208 in a grid formation 220 at positions aligned with corresponding positions of MEMS element (viz., micromirror array) 102 die areas of a MEMS wafer 400 (FIG. 1). A suitable window wafer 200 usable in fabricating packaged DMD devices may be a 1050μ thick, AR coated borosilicate glass wafer having a dark chrome aperture grid patterned under the AR coating 204 on an upper surface thereof. Optical properties of wafer 200 should correspond to optical properties appropriate for the intended example optical MEMS device.

(18) ARC layer 204 may comprise multiple ARC layers of, e.g., about 0.28μ total thickness blanket deposited over a patterned thin film chrome layer 212 of, e.g., about 0.16μ thickness. The top AR coating of ARC layer 204 may be an alkaline earth Group I or II metal fluoride or, optionally, a lanthanide or actinide metal fluoride. Suitable materials include magnesium fluoride (MgF.sub.2), yttrium fluoride (YF.sub.3) and ytterbium fluoride (YbF.sub.3). A layer of Al.sub.2O.sub.3 may be included. The top layer material will serve not only as an AR coating but also as an etch stop for selective etching of interposer wafer 300, as further described below. ARC layer 206 may have a similar composition to ARC layer 204.

(19) As shown in FIG. 4D, in preparation for bonding window wafer 200 to interposer wafer 300, an oxide layer 214 is deposited over ARC layer 204 and planarized to provide a suitable bonding surface. Deposition may be effected, for example, using a Silox or other PECVD process employing silane and nitrous oxide to establish a silicon dioxide layer 214 of about 1-1.4μ (e.g., 1.2μ) thickness. Subsequent planarity may be accomplished using CMP or other planarization (e.g., to meet <200 Å step height fusion bonding or other specification) leaving a remaining oxide layer 214 thickness of, e.g., about 0.6μ. A similar oxide layer 216 may optionally be deposited over ARC layer 206 (not thinned by planarization) to provide protection to the back surface of wafer 200 during handling and fabrication.

(20) Following the preparation, as shown in FIG. 4E, the planarized oxide layer 214 side of window wafer 200 is bonded (as indicated by dashed line 320) to the top surface of interposer wafer 300 (for example, to optional oxide layer 304). This may be done, for example, using a plasma activated low temperature (≤400° C.) wafer-to-wafer fusion bonding process conducted, for example, at about room temperature or so (e.g., at 15-35° C.). The fusion bonding process may be followed by a post-bond anneal conducted, for example, at about 200-300° C. (e.g., 250° C.) for one to several hours.

(21) Next, as shown in FIG. 4F, a layer of photoresist 340 is formed (e.g., spin coated) over hardmask layer 308 on the bottom of interposer wafer 300 (note: top of interposer wafer 300 is bonded to top of window wafer 200 in FIG. 4E), and standard photolithography patterning and developing techniques are applied to pattern photoresist layer 340 to form a mask defining bottom openings 310 of cavities 314 for containment of micromechanical elements 102 at the respective die locations (viz., micromirror arrays at respective DMD die areas) of the MEMS wafer 400 to be subsequently bonded (see FIG. 1). A hardcoat etch is then performed to remove portions of the hardmask layer 308 to transfer the bottom opening pattern 310 from the developed photoresist layer 340 to the hardmask layer 308. This is followed by etching portions of dielectric layer 306 down to the silicon 302 to form first opening ends of cavities 314. This etch may be accomplished, for example, using a fluorocarbon dry etch and/or a buffered oxide (NH.sub.4F/HF mixture) wet etch, followed by a resist strip and clean-up.

(22) Next, as shown in FIG. 4G, an anisotropic etch is performed to selectively remove portions of the silicon from substrate 302 and deepen the cavities 314 down to the buried oxide layer 304, if present, using the patterned oxide hardmask material layer 308 as a mask. If optional layer 304 is not included, the oxide layer 214 functions as the etch stop. An example suitable etchant for this purpose is tetramethylammonium hydroxide (TMAH) which may be used alone or optionally in combination with a dry reactive-ion etch. The example etch defines cavity sidewalls that slope outwardly in the direction away from apertures 208 (inwardly in the downward direction in FIG. 4G).

(23) Thereafter, as shown in FIG. 4H, further etching is applied to selectively remove oxide exposed at the inside ends of cavities 314 to further expand the cavities 314 through oxide layers 304, 214, stopping on ARC layer 204 which acts as an etch stop. The oxide etch may use, for example, a fluorocarbon dry etch and/or a buffered oxide (NH.sub.4F/HF mixture) wet etch. The dry etch may, for example, be a fluorocarbon oxygen plasma.

(24) FIG. 4H illustrates the bonded interposer/window wafer assembly 200/300 with hardmask layer 308 over dielectric layer 306 and all or portions of layers 306 and 216 still present. Thicknesses, compositions and/or number of layers of layers 306, 308, 216 may however be varied and the various etch processes controlled according to individual needs and preferences so that some or all of layers 306, 308, 216 remain in place unless or until subsequent removal at a desired point in the fabrication process. In the example, layers 216, 308 are sacrificial layers configured to respectively protect the unbonded sides of wafers 200 and 300 during at least a majority of the early steps in the fabrication procedure. Additional oxide and/or other sacrificial material layers may also be utilized.

(25) As shown in FIG. 4I, an optional metallization layer 334 may be deposited over the sidewalls of cavities 314. Metallization 334 may be accomplished, for example, using a plating process wherein a metal seed layer is first blanket deposited, then etched to expose layer 208 at the aperture areas 208 at the inner ends of the cavities 314, and then followed by plating metal on top of the seed layer.

(26) Following completion of the cavities 314, the bottom of the bonded window and interposer wafer structure 200/300 is joined to the top of the MEMS device wafer 400. In preparation for the bonding, in the described specific implementation, remaining portions of protective hardmask layer 308 are stripped away to expose the one or more layers 502 of the sealing structure as indicated in FIG. 4J. (As already mentioned, individual preferences and needs may remove some or all of layer 308 at an earlier or later step.) The lower surface of assembly 200/300 is then aligned and mated with and the upper surface of MEMS device wafer 400 as indicated by the inversion of assembly 200/300 and movement in the direction of the downward arrows shown in FIG. 4K.

(27) As already stated, the bonding of the bonded wafer pair 200/300 to the MEMS wafer 400 may include prior or subsequent deposition of one or more layers 502 on bottom surfaces of structure 200/300 peripherally surrounding cavities 314, and/or prior or subsequent deposition of one or more layers 504 in corresponding locations peripherally surrounding micromechanical elements (viz., micromirror arrays) 102 on top surfaces of MEMS device wafer 400. The bonding process mates the facing surfaces of layers 502, 504 to form hermetically sealed (or, optionally, non-hermetic) protective containments for the elements 102. After the bonding of interposer/window wafer assembly 200/300 to MEMS device wafer 400 is complete, the joint wafer assembly 200/300/400 is singulated to separate the respective encapsulated die regions into discrete packaged MEMS devices, such as shown in FIG. 1.

(28) Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.