Semiconductor element and method for producing the same

Abstract

A semiconductor element and a method for producing the same are provided. A semiconductor element includes an active region comprising trenches, a termination region outside the active region, a transient region disposed between the active region and the termination region, the transient region including an inside trench, in which a center poly electrode is disposed inside at least one of the trenches of the active region, at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode, a p-body region is disposed between upper portions of the trenches, and a source region is disposed at a side of the gate poly electrodes.

Claims

1. A semiconductor element comprising: a termination region outside an active region, the active region comprising trenches, wherein a center poly electrode is disposed inside at least one of the trenches; a transient region disposed between the active region and the termination region, the transient region comprising an inside trench; at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode; a p-body region disposed between upper portions of the trenches; a source region disposed at a side of the gate poly electrodes, wherein the source region is not disposed at the p-body region shared with the gate poly electrode formed in the inside trench; a channel stopper region disposed in the termination region, the channel stopper region including a via hole; and an equipotential ring metal disposed over the channel stopper region, the equipotential ring metal electrically connecting to the channel stopper region through the via hole included in the channel stopper region, wherein the via hole penetrates the channel stopper region.

2. The semiconductor element according to claim 1, wherein the active region, the transient region and the termination region are disposed within a substrate, and the termination region does not include a trench.

3. The semiconductor element according to claim 1, further comprising an extension gate poly electrode extending to the termination region from the trench of the transient region.

4. The semiconductor element according to claim 3, wherein a source metal electrically connects the center poly electrode and the source region, a gate metal electrically connects the extended gate poly electrode, and the source metal is substantially coplanar to the gate metal.

5. The semiconductor element according to claim 4, wherein the source metal electrically connects the center poly electrode and the source region through via holes.

6. The semiconductor element according to claim 5, wherein the source metal comprises aluminum, the via holes comprise tungsten, and a barrier metal comprising titanium or titanium nitride is disposed at a bottom surface of the via holes and the source metal.

7. The semiconductor element according to claim 6, wherein an insulating film comprising a high temperature low pressure deposition (HLD) oxide film and a borophosphosilicate glass (BPSG) film is disposed between the via holes.

8. The semiconductor element according to claim 4, wherein the equipotential ring metal is disposed substantially coplanar to the source metal and the gate metal at a periphery of the termination region.

9. The semiconductor element according to claim 8, wherein the channel stopper region is disposed at a surface of a substrate.

10. The semiconductor element according to claim 9, wherein the channel stopper region is an n+ region.

11. The semiconductor element according to claim 3, wherein an oxide layer is disposed under the extension gate poly electrode.

12. The semiconductor element according to claim 11, wherein the oxide layer extends from at least one of the trenches in the active region to the termination region.

13. The semiconductor element according to claim 1, wherein the center poly electrode is disposed within the inside trench of the transient region, and the gate poly electrode is disposed within the inside trench of the transient region in a region closer to the active region than to the termination region.

14. The semiconductor element according to claim 5, wherein a p+ region is disposed at a bottom surface of the via holes.

15. The semiconductor element according to claim 14, wherein a protective layer is disposed on the source metal, the gate metal and the equipotential ring metal.

16. The semiconductor element according to claim 15, wherein the protective layer comprises a nitride film.

17. The semiconductor element according to claim 1, wherein the gate insulating film is disposed between a side of the trench and at least one of the gate poly electrodes, between the gate poly electrodes, and between the center poly electrode and a second center poly electrode, and wherein the gate insulating film is thicker between the gate poly electrode and the center poly electrode than between the side of the trench and the at least one of the gate poly electrode.

18. The semiconductor element according to claim 1, wherein a depth of the p-body region is disposed at an intermediate portion of a depth of the gate poly electrode.

19. The semiconductor element according to claim 2, wherein upper surfaces of the center poly electrode and the gate poly electrodes are substantially coplanar to each other.

20. The semiconductor element according to claim 1, wherein a depth of the inside trench in the transient region is deeper than a depth of the trenches formed in the active region.

21. The semiconductor element according to claim 1, wherein a bottom surface of the gate poly electrodes inclines toward the center poly electrode disposed between the gate poly electrodes.

22. The semiconductor element according to claim 1, wherein a bottom portion of the gate poly electrodes close to the center poly electrode is deeper than a bottom portion of the gate poly electrodes distant from the center poly electrode.

23. The semiconductor element according to claim 1, wherein a p+ region is disposed at a bottom surface of each of the via hole.

24. A semiconductor element comprising: an active region comprising active trenches, wherein the active trenches comprise a first trench and a second trench, wherein each active trench includes a U-shaped portion of oxide layer, and wherein each U-shaped portion includes a left wall, a bottom, and a right wall; a termination region outside the active region; a transient region disposed between the active region and the termination region, the transient region comprising an inside trench; a first center poly electrode located between a left wall of the first trench and a right wall of the first trench; a left gate poly electrode located in a top region of the left wall of the first trench; a right gate poly electrode located in a top region of the right wall of the first trench, wherein the left gate poly electrode and the right gate poly electrode are adjacent to an upper portion of the center poly electrode; a p-body region located between the right wall of the first trench and a left wall of the second trench, and located horizontally to the right of the right gate poly electrode; a source region located directly on top of the p-body region; a channel stopper region disposed in the termination region, the channel stopper region including a via hole that penetrates the channel stopper region; and an equipotential ring metal disposed over the channel stopper region, the equipotential ring metal electrically connecting to the channel stopper region through the via hole included in the channel stopper region, wherein the first trench includes an outer left gate insulating film adjacent to a left surface of the left gate poly electrode, and an inner left gate insulating film adjacent to a right surface of the left gate poly electrode, wherein the outer left gate insulating film has a thin width, the inner left gate insulating film has a thick width, and wherein the thin width is smaller than the thick width.

25. A semiconductor element comprising: a termination region disposed adjacent an active region, the active region including a trench; a transient region disposed between the active region and the termination region, the transient region including an inside trench having a center poly electrode disposed therein, a width of the trench being different from a width of the inside trench; an extension gate poly electrode disposed above entire planar upper surfaces of the inside trench and the trench; an equipotential ring electrode disposed in the termination region; and an insulating layer disposed between the equipotential ring electrode and a metal layer, and between the equipotential ring electrode and a channel stopper region, wherein via holes respectively electrically connect the metal layer to the equipotential ring electrode and the channel stopper region.

26. A semiconductor element comprising: a termination region disposed adjacent an active region, the active region including a trench having a center poly electrode disposed therein; a transient region disposed between the active region and the termination region, the transient region including an inside trench, a width of the trench being different from a width of the inside trench; an extension gate poly electrode disposed above an entire planar upper surface of the inside trench and a portion of a planar upper surface of the trench; an equipotential ring electrode and a channel stopper region both disposed in the termination region; and an insulating layer disposed between the equipotential ring electrode and a metal layer, and between the equipotential ring electrode and a channel stopper region, wherein via holes respectively electrically connect the metal layer to the equipotential ring electrode and the channel stopper region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1 through 9 illustrate an example of a method of producing a semiconductor element.

(2) FIG. 10 illustrates a cross-sectional view of an example of a semiconductor element obtained by the method illustrated in FIGS. 1-9.

(3) FIG. 11 illustrates a magnified cross-sectional view of an upper portion of a trench according to an example of a semiconductor element illustrated in FIG. 10.

(4) FIG. 12 illustrates a plan view of an example of a semiconductor element.

(5) FIG. 13 illustrates a cross-sectional view of an example of a trench along line A-A′ of FIG. 12.

(6) FIG. 14 illustrates a cross-sectional view of an example of a gate poly along line B-B′ of FIG. 12.

(7) FIG. 15 illustrates a cross-sectional view of an example of a center poly along line C-C′ of FIG. 12.

(8) FIG. 16 illustrates a cross-sectional view of an example of a p-body region outside an active region along line D-D′ of FIG. 12.

(9) Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

(10) The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the systems, apparatuses and/or methods described herein will be apparent to one of ordinary skill in the art. The progression of processing steps and/or operations described is an example; however, the sequence of and/or operations is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps and/or operations necessarily occurring in a certain order. Also, descriptions of functions and constructions that are well known to one of ordinary skill in the art may be omitted for increased clarity and conciseness.

(11) The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will convey the full scope of the disclosure to one of ordinary skill in the art.

(12) Unless indicated otherwise, a statement that a first layer is “on” a second layer or a substrate is to be interpreted as covering both a case where the first layer is directly contacts the second layer or the substrate, and a case where one or more other layers are disposed between the first layer and the second layer or the substrate.

(13) The spatially-relative expressions such as “below”, “beneath”, “lower”, “above”, “upper”, and the like may be used to conveniently describe relationships of one device or elements with other devices or among elements. The spatially-relative expressions should be understood as encompassing the direction illustrated in the drawings, added with other directions of the device in use or operation. Further, the device may be oriented to other directions and accordingly, the interpretation of the spatially-relative expressions is based on the orientation.

(14) The expression such as “first conductivity type” and “second conductivity type” as used herein may refer to the conductivity types such as n or p types which are opposed to each other, and an example explained and exemplified herein encompasses complementary examples thereof.

(15) Hereinafter, various embodiments of the present disclosure will be described in detail in reference to the drawings.

(16) According to some examples, a method for forming a semiconductor element involves simultaneously forming various via holes at an insulating film in order to electrically connect a center poly electrode and a gate poly electrode respectively.

(17) Additionally, some examples relate to a semiconductor element and a method for producing the same which forms the source metal connected with the center poly electrode through a plurality of via holes and the gate metal connected with the gate poly electrode, the source metal and the gate metal being substantially coplanar to each other.

(18) FIGS. 1 through 9 illustrate cross-sectional views of a semiconductor element during an example of a method of producing the semiconductor element. FIG. 10 illustrates an example of semiconductor element that is obtained by the method illustrated in FIG. 1-9. FIG. 11 illustrates a magnified cross-sectional view of an upper portion of a trench of the semiconductor element illustrated in FIG. 10.

(19) Referring to FIG. 11, a semiconductor element according to an example includes: a substrate 10; an active region 100 including a plurality of trenches 11 formed on the substrate 10; a termination region 200 other than the active region 100; and a transient region 300 including at least one trench 11 formed between the active region 100 and the termination region 200. The plurality of trenches 11 of the active region 100 include therein a center poly electrode 13 formed at the center of the trench, and at least two gate poly electrodes 16 formed at the side of the upper portion of the center poly electrode 13. A p-body region 18 and an upper portion of the p-body region 18 are formed between upper portions of the plurality of trenches 11. Further, a plurality of via holes 23c are formed in order to electrically connect a source region 22 formed at a side of the gate poly electrode 16 and the center poly electrode 13 and source region 22. Further, an extension gate poly electrode 20 extends to the termination region 200 from the trenches 11. Polysilicon may be used as a material for forming the gate poly electrodes 16 and the center poly electrode 13.

(20) A source metal 24c electrically connecting the center poly electrode 13 and the source region 22, and a gate metal 24b electrically connecting the extended gate poly electrode 20 are formed substantially coplanar to each other.

(21) The source metal 24c electrically connects the center poly electrode 13 and source region 22 through the various via holes 23c.

(22) The source metal 24c and the via holes 23c consist of aluminum (Al) and tungsten (W) respectively. A barrier metal including titanium, titanium nitride or a combination thereof (Ti/TiN) is disposed at a side and a bottom portion of the source metal 24c and the via hole 23c.

(23) A bottom portion of the p-body region 18 exists between a bottom portion of the gate poly electrode 16 and a bottom portion of the center poly electrode 13.

(24) A p+ region exists at a bottom portion of the via holes 23c.

(25) An equipotential ring (EQR) metal 24a is formed substantially coplanar to the source metal 24c and gate metal 24b at an exterior angle of the termination region 200.

(26) An oxide layer 12 is disposed at a bottom portion of the extension gate poly electrode 20.

(27) The oxide layer 12 may extend from the surfaces of the various trenches 11 formed on the active region 100 to the termination region 200.

(28) The transient region 300 includes at least one trench formed between the active region 100 and the termination region 200. The inside trench 11 of the transient region 300 includes a center poly electrode 13 therein, and a gate poly electrode 16 is formed at a side of the upper portion of the inside trench 11 close to the active region 100 in an asymmetric structure with the center poly electrode 13 as a center. In this example, the gate poly electrode 16 is not disposed at a side of the inside trench 11 close to the terminal region 200.

(29) A protective layer 25 is formed over the upper portions of the source metal 24c, gate metal 24b and equipotential ring metal 24a. The protective layer 25 includes a nitride film.

(30) FIG. 11 illustrates a magnified cross-sectional view of an upper portion of a trench illustrated in FIG. 10. Referring to FIG. 11, the gate insulating films 27a, 27b exist between the side of the trench 11 and the gate poly electrode 16, and between the gate poly electrodes 16, and between the center poly electrodes 13, and a width A of the gate insulating film 27a between the gate poly electrode 16 and the center poly electrode 13 may be thicker than a width B of the gate insulating film 27b between the side of the trench 11 and the gate poly electrode 16.

(31) Referring back to FIG. 10, the source region 22 may not exist at the p-body region 18 shared with the gate poly electrode 16 formed in the asymmetric structure.

(32) A channel stopper region 26 may further exist at a surface of the substrate 10 of the bottom portion of the equipotential ring metal 24a.

(33) The equipotential ring metal 24a becomes equipotential by being connected with the substrate 10 through via hole 23d contacted with the channel stopper region 26.

(34) The via hole 23d is capable of being connected with the substrate by passing through the channel stopper region 26 and capable of injecting additionally a p+ ion to reduce a contact resistance with the substrate of the bottom portion of the via hole 23d.

(35) The bottom portion of the p-body region 18 exists upon the bottom portion of the gate poly electrode 16.

(36) The channel stopper region 26 is an N+ region.

(37) The upper portions of the center poly electrode 13 and the gate poly electrode 16 are substantially coplanar to the surface of the substrate 10.

(38) A depth of the trench 11 formed between the active region 100 and the termination region 200 may be deeper than that of the trench 11 formed in the active region 100.

(39) The bottom portion of the gate poly electrode 16 may be formed as an inclined surface with the center poly electrode 13 as a center. For example, the bottom portion of the gate poly electrode 16 close to the center poly electrode 13 may be deeper than that of the gate poly electrode 16 distant therefrom, as illustrated in FIG. 11. An example of a method for producing a semiconductor element involves: forming an active region 100 including various trenches 11 formed on the substrate 10, a termination region 200 other than the active region 100, and a transient region 300 including at least one trench formed between the active region 100 and the termination region 200. The process of forming the active region 100 including the plurality of trenches 11 may involve: forming the center poly electrode 13 at the center portion of each trench 11 formed at the active region 100, forming the gate poly electrode 16 at the upper portions of both sides of the center poly electrode 13, forming the insulating film 23 at the upper portion formed of the center poly electrode 13 and gate poly electrode 16, simultaneously forming the various via holes 23a, 23b, 23c, 23d at the insulating film 23 in order to electrically connect each of the center poly and gate poly electrodes 13, 16.

(40) Also, the forming of the gate poly electrode 16 may involve: injecting impurities at the sides of the various trenches 11 and the upper portion of the center poly electrode 13; forming gate insulating films 27a, 27b by oxidizing the sides of the trenches 11 injected with the impurities and center poly electrode 13; and etching at the upper portions of the gate insulating films 27a, 27b after depositing the gate poly.

(41) The method may further involve forming the barrier metal including Ti/TiN at the sides and the bottom portions of the various via holes 23a, 23b, 23c, 23d.

(42) The method may further involve forming the source metal 24c connected with the center poly electrode 13 through the various via holes 23a, 23b, 23c, 23d and the gate metal 24b connected with the gate poly electrode 16. The source metal 24c and the gate metal 24b may be substantially coplanar, as illustrated in FIG. 10.

(43) The forming of the center poly electrode 13 and gate poly electrode 16 may be characterized in that the upper portion of the center poly electrode 13 and the upper portion of the gate poly electrode 16 may be substantially coplanar to the surface of the substrate 10.

(44) The insulating film 23 includes a high temperature low pressure deposition (HLD) oxide film and a borophosphosilicate glass (BPSG) film.

(45) An example of a method for producing a semiconductor element having the configuration described above will be described below by referring to FIGS. 1 through 9.

(46) Referring to FIG. 1, a trench 11 is formed in an active region 100 of a side of a substrate 10.

(47) For example, an n-type epi wafer substrate 10 is provided, and a deep trench hard masking procedure is performed on the substrate 10 using a trench mask. At this time, an etch process is performed by using stacked layer of a silicon nitride (NIT) and an silicon oxide as a hard mask because a photo resist (PR) by itself may not endure a dry etching process, such as a deep trench etching process, that may be subsequently performed.

(48) After the etching process, a plurality of trenches 11 is formed by performing a deep trench photo and trench etch. A method of a trench etch performed may be an anisotropic dry etch process.

(49) Afterward, the substrate 10 is oxidized with a sacrificial oxide film. At this time, when it comes to forming a first sacrificial oxide film, the surface of a silicon substrate 10 generated when performing trench etch, i.e., a plasma damage region brought when performing trench etch of the inside trench 11 is oxidized with the sacrificial oxide film, and then etch is removed and thus the plasma damage region of the surface of the surface of the trench 11 is removed.

(50) Afterward, as illustrated in FIG. 2, an oxide layer 12 and the center poly electrode 13 are formed.

(51) The oxide layer 12 may include a second sacrificial oxide layer, or a field oxide layer.

(52) If the surface of the substrate 10 is oxidized, a higher rated voltage (a BVDSS) may be realized by electric field being distributed due to the oxide layer 12. A higher rating (the BVDSS) may be realized as the oxide layer 12 can serve a role in a reduced surface field effect (RESURF effect) such that sufficient electric field may be supported between the trenches and therefore a higher electric field formation can be obtained.

(53) A formation of center poly electrode 13 is performed by a formation of doping poly, a poly oxide, a poly etch-back in order. The center poly electrode 13 is a middle electrode among the three gate poly electrodes formed in on trench 11 after a final process, and it is a poly electrode contacted with a source by a succeeding process through a source metal unlike two different right/left side poly electrodes.

(54) To form a doping poly, the center poly electrode 13 doped of impurities (i.e., a dopant) for enhancing a conductivity of the poly electrode is formed.

(55) To oxidize the poly, once the center poly electrode 13 is formed in the trench 11, an upper portion of the poly is oxidized for flattening a formation caused from a center portion of the center poly electrode 13 being formed as dented in the middle by a trench structure.

(56) To perform the poly etch-back, the center poly electrode 13 is etched up to the upper portion of the oxide layer 12.

(57) After this, the plasma damage region generated at the upper portion of the center poly electrode 13 is removed by oxidization when poly etch is performed. A formation of leakage current caused from the center poly electrode 13 is removed by the process in advance. Accordingly, the reliability of the device can be enhanced.

(58) Afterward, referring to FIG. 3, the oxide layer 12 formed on the upper portions of the stopper region 26 and the substrate 10 of the active region 100 and the side of the trench 11 in the active region 100 is removed by merely etching the oxide layers 12 of the channel stopper region 26 and the active region 100 among the termination region with using photo resist mask 14.

(59) After the removal, referring to FIG. 4, the gate poly is deposited at the entire sides of the substrate 10 after removing the partial portion of the oxide layer 12 and removing the photo resist mask.

(60) The method may further involve forming the gate insulating films 27a, 27b before depositing the gate poly. Referring to FIG. 11, the method may further involve injecting an impurity ion to the entire sides before forming the gate insulating films 27a, 27b after removing the mask when forming the gate insulating films 27a, 27b. Accordingly, a thickness A of the gate insulating film 27a between the gate poly electrode 16 and the center poly electrode 13 could be thicker than a thickness B of the gate insulating film 27b between the trench 11 side and the gate poly electrode 16 to be formed. As described above, a high speed switching can be feasible by reducing a parasitism capacitance with the gate poly electrode 16 and the center poly electrode 13.

(61) Afterward, referring to FIG. 5, a p-body region 18 is formed between the trenches 11 by using the p-body region mask. The p-body region 18 is formed through an implant of a p type dopant and spread in an n-type epi wafer substrate 10 as a p-well.

(62) Next, referring to FIG. 6, the equipotential ring electrode 19 and the extension gate poly electrode 20 are formed at the termination region 200, and the gate poly electrode 16 is formed at an inside trench 11 of the active region 100 by selectively etching the gate poly electrode 16 using the poly mask.

(63) Next, referring to FIG. 7, a source region 22 is formed at the upper portion of the p-body region 18 and simultaneously a channel stopper region 26 is formed at the termination region 200 through the source mask. The source region 22 may be formed at the upper portion of the inside p-body region 18 through implanting an n type dopant.

(64) The equipotential ring metal 24a becomes equipotential by being connected through the channel stopper region 26 and via hole 23d. Also, the via hole 23d connected with the channel stopper region 26 may be equipotential by being connected with the substrate 10 by passing through the channel stopper region 26. The channel stopper region 26 may be an N+ region.

(65) The channel stopper region 26 includes a depletion layer that extends when a P-N reverse bias is permitted, and serves a role of preventing the depletion layer from being further extended by performing a N+ or P+ doping in order that the depletion layer would not be extended to the chip edge accordingly.

(66) Next, referring to FIG. 8, the insulating film region 23 is formed on the entire sides of the substrate after forming the source region 22. The insulating film 23 may be formed as a double layer of a high temperature low pressure deposition (HLD) oxide film and a borophosphosilicate glass (BPSG) film, and each via holes 23a, 23b, 23c, 23d are formed at the upper portions of the equipotential ring electrode 19, the extension gate poly electrode 20, the gate poly electrode 16, the center poly electrode 13 and the p-body region 18 by etching the insulating film region 23.

(67) The insulating film region 23 insulates the gate electrode and the top metal to be performed on a succeeding process with an inter level dielectric (ILD). At this time, the via holes 23a, 23b, 23c, 23d are each formed at the corresponding portions to the equipotential ring electrode 19, the extension gate poly electrode 20, the gate poly electrode 16, the center poly electrode 13 and the p-body region 18 respectively by etching the insulting film region 23 with processes of contact photo and etch.

(68) A p+ region is formed by implanting and annealing the p type dopant in the p-body region 18 through the each via holes 23a, 23b, 23c, 23d. In this regard, latch-up may be prevented by suppressing a turn-on easily through lowering the base resistance (Rb) of a NPN parasitic transistor in the p-body region 18 when reverse current passes.

(69) Next, referring to FIG. 9, the equipotential ring metal 24a, gate metal 24b and source metal layer 24c are each formed at the upper portion of the insulating film region 23.

(70) The equipotential ring metal 24a, gate metal 24b and source metal layer 24c are formed as metal layers at corresponding portions of the semiconductor element, respective to the equipotential ring electrode 19, gate poly electrode 20, center poly electrode 13 and p-body region 18 through each via hole 23a, 23b, 23c, 23d. Therefore, the above metal layers 24a, 24b, 24c consist of the equipotential ring metal layer 24a, gate metal layer 24b and source metal layer 24c.

(71) As to the insulating film region 23, a barrier metal sputter method is applied in order to prevent Aluminum spike. The barrier metal consists of Ti/TiN and, afterward, forms the equipotential ring metal layer 24a, gate metal layer 24b and source metal layer 24c by forming a metal layer through Aluminum sputtering after filing a contact region (herein, a via hole) with a W-plug.

(72) Afterward, referring to FIG. 10, by forming a protective layer 25 over the upper portions of the each metal layer 24a, 24b, 24c, a semiconductor element according to an example embodiment may be produced. In this example, the protective layer 25 may be formed of a material containing nitride film for protecting the chip on the each metal layers 24a, 24b, 24c.

(73) FIG. 12 illustrates a plan view of an example of a semiconductor element. FIG. 13 illustrates a horizontal view of an example of a trench along line A-A′ of FIG. 12. FIG. 14 illustrates a vertical view of an example of a gate poly along line B-B′ of FIG. 12. FIG. 15 illustrates a vertical view of an example of a center poly along line C-C′ of FIG. 12. FIG. 16 illustrates a vertical view of an example of a p-body region other than an active region along line D-D′ of FIG. 12.

(74) Referring to FIG. 10, in an example of the semiconductor element, the middle center poly electrode 13 connects with the equipotential ring metal layer 24a, gate metal layer 24b and source metal layers 24c by designing the gate poly electrode 16 merely within one side in the chip.

(75) Therefore, a semiconductor element of a triple poly structure having two gate poly electrodes 16 and one center poly electrode 13 in one trench 11 is provided herein, and the additional mask process for connecting center poly may be omitted. Thus, the whole process can be simplified by performing a contact etch process of the upper portion of the center poly electrode 13 and a contact etch process of the p-body region 18 simultaneously, and thereby forming via holes simultaneously and thereby connecting with the top metal layers 24a, 24b, 24c.

(76) While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.