Slew-rate compensated transistor turnoff system

Abstract

In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.

Claims

1. A transistor turnoff system comprising: a transistor control circuit having a control input and a transistor control output, wherein the transistor control circuit is configured to adjust a control voltage at the transistor control output responsive to a comparison signal at the control input, the control voltage having a slew rate; a comparator having a comparator output and first and second comparator inputs, wherein the comparator output is coupled to the control input, the first comparator input is coupled to the transistor control output, and the comparator is configured to: provide the comparison signal at the comparator output responsive to a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage; and a slew-rate compensator having a compensator output coupled to the second comparator input, wherein the slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit, in which the compensation voltage is proportional to the slew rate.

2. The system of claim 1, wherein the compensation voltage is approximately equal to a product of the slew rate and the time delay.

3. The system of claim 1, wherein the slew-rate compensator includes: a capacitor coupled to the transistor control output, the capacitor configured to conduct a first current proportional to the slew rate; a resistor coupled to a reference terminal; and a current mirror coupled to the transistor control output, the comparator and the resistor, in which the current mirror is configured to provide a second current through the resistor to generate the compensation voltage, in which the second current is approximately equal to the first current.

4. The system of claim 3, wherein the second comparator input is coupled through the resistor to the reference terminal, and the current mirror is configured to provide the second current through the resistor responsive to the control voltage.

5. The system of claim 4, wherein the capacitor is a first capacitor and the slew-rate compensator includes a second capacitor coupled to the current mirror, wherein the second capacitor is configured to conduct the second current, the slew-rate compensator is configured to provide a sum of the first and second currents to the transistor control circuit, and the transistor control circuit is configured to reduce the control voltage by adding the sum to a turnoff current at the transistor control output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates an example of a transistor turnoff system.

(2) FIG. 2 illustrates an example of a timing diagram.

(3) FIG. 3 illustrates another example of a timing diagram.

(4) FIG. 4 illustrates an example of a transistor turnoff circuit.

(5) FIG. 5 illustrates another example of a timing diagram.

DETAILED DESCRIPTION

(6) This description relates generally to electronic circuits, and more particularly to a slew-rate compensated transistor turnoff system. For example, the slew-rate compensated transistor turnoff system can be implemented in a two-level turnoff (hereinafter “2LTO”) system in a transistor gate driver. The system can be implemented for providing a controlled deactivation of a transistor (e.g., a bipolar junction transistor (BJT) or a field effect transistor (FET)), such as in a high-voltage switching application. The system includes a transistor control circuit that is activated to reduce a control voltage (e.g., base voltage for a BJT or gate voltage for an FET) in response to a deactivation event. For example, the deactivation event can include a standard deactivation of the transistor, or can include a spurious condition (e.g., a short circuit or a desaturation of the transistor) that can require a controlled deactivation of the transistor. For example, the transistor control circuit can include a current source configured to conduct a current from a control terminal (e.g., base or gate) of the transistor at a slew rate. For example, the slew rate can be programmable, such as based on the current source.

(7) The system also includes a reference comparator configured to compare the control voltage with a predetermined reference voltage. For example, the reference voltage can be equal to a plateau voltage (e.g., the Miller plateau voltage) of the transistor. The reference comparator can be configured to generate a comparison signal provided to the current source, so the comparison signal has a first state to activate the current source and a second state to deactivate the current source. Therefore, in response to the control voltage falling below the reference voltage, the reference comparator can switch the comparison signal from the first state to the second state to deactivate the current source, and thus cease deactivation of the transistor.

(8) The system also includes a slew-rate compensator configured to add a slew-rate adjustment voltage to the reference voltage to provide for a more accurate comparison of the reference voltage and the control voltage. For example, because the reference comparator and/or the transistor control circuit has inherent delays (e.g., of switching), deactivation of the transistor control circuit in response to the control voltage falling below the reference voltage can cause the control voltage to settle below the reference voltage (e.g., by an error voltage amplitude). Such an error voltage amplitude can cause an unacceptable increase in the drain or collector voltage upon reactivation of the transistor at a control voltage slightly below the plateau voltage. The error voltage amplitude can be based on slew rate of the decrease in the control voltage, which can be unpredictable based on a variety of factors, including the characteristics of the transistor (e.g., such as an external transistor coupled to an integrated circuit (IC) that includes the slew-rate compensated transistor turnoff system).

(9) Accordingly, the slew-rate compensator can generate the slew-rate compensation voltage to have an amplitude proportional to the slew rate of the decrease in the control voltage. Therefore, the addition of the slew-rate compensation voltage to the reference voltage can cause the reference comparator to change the state of the comparison signal sooner to account for the inherent time delays of the reference comparator and/or the transistor control circuit. As a result, the static amplitude of the control voltage upon deactivation of the transistor control circuit can be approximately equal to the reference voltage, and thus the plateau voltage of the transistor, to mitigate a potential increase of the drain or collector voltage, and thus to mitigate damage to the transistor. As described herein, the term “approximately equal” can include some deviation from an exact value (e.g., +/−5%).

(10) FIG. 1 illustrates an example of a slew-rate compensated transistor turnoff system 100. The transistor turnoff system 100 can be implemented in any of a variety of high-voltage switching systems to provide for a controlled deactivation of a transistor 102. For example, the transistor turnoff system 100 can be implemented in a 2LTO in a gate driver system, such as for motor controls (e.g., in an electric vehicle). As another example, the transistor turnoff system 100 can be part of an integrated circuit (IC), and the transistor 102 can be an external device electrically coupled to the transistor turnoff system 100 via external pins with respect to the IC.

(11) The transistor turnoff system 100 includes a transistor control circuit 104 coupled to a control terminal of the transistor 102. As described herein, the term “control terminal” refers to a gate in the example of the transistor 102 being configured as a field-effect transistor (FET) or a base in the example of the transistor 102 being configured as a bipolar junction transistor (BJT). The term “control voltage” therefore refers to the voltage at the control terminal, and therefore to either a gate voltage (e.g., a gate to source V.sub.GS) or a base voltage (e.g., a base to emitter voltage (V.sub.BE). As described hereinafter, the control voltage is demonstrated as a voltage V.sub.GE. In response to a deactivation event, such as a desired deactivation of the transistor or a fault condition (e.g., desaturation of the transistor 102 or a short-circuit), the transistor control circuit 104 can be configured to reduce the control voltage V.sub.GE to provide a controlled deactivation of the transistor 102. For example, the transistor control circuit 104 can include a current source configured to conduct a current from the control terminal of the transistor 102 to reduce the control voltage V.sub.GE at a slew rate. For example, the slew rate can be programmable, such as based on the current source.

(12) The transistor turnoff system 100 also includes a reference comparator 106. The reference comparator 106 is configured to compare the control voltage V.sub.GE with a predetermined reference voltage, demonstrated in the example of FIG. 1 as a voltage V.sub.REF. For example, the reference voltage V.sub.REF can be equal to a plateau voltage (e.g., the Miller plateau voltage) of the transistor 102. The reference voltage V.sub.REF is shown as being provided externally, but the reference voltage can instead be generated internally as described herein. The reference comparator 106 can be configured to generate a comparison signal provided to the transistor control circuit 104, such as to control the current source of the transistor control circuit 104. For example, the comparison signal can have a first state to activate the transistor control circuit 104 and a second state to deactivate the transistor control circuit 104. Therefore, in response to the control voltage V.sub.GE falling below the reference voltage V.sub.REF, the reference comparator 106 can switch the comparison signal from the first state to the second state to deactivate the transistor control circuit 104, and thus cease deactivation of the transistor 102 at approximately the reference voltage V.sub.REF, and therefore the plateau voltage amplitude.

(13) As described herein, the phrase “falling below” refers to the control voltage V.sub.GE falling to an amplitude at which the reference comparator 106 begins to switch its output state based on a relative amplitude of the control voltage V.sub.GE and the reference voltage V.sub.REF. Also, as described in greater detail herein, the reference voltage V.sub.REF is adjustable by a slew-rate adjustment voltage to accommodate an error voltage amplitude that can result from time delays of the reference comparator 106 and/or the transistor control circuit 104. Therefore, as described herein, the comparison of the control voltage V.sub.GE with the reference voltage V.sub.REF can be the comparison of the control voltage V.sub.GE with an adjusted reference voltage that is a sum of the reference voltage V.sub.REF and the slew-rate adjustment voltage, as described in greater detail herein.

(14) FIG. 2 illustrates an example of a timing diagram 200. The timing diagram 200 demonstrates a first diagram 202 and a second diagram 204 that plot the control voltage V.sub.GE over time. Each of the diagrams 202 and 204 demonstrate the control voltage V.sub.GE at a substantially constant amplitude starting at a time T.sub.0. For example, the initial amplitude of the control voltage V.sub.GE can be a normal operating voltage (e.g., activation voltage) of the transistor 102. Therefore, at the time T.sub.0 and thereafter at the constant amplitude of the control voltage V.sub.GE, the transistor 102 can be activated. At a time T.sub.1 in both diagrams 202 and 204, a deactivation event occurs. For example, the deactivation event can represent deactivation of the transistor 102, such as based on a fault condition (e.g., desaturation of the transistor 102 or a short-circuit). Therefore, the transistor control circuit 104 can be activated to reduce the control voltage V.sub.GE at a slew rate. In the example of FIG. 2, the first diagram 202 shows a first slew rate, and the second diagram 204 shows a second slew rate below the first slew rate, and therefore decreases at a slower rate than the first slew rate.

(15) In the first diagram 202, the control voltage V.sub.GE falls below an approximate amplitude of the reference voltage V.sub.REF. At a time T.sub.2, the control voltage V.sub.GE has an amplitude approximately equal to the reference voltage V.sub.REF (e.g., falls below the reference voltage V.sub.REF). Therefore, at the time T.sub.2, the reference comparator 106 can change the comparison signal from a first state to a second state to deactivate the transistor control circuit 104. Therefore, the control voltage V.sub.GE ceases to decrease at the slew rate. However, the reference comparator 106 and the transistor control circuit 104 can include inherent delays in operation, such as resulting from the switching of transistors therein. Thus, the amplitude of the control voltage V.sub.GE continues to decrease after the time T.sub.2 until a time T.sub.3, at which time the transistor control circuit 104 is deactivated and the amplitude of the control voltage V.sub.GE remains constant. Therefore, in the example of FIG. 2, the time delay is demonstrated as a time ΔT, which is a duration of time between the time T.sub.2 and the time T.sub.3.

(16) Accordingly, due to the time delay of the reference comparator 106 and/or the transistor control circuit 104, despite the reference comparator 106 detecting that the control voltage V.sub.GE falls below the reference voltage V.sub.REF at the time T.sub.2, the transistor control circuit 104 is not deactivated until the time T.sub.3. As a result, the control voltage V.sub.GE has a constant amplitude below the reference voltage V.sub.REF. The difference between the constant amplitude of the control voltage V.sub.GE after the time T.sub.3 and the reference voltage V.sub.REF is demonstrated in the example of FIG. 2 as a first error voltage V.sub.ERR1. As described above, the reference voltage V.sub.REF can have an amplitude that is equal to a plateau voltage (e.g., Miller plateau) of the transistor 102. Therefore, because the control voltage V.sub.GE has a constant amplitude after the time T.sub.3 that is below the reference voltage V.sub.REF by the first error amplitude V.sub.ERR1, the drain or collector voltage of the transistor 102 can increase to an amplitude that can detrimentally damage to the transistor 102.

(17) In the second diagram 204, the control voltage V.sub.GE falls below an approximate amplitude of the reference voltage V.sub.REF at the second slew rate that is slower than the first slew rate. At a time T.sub.4, the control voltage V.sub.GE has an amplitude approximately equal to the reference voltage V.sub.REF (e.g., falls below the reference voltage V.sub.REF). Therefore, at the time T.sub.4, the reference comparator 106 can change the comparison signal from a first state to a second state to deactivate the transistor control circuit 104. Therefore, the control voltage V.sub.GE ceases to decrease at the slew rate. However, similar to as described above, the reference comparator 106 and the transistor control circuit 104 can include the inherent time delay ΔT. Because the time delay ΔT is associated with the circuit components of the reference comparator 106 and/or the transistor control circuit 104, the time delay ΔT can be the same regardless of the slew rate. Thus, the amplitude of the control voltage V.sub.GE continues to decrease after the time T.sub.4 until a time T.sub.5, at which time the transistor control circuit 104 is deactivated and the amplitude of the control voltage V.sub.GE remains constant.

(18) Accordingly, due to the time delay of the reference comparator 106 and/or the transistor control circuit 104, despite the reference comparator 106 detecting that the control voltage V.sub.GE falls below the reference voltage V.sub.REF at the time T.sub.4, the transistor control circuit 104 is not deactivated until the time T.sub.5. As a result, the control voltage V.sub.GE has a constant amplitude below the reference voltage V.sub.REF, similar to as demonstrated in the first diagram 202. However, because the slew rate in the second diagram 204 is less than in the first diagram 202, the difference between the constant amplitude of the control voltage V.sub.GE after the time T.sub.3 and the reference voltage V.sub.REF is demonstrated in the example of FIG. 2 as a second error voltage V.sub.ERR2 below the first error voltage V.sub.ERR1. Therefore, the error voltage V.sub.ERR can be expressed as a product of the time delay ΔT and the slew rate of the control voltage V.sub.GE. Despite the second error voltage V.sub.ERR2 being below the first error voltage V.sub.ERR1, the control voltage V.sub.GE is still below the reference voltage V.sub.REF. Thus, the drain or collector voltage of the transistor 102 can still increase to an amplitude that can detrimentally damage to the transistor 102 based on the second error voltage V.sub.ERR2.

(19) The example of FIG. 2 describes operation of an example transistor turnoff system. For example, the transistor turnoff system can be subject to the control voltage V.sub.GE achieving a constant amplitude below the reference voltage V.sub.REF, and thus causing potential damage to the transistor 102. However, as described in greater detail herein, the transistor turnoff system 100 can add a slew-rate adjustment voltage to the reference voltage V.sub.REF to provide an adjusted reference voltage. As a result, the comparison of the control voltage V.sub.GE with the slew-rate adjustment voltage

(20) Referring again to the example of FIG. 1, the transistor turnoff system 100 further includes a slew-rate compensator 108. The slew-rate compensator 108 is configured to generate a slew-rate adjustment voltage, described hereinafter as a voltage V.sub.SR, which is proportional to the slew rate of the decrease of the control voltage V.sub.GE, and is further configured to add the slew-rate adjustment voltage to the reference voltage V.sub.REF. Therefore, the reference comparator 106 can compare the control voltage V.sub.GE with the adjusted reference voltage, described hereinafter as a voltage V.sub.ADJ. As a result, the reference comparator 106 can compensate for the time delay ΔT of the reference comparator 106 and/or the transistor control circuit 104 in providing the comparison of the control voltage V.sub.GE with the adjusted reference voltage V.sub.ADJ. As a result, after expiration of the time delay ΔT, the control voltage V.sub.GE can have a substantially constant amplitude approximately equal to the reference voltage V.sub.REF, regardless of the slew rate of the decrease of the control voltage V.sub.GE before deactivation of the transistor control circuit 104. Accordingly, the error voltage V.sub.ERR can be set to approximately zero, thus mitigating the potential for an undesirable increase in the drain or collector voltage during the constant amplitude of the control voltage V.sub.GE.

(21) FIG. 3 illustrates an example of a timing diagram 300. The timing diagram 300 demonstrates a first diagram 302 and a second diagram 304 that plot the control voltage V.sub.GE over time. The timing diagram 300 demonstrates the effect of the comparison of the control voltage V.sub.GE with the adjusted reference voltage V.sub.ADJ by the reference comparator 106, as described above.

(22) Each of the diagrams 302 and 304 demonstrate the control voltage V.sub.GE at a substantially constant amplitude starting at a time T.sub.0. For example, the initial amplitude of the control voltage V.sub.GE can be a normal operating voltage (e.g., activation voltage) of the transistor 102. Therefore, at the time T.sub.0 and thereafter at the constant amplitude of the control voltage V.sub.GE, the transistor 102 can be activated. At a time T.sub.1 in both diagrams 302 and 304, a deactivation event occurs. For example, the deactivation event can represent deactivation of the transistor 102, such as based on a fault condition (e.g., desaturation of the transistor 102 or a short-circuit). Therefore, the transistor control circuit 104 can be activated to decrease the control voltage V.sub.GE at a slew rate. In the example of FIG. 3, the first diagram 302 shows a first slew rate, and the second diagram 304 shows a second slew rate below the first slew rate, and therefore decreases at a slower rate than the first slew rate.

(23) In the example of the first diagram 302, the slew-rate compensator 108 can generate a slew-rate adjustment voltage V.sub.SR1 proportional to the first slew rate. For example, the slew-rate adjustment voltage V.sub.SR1 can be approximately equal to the first error voltage V.sub.ERR1 in the example of FIG. 2. The slew-rate compensator 108 can thus add the slew-rate adjustment voltage V.sub.SR1 to the reference voltage V.sub.REF to provide an adjusted reference voltage V.sub.ADJ to which the reference comparator 106 can compare the control voltage V.sub.GE. Therefore, the control voltage V.sub.GE falls below an approximate amplitude of the adjusted reference voltage V.sub.ADJ. At a time T.sub.2, the control voltage V.sub.GE has an amplitude approximately equal to the adjusted reference voltage V.sub.ADJ (e.g., falls below the adjusted reference voltage V.sub.ADJ). Therefore, at the time T.sub.2, the reference comparator 106 can change the comparison signal from a first state to a second state to deactivate the transistor control circuit 104. Therefore, the control voltage V.sub.GE ceases to decrease at the slew rate. However, the amplitude of the control voltage V.sub.GE continues to decrease after the time T.sub.2 until a time T.sub.3, at which time the transistor control circuit 104 is deactivated and the amplitude of the control voltage V.sub.GE remains constant, based on the time delay ΔT.

(24) Accordingly, due to the time delay of the reference comparator 106 and/or the transistor control circuit 104, upon the reference comparator 106 detecting that the control voltage V.sub.GE falls below the adjusted reference voltage V.sub.ADJ at the time T.sub.2, the transistor control circuit 104 is not deactivated until the time T.sub.3. At the time T.sub.3, the control voltage V.sub.GE has a constant amplitude that approximately equal to the reference voltage V.sub.REF. As a result, there is no error voltage amplitude of the control voltage V.sub.GE after the time T.sub.3, and the reference voltage V.sub.REF has an amplitude that is equal to the plateau voltage (e.g., Miller plateau) of the transistor 102. Accordingly, an increase in the drain or collector voltage of the transistor 102 can be mitigated, so potential damage to the transistor 102 can likewise be mitigated.

(25) In the second diagram 304, the slew-rate compensator 108 can generate a slew-rate adjustment voltage V.sub.SR2 proportional to the second slew rate. For example, the slew-rate adjustment voltage V.sub.SR2 can be approximately equal to the second error voltage V.sub.ERR2 in the example of FIG. 2. The slew-rate compensator 108 can thus add the slew-rate adjustment voltage V.sub.SR2 to the reference voltage V.sub.REF to provide an adjusted reference voltage V.sub.ADJ to which the reference comparator 106 can compare the control voltage V.sub.GE. Therefore, the control voltage V.sub.GE falls below an approximate amplitude of the adjusted reference voltage V.sub.ADJ at the second slew rate that is slower than the first slew rate. At a time T.sub.4, the control voltage V.sub.GE has an amplitude approximately equal to the adjusted reference voltage V.sub.ADJ (e.g., falls below the adjusted reference voltage V.sub.ADJ). Therefore, at the time T.sub.4, the reference comparator 106 can change the comparison signal from a first state to a second state to deactivate the transistor control circuit 104. Therefore, the control voltage V.sub.GE ceases to decrease at the slew rate. However, similar to as described above, the amplitude of the control voltage V.sub.GE continues to decrease after the time T.sub.4 until a time T.sub.5, at which time the transistor control circuit 104 is deactivated and the amplitude of the control voltage V.sub.GE remains constant, based on the time delay ΔT.

(26) Accordingly, due to the time delay of the reference comparator 106 and/or the transistor control circuit 104, upon the reference comparator 106 detecting that the control voltage V.sub.GE falls below the adjusted reference voltage V.sub.ADJ at the time T.sub.4, the transistor control circuit 104 is not deactivated until the time T.sub.5. At the time T.sub.5, the control voltage V.sub.GE has a constant amplitude that approximately equal to the reference voltage V.sub.REF. As a result, there is no error voltage amplitude of the control voltage V.sub.GE after the time T.sub.5, and the reference voltage V.sub.REF has an amplitude that is equal to the plateau voltage (e.g., Miller plateau) of the transistor 102. Accordingly, similar to as described in the first diagram 302, an increase in the drain or collector voltage of the transistor 102 can be mitigated, so potential damage to the transistor 102 can likewise be mitigated. Also, as demonstrated in the example of FIG. 3 herein, the slew-rate compensator 108 can generate the slew-rate adjustment voltage V.sub.SR to have an amplitude proportional to the slew rate, and thus provides for the control voltage V.sub.GE to be set to the constant amplitude approximately equal to the reference voltage V.sub.REF, regardless of the slew rate.

(27) FIG. 4 illustrates an example of a transistor control circuit 400. The transistor control circuit 400 can be implemented in any of a variety of high-voltage switching systems to provide for a controlled deactivation of a transistor (not shown in the example of FIG. 4), such as the transistor 102 of FIG. 1. For example, the transistor control circuit 400 can be implemented for motor controls, such as in an electric vehicle. As another example, the transistor control circuit 400 can be part of an integrated circuit (IC), and the transistor can be an external device electrically coupled to the transistor control circuit 400 via external pins with respect to the IC.

(28) The transistor control circuit 400 includes a transistor control circuit 402. The transistor control circuit 402 includes a current source 404 configured to conduct a current I.sub.G in response to a comparison signal CMP. The transistor control circuit 402 also includes a first resistor R.sub.G1 and a second resistor R.sub.G2, which are each coupled to a terminal 406 that represents the control terminal of the transistor, and which has the control voltage V.sub.GE. Therefore, in response to activation via the comparison signal CMP (e.g., a first state of the comparison signal CMP), such as based on a deactivation event, the current source 404 conducts the current I.sub.G from the terminal 406 via the resistor R.sub.G2 to reduce the amplitude of the control voltage V.sub.GE. In the example of FIG. 4, the current I.sub.G can be expressed as a sum of a turnoff current I.sub.TO provided from the control terminal of the transistor and a current I.sub.SUM. For example, the current I.sub.TO can be greater than the current I.sub.SUM (e.g., by several orders of magnitude). For example, the current I.sub.SUM can have a relatively small amplitude (e.g., below 5 μA, such as 3 μA) relative to the turnoff current (e.g., between 300 mA and 1.2 A). Because the current I.sub.G is expressed as a sum of the current I.sub.SUM and the turnoff current I.sub.TO, the current I.sub.G can have an amplitude that defines the slew rate of the decrease of the control current V.sub.GE.

(29) The transistor control circuit 400 also includes a reference comparator 408. The reference comparator 408 is configured to compare the control voltage V.sub.GE at a non-inverting input via the resistor R.sub.G1 with an adjusted reference voltage V.sub.ADJ at the inverting input. The adjusted reference voltage V.sub.ADJ equals a sum of the reference voltage V.sub.REF and the slew-rate adjustment voltage V.sub.SR, as described above. For example, the reference voltage V.sub.REF can be equal to a plateau voltage (e.g., the Miller plateau voltage) of the transistor. The reference comparator 408 is demonstrated as generating the comparison signal CMP provided to the current source 404 of the transistor control circuit 402. For example, the first state of the comparison signal CMP can activate the current source 404, and a second state can deactivate the current source 404. Therefore, in response to the control voltage V.sub.GE falling below the adjusted reference voltage V.sub.ADJ, the reference comparator 408 can switch the comparison signal from the first state to the second state to deactivate the current source 404, and thus cease deactivation of the transistor at approximately the reference voltage V.sub.REF, and therefore the plateau voltage amplitude, as described herein.

(30) The transistor control circuit 400 further includes a slew-rate compensator 410. The slew-rate compensator 410 includes a voltage source 412 configured to generate the reference voltage V.sub.REF, and further includes a resistor R.sub.SR interconnecting the inverting input of the reference comparator 408 and a terminal 414 coupled to the voltage source 412. As described in greater detail herein, in response to the decrease of the control voltage V.sub.GE, the resistor R.sub.SR can exhibit the slew-rate adjustment voltage V.sub.SR across it, so the slew-rate adjustment voltage V.sub.SR is added to the reference voltage V.sub.REF to provide the adjusted reference voltage V.sub.ADJ at the inverting input of the reference comparator 408.

(31) The slew-rate compensator 410 also includes a first P-channel FET (hereinafter “PFET”) P.sub.1 and a second PFET P.sub.2 configured to conduct a current from a high-voltage rail, demonstrated as a voltage V.sub.DD. In the example of FIG. 4, the PFETs P.sub.1 and P.sub.2 can be sized approximately the same, and are arranged with common sources and common gates, and are therefore arranged as a current-mirror. Particularly, in the example of FIG. 4, in response to activation of the current source 404 during the deactivation event, the current I.sub.G draws the current I.sub.SUM through the resistor R.sub.G1 (e.g., as the sum of the current I.sub.G and the turnoff current I.sub.TO, as described above). The current I.sub.SUM equals a sum of a current I.sub.1 and a current I.sub.2 that are combined at a terminal 416. In the example of FIG. 4, the current I.sub.1 flows through a capacitor C.sub.1 and the current I.sub.2 flows through a capacitor C.sub.2. For example, the capacitors C.sub.1 and C.sub.2 can be sized approximately equally, so the currents I.sub.1 and I.sub.2 can be equal and can form respective halves of the current I.sub.SUM.

(32) For example, in response to the deactivation event, the current source 404 is activated to conduct the current I.sub.G, resulting in the flow of the current I.sub.SUM and thus the decrease of the control voltage V.sub.GE. As a result, the current I.sub.1 flows from the high-voltage rail V.sub.DD through the PFET P.sub.1 and the capacitor C.sub.1. The current I.sub.1 can thus have an amplitude that can be expressed as follows:

(33) $\begin{array}{cc}{I}_1=C_1*{\mathrm{dV}}_{GE}/dt& \mathrm{Equation}1\end{array}$
where dV.sub.GE/dt is the change in amplitude of the control voltage V.sub.GE, and thus the slew rate of the control voltage.

(34) Because the PFETs P.sub.1 and P.sub.2 are arranged as approximately equal sized transistors in a current-mirror configuration, the PFET P.sub.2 is demonstrated in the example of FIG. 4 as conducting a current I.sub.1C that has an amplitude approximately equal to the amplitude of the current I.sub.1. The current I.sub.1C is demonstrated as flowing through the resistor R.sub.SR to provide the slew-rate adjustment voltage V.sub.SR across the resistor R.sub.SR. As a result, the slew-rate adjustment voltage V.sub.SR has an amplitude that can be expressed as follows:

(35) $\begin{array}{cc}{V}_{\mathrm{SR}}=I_{1C}*R_{\mathrm{SR}}=R_{\mathrm{SR}}*C_1*{\mathrm{dV}}_{GE}/dt& \mathrm{Equation}2\end{array}$

(36) Because the slew-rate adjustment voltage V.sub.SR is a factor of the change of amplitude of the control voltage V.sub.GE over time, and thus the slew rate, the slew-rate adjustment voltage V.sub.SR is proportional to the slew rate. For example, the capacitors C.sub.1 and C.sub.2 can be designed for the slew-rate adjustment voltage V.sub.SR to approximately equal the error voltage V.sub.ERR of example transistor control circuits, as described in the example of FIG. 2. For example, the error voltage V.sub.ERR can be described as follows:

(37) $\begin{array}{cc}{V}_{\mathrm{ERR}}=d{V}_{\mathrm{GE}}/\mathrm{dt}*\Delta T& \mathrm{Equation}3\end{array}$

(38) Substituting Equations 1 and 2, results in the following:

(39) $\begin{array}{cc}{V}_{\mathrm{SR}}=R_{\mathrm{SR}}*I_1=R_{\mathrm{SR}}*C_1*{\mathrm{dV}}_{\mathrm{GE}}/dt& \mathrm{Equation}4\end{array}$

(40) Setting V.sub.SR equal to V.sub.ERR results in the following:

(41) $\begin{array}{cc}{V}_{\mathrm{SR}}=R_{\mathrm{SR}}*C_1*{\mathrm{dV}}_{\mathrm{GE}}/dt=d{V}_{\mathrm{GE}}/\mathrm{dt}*\Delta T=V_{\mathrm{ERR}}& \mathrm{Equation}5\end{array}$

(42) Accordingly, Equation 5 can allow for C.sub.1 to be calculated as follows:

(43) $\begin{array}{cc}{C}_1=\Delta T/R_{\mathrm{SR}}& \mathrm{Equation}6\end{array}$

(44) As a result, by sizing the capacitors C.sub.1 and C.sub.2 to be approximately equal based on Equation 6, the slew-rate adjustment voltage V.sub.SR can be set approximately equal to the error voltage V.sub.ERR, which can allow the substantially constant amplitude of the control voltage V.sub.GE, upon deactivation of the current source 404 in response to the second state of the comparison signal CMP, to be approximately equal to the reference voltage V.sub.REF, as described in the example of FIG. 3.

(45) As described above, the capacitor C.sub.2 is configured to conduct the current I.sub.2 to the terminal 416. In the example of FIG. 2, the current I.sub.2 flows from the terminal 414 and can be approximately equal to the current I.sub.1C, as described above. For example, the voltage source 412 that generates the reference voltage V.sub.REF can be a non-ideal voltage reference with an internal resistance. Therefore, the current I.sub.1C can flow through the resistor R.sub.SR, and substantially the entirety of the amplitude of the current I.sub.1C can flow from the terminal 414 as the current I.sub.2 through the capacitor C.sub.2 to maintain stability in the reference voltage V.sub.REF. As a result, without the current I.sub.2 flowing from the terminal 414 through the capacitor C.sub.2 as substantially the entirety of the voltage I.sub.1C, the accuracy of the voltage source 412, and thus the amplitude of the reference voltage V.sub.REF, can be compromised (e.g., through AC noise). The currents I.sub.1 and I.sub.2 are thus combined at the terminal 416 to form the current I.sub.SUM, which flows through the resistor R.sub.G1, and is thus combined with the turnoff current I.sub.TO through the resistor R.sub.G2 to provide the current I.sub.G during activation of the current source 404. Accordingly, the current I.sub.1C can generate the amplitude of the slew-rate adjustment voltage V.sub.SR through the resistor R.sub.SR without affecting the amplitude of the reference voltage V.sub.REF.

(46) FIG. 5 illustrates another example of a timing diagram 500. The timing diagram 500 includes the control voltage V.sub.GE, the current I.sub.1, the current I.sub.2, and the adjusted reference voltage V.sub.ADJ plotted as a function of time. The timing diagram 500 can show operation of the transistor control circuit 400. Therefore, the example of FIG. 4 likewise relates to the following description of the example of FIG. 5.

(47) The timing diagram 500 demonstrates the control voltage V.sub.GE at a substantially constant amplitude starting at a time T.sub.0. For example, the initial amplitude of the control voltage V.sub.GE can be a normal operating voltage (e.g., activation voltage) of the transistor (e.g., the transistor 102). Therefore, at the time T.sub.0 and thereafter at the constant amplitude of the control voltage V.sub.GE, the transistor can be activated. At a time T.sub.1, a deactivation event occurs. For example, the deactivation event can represent deactivation of the transistor, such as based on a fault condition (e.g., desaturation of the transistor or a short-circuit). Therefore, the current source 404 can be activated to conduct the current I.sub.G, and thus to reduce the control voltage V.sub.GE at a slew rate. In response to the current I.sub.G, the current I.sub.SUM likewise flows. As described in the example of FIG. 4, the current I.sub.SUM includes the currents I.sub.1 and I.sub.2 flowing through the respective capacitors C.sub.1 and C.sub.2. Therefore, the timing diagram 500 demonstrates activation of the currents I.sub.1 and I.sub.2 at the time T.sub.1.

(48) Before the time T.sub.1, the adjusted reference voltage V.sub.ADJ has an amplitude approximately equal to the reference voltage V.sub.REF, as generated by the voltage source 412. Before the time T.sub.1, the current I.sub.1 is approximately equal to zero. Therefore, the current I.sub.1C is not generated via the current mirror configuration of the PFETs P.sub.1 and P.sub.2. Because the current I.sub.1C does not flow through the resistor R.sub.SR, the slew-rate adjustment voltage V.sub.SR has an amplitude of approximately zero. Therefore, the adjusted reference voltage V.sub.ADJ is approximately equal to the reference voltage V.sub.REF before the time T.sub.1. However, at the time T.sub.1, in response to the flow of the current I.sub.1, the current I.sub.1C is generated via the current mirror configuration of the PFETs P.sub.1 and P.sub.2. The current I.sub.1C thus flows through the resistor R.sub.SR, thereby increasing the slew-rate adjustment voltage V.sub.SR to an amplitude proportional to the slew rate, and thus approximately equal to the error voltage V.sub.ERR, as described in the example of FIGS. 2 and 3 and based on Equations 3-6. As a result, the amplitude of the slew-rate adjustment voltage V.sub.SR is added to the amplitude of the reference voltage V.sub.REF to form the adjusted reference voltage V.sub.ADJ at the inverting input of the reference comparator 408 at the time T.sub.1. Also, as the current I.sub.1C flows through the resistor R.sub.SR, the current I.sub.2 flows from the terminal 414, approximately equal to the current I.sub.1C, to be combined with the current I.sub.1 at the terminal 416 to form the current I.sub.SUM.

(49) The control voltage V.sub.GE continues to reduce after the time T.sub.1 at the slew rate until a time T.sub.2. Thus, as the control voltage V.sub.GE decreases, the currents I.sub.1 and I.sub.2 continue to flow through the respective capacitors C.sub.1 and C.sub.2 to form the current I.sub.SUM to provide the current flow I.sub.G from the control terminal of the transistor (via the resistors R.sub.G1 and R.sub.G2). At the time T.sub.2, the reference comparator 408 can determine that the control voltage V.sub.GE falls below the adjusted reference voltage V.sub.ADJ, and therefore changes the state of the comparison signal CMP to the second state to deactivate the current source 404. As a result, the current I.sub.G decreases to zero, thereby reducing the control voltage V.sub.GE to approximately the reference voltage V.sub.REF after the time delay ΔT, as described above in the example of FIGS. 3 and 4. Also, the current I.sub.G falling to approximately zero likewise causes the currents I.sub.1 and I.sub.2 to fall to approximately zero. As a result, the current I.sub.1C falls to approximately zero, which likewise causes the slew-rate adjustment voltage V.sub.SR to fall to approximately zero. Accordingly, the adjusted reference voltage V.sub.ADJ falls to the approximate amplitude of the reference voltage V.sub.REF at the time T.sub.2.

(50) Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.