Hafnium oxide-based ferroelectric field effect transistor and manufacturing method thereof

Abstract

A hafnium oxide-based ferroelectric field effect transistor includes a substrate, an isolation region arranged around the substrate; a gate structure including a buffer layer, a floating gate electrode, a hafnium oxide-based ferroelectric film layer, a control gate electrode and a film electrode layer which are sequentially stacked from bottom to top at a middle part of an upper surface of the substrate, a side wall arranged outside the gate structure, a source region and a drain region arranged oppositely at two sides of the gate structure and are formed by extending from an inner side of the isolation region to the middle part of the substrate, a first metal silicide layer formed by extending from the inner side of the isolation region to the side wall, and a second metal silicide layer arranged on an upper surface of the gate structure.

Claims

1. A hafnium oxide-based ferroelectric field effect transistor, comprising: a substrate (1); an isolation region (2) arranged around the substrate (1), wherein an upper surface of the isolation region (2) is not lower than that of the substrate (1), and a bottom surface of the isolation region (2) is not lower than that of the substrate (1); a gate structure (3) including a buffer layer (31), a floating gate electrode (32), a hafnium oxide-based ferroelectric film layer (33b), a control gate electrode (34) and a film electrode layer (35) which are sequentially stacked from bottom to top at a middle part of the upper surface of the substrate (1); a side wall (4) arranged outside the gate structure (3), wherein an inner surface of the side wall (4) is closely attached to the gate structure (3); a source region (5) and a drain region (6) which are oppositely arranged on two sides of the gate structure (3) and are formed by extending from an inner side of the isolation region (2) to the middle part of the substrate (1), wherein upper surfaces of the source region (5) and the drain region (6) are flush with that of the substrate (1), and bottom surfaces of the region (5) and the drain region (6) are not lower than that of the isolation region (2); a first metal silicide layer (71) formed by extending from the inner side of the isolation region (2) to the side wall (4), wherein an upper surface of the first metal silicide layer (71) is higher than that of the substrate (1); a bottom surface of the first metal silicide layer (71) is higher than that of the isolation region (2); and the first metal silicide layer (71) is shorter than the source region (5) or the drain region (6); and a second metal silicide layer (72) arranged on an upper surface of the gate structure (3), wherein a lower surface of the second metal silicide layer (72) is closely attached to the gate structure (3); and wherein the floating gate electrode (32) and the control gate electrode (34) are made from HfN.sub.x, wherein 0<x≤1.1; each of the floating gate electrode (32) and the control gate electrode (34) has a thickness of 5 nm to 50 nm; the hafnium oxide-based ferroelectric film layer (33b) has a thickness of 3 nm to 20 nm; and wherein the floating gate electrode (32), the hafnium oxide-based ferroelectric film layer (33b), and the control gate electrode (34) jointly form a hafnium-based stack and the hafnium-based stack includes a 3-20 nm thick hafnium oxide-based layer interposed between two 5-50 nm thick HfN.sub.x layers.

2. The hafnium oxide-based ferroelectric field effect transistor according to claim 1, wherein the buffer layer (31) is made from any one or more of SiO.sub.2, SiON, Al.sub.2O.sub.3, La.sub.2O.sub.3, HfO.sub.2, HfON, HfSiON, and aluminum-doped HfO.sub.2(Al:HfO.sub.2), and the buffer layer (31) has a thickness of 3 nm to 10 nm.

3. The hafnium oxide-based ferroelectric field effect transistor according to claim 1, wherein the film electrode layer (35) is made from any one or more of polysilicon, amorphous silicon, W, TaN, TiN and HfN.sub.x (0<x≤1.1), and the film electrode layer (35) has a thickness of 10 nm to 200 nm.

4. The hafnium oxide-based ferroelectric field effect transistor according to claim 1, wherein the first metal silicide layer (71) and the second metal silicide layer (72) are made from any one of TiSi.sub.2, CoSi.sub.2 and NiSi.sub.2, and the first metal silicide layer (71) and the second metal silicide layer (72) both have a thickness of 5 nm to 30 nm.

5. The hafnium oxide-based ferroelectric field effect transistor according to claim 1, wherein at least one element from a group consisting of zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N) is doped in the hafnium oxide-based ferroelectric film layer (33b).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a structural schematic diagram of a hafnium oxide-based ferroelectric field effect transistor provided by an embodiment of the present disclosure;

(2) FIG. 2 is a flow chart of a manufacturing method of the hafnium oxide-based ferroelectric field effect transistor provided by an embodiment of the present disclosure; and

(3) FIG. 3a to FIG. 3f are schematic diagrams of a manufacturing process of the hafnium oxide-based ferroelectric field effect transistor provided by an embodiment of the present disclosure.

REFERENCE NUMERALS

(4) 1: substrate; 2: isolation region; 3: gate structure; 31: buffer layer; 32: floating gate electrode; 33a: doped hafnium oxide film layer; 33b: hafnium oxide-based ferroelectric film layer (formed by annealing 32a); 34: control gate electrode; 35: film electrode layer; 4: side wall; 5: source region; 51a: first lightly doped region; 52a: first heavily doped region; 51b: activated first lightly doped region (formed by annealing 51a): 52b: activated first heavily doped region (formed by annealing 52a): 6: drain region; 61a: second lightly doped region; 62a: second heavily doped region; 61b: activated second lightly doped region (formed after annealing at 61a): 62b: activated second heavily doped region (formed after annealing at 62a); 71: first metal silicide layer; and 72: second metal silicide layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(5) To make the purpose, technical solutions, and advantages of the present disclosure clearer, the present disclosure is further described in detail with reference to specific embodiments and the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of conventional structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

(6) It should be noted that the terms “first” and “second” in the description of the present disclosure are merely used for description purpose and cannot be understood to indicate or imply relative importance.

(7) FIG. 1 is a structural schematic diagram of a hafnium oxide-based ferroelectric field effect transistor provided by an embodiment of the present disclosure.

(8) Referring to FIG. 1, an embodiment of the present disclosure provides a hafnium oxide-based ferroelectric field effect transistor, which includes a substrate 1, an isolation region 2, a gate structure 3, side walls 4, a source region 5, a drain region 6, a first metal silicide layer 71 and a second metal silicide layer 72.

(9) Optionally, the substrate 1 is p-type or n-type doped monocrystalline silicon or silicon-on-insulator (SOI for short).

(10) Preferably, an element boron (B) is doped in p-type doping, and an element phosphorus (P) or arsenic (As) is doped in n-type doping.

(11) The isolation region 2 is arranged around the substrate 1; an upper surface of the isolation region 2 is not lower than that of the substrate 1; and a bottom surface of the isolation region 2 is not lower than that of the substrate 1.

(12) Optionally, the isolation region 2 is made from at least one of SiO.sub.2 and Si.sub.3N.sub.4.

(13) The gate structure 3 includes a buffer layer 31, a floating gate electrode 32, a hafnium oxide-based ferroelectric film layer 33b, a control gate electrode 34 and a film electrode layer 35 which are sequentially stacked from bottom to top at a middle part of the upper surface of the substrate 1.

(14) Optionally, the buffer layer 31 is made from any one or more of SiO.sub.2, SiON, Al.sub.2O.sub.3, La.sub.2O.sub.3, HfO.sub.2, HfON, HfSiON, and aluminum-doped HfO.sub.2(Al:HfO.sub.2).

(15) Optionally, the buffer layer 31 has a thickness of 3 nm to 10 nm.

(16) Optionally, at least one element from the group consisting of zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N) is doped in the hafnium oxide-based ferroelectric film layer 33b.

(17) Preferably, at least one element from the group consisting of zirconium (Zr), aluminum (Al), silicon (Si) and lanthanum (La) is doped in the hafnium oxide-based ferroelectric film layer 33b.

(18) Optionally, the hafnium oxide-based ferroelectric film layer 33b has a thickness of 3 nm to 20 nm.

(19) Optionally, the floating gate electrode 32 and the control gate electrode 34 are made from HfNx, and the HfNx includes x N atoms, where 0<x≤1.1.

(20) Optionally, each of the floating gate electrode 32 and the control gate electrode 34 has a thickness of 5 nm to 50 nm.

(21) Optionally, the film electrode layer 35 is made from any one or more of polysilicon, amorphous silicon, W, TaN, TiN and HfN.sub.x(0<x≤1.1).

(22) Optionally, the film electrode layer 35 has a thickness of 10 nm to 200 nm.

(23) The side walls 4 are arranged outside the gate structure 3, and inner surfaces of the side walls 4 are closely attached to the gate structure 3.

(24) The source region 5 and the drain region 6 are oppositely arranged on two sides of the gate structure 3, and are formed by extending from an inner side of the isolation region 2 to the middle part of the substrate 1; the upper surfaces of the source region 5 and the drain region 6 are flush with the substrate 1; and the bottom surfaces of the region 5 and the drain region 6 are not lower than that of the isolation region 2.

(25) The first metal silicide layer 71 extends from the inner side of the isolation region 2 to the side walls 4; the upper surface of the first metal silicide layer 71 is higher than that of the substrate 1; the bottom surface of the first metal silicide layer 71 is higher than that of the isolation region 2; and the first metal silicide layer 71 is shorter than the source region 5 or the drain region 6. A length of the first metal silicide layer 71 refers to a dimension in an extension direction from the inner side of the isolation region 2 to the side walls 4, that is, the dimension in the left-right direction in FIG. 1; and a length of the source region 5 (or the drain region 6) refers to a dimension in an extension direction from the inner side of the isolation region 2 to the middle part of the substrate 1.

(26) The second metal silicide layer 72 is arranged on an upper surface of the gate structure 3, and a lower surface of the second metal silicide layer 72 is closely attached to the gate structure 3.

(27) Optionally, the first metal silicide layer 71 and the second metal silicide layer 72 are made from any one of TiSi.sub.2, CoSi.sub.2 and NiSi.sub.2.

(28) Optionally, each of the first metal silicide layer 71 and the second metal silicide layer 72 has a thickness of 5 nm to 30 nm.

(29) In the above embodiment, when the substrate 1 is made from a p-type doped material, the source region 5 and the drain region 6 are made from n-type doped monocrystalline silicon or silicon-on-insulator; or when the substrate 1 is made from an n-type doped material, the source region 5 and the drain region 6 are made from p-type doped monocrystalline silicon or silicon-on-insulator.

(30) In a specific embodiment of the present disclosure, the hafnium oxide-based ferroelectric field effect transistor includes a substrate 1, an isolation region 2, a gate structure 3, side walls 4, a source region 5, a drain region 6, a first metal silicide layer 71 and a second metal silicide layer 72.

(31) The substrate 1 is p-type doped monocrystalline silicon, and an element boron (P) is doped in p-type doping.

(32) The isolation region 2 is arranged around the substrate 1; an upper surface of the isolation region 2 is not lower than that of the substrate 1; and a bottom surface of the isolation region 2 is not lower than that of the substrate 1, wherein the isolation region 2 is made from SiO.sub.2.

(33) The gate structure 3 includes a buffer layer 31, a floating gate electrode 32, a hafnium oxide-based ferroelectric film layer 33b, a control gate electrode 34 and a film electrode layer 35 which are sequentially stacked from bottom to top at a middle part of the upper surface of the substrate 1, where the buffer layer 31 is made from HfO.sub.2 and has a thickness of 5 nm; an element zirconium (Zr) is doped in the hafnium oxide-based ferroelectric film layer 33b, with a doping amount of 50% and a thickness of 10 nm; the floating gate electrode 32 and the control gate electrode 34 are made from HfN with a thickness of 10 nm; and the film electrode layer 35 is made from polysilicon and has a thickness of 50 nm.

(34) The side walls 4 are arranged outside the gate structure 3; inner surfaces of the side walls 4 are closely attached to the gate structure 3; the side walls 4 are made from SiO.sub.2; and a transverse width of the gate structure 3 is equal to a distance between the two side walls 4.

(35) The source region 5 and the drain region 6 are oppositely arranged on two sides of the gate structure 3, and are formed by extending from an inner side of the isolation region 2 to the middle part of the substrate 1; the upper surfaces of the source region 5 and the drain region 6 are flush with the substrate 1; the bottom surfaces of the region 5 and the drain region 6 are higher than that of the isolation region 2; and an element phosphorus is doped in the source region 5 and the drain region 6.

(36) Specifically, the source region 5 includes an activated first lightly doped region 51b and an activated first heavily doped region 52b, and the drain region 6 includes an activated second lightly doped region 61b and an activated second heavily doped region 62b. The activated first lightly doped region 51b and the activated second lightly doped region 61b are each formed by annealing a lightly doped region, while the activated first heavily doped region 52b and the activated second heavily doped region 62b are each formed by annealing a heavily doped region.

(37) The first metal silicide layer 71 extends from the inner side of the isolation region 2 to the side walls 4; the upper surface of the first metal silicide layer 71 is higher than that of the substrate 1; the bottom surface of the first metal silicide layer 71 is higher than that of the isolation region 2; the first metal silicide layer 71 is shorter than the source region 5 or the drain region 6; and the first metal silicide layer 71 is made from TiSi2 and has a thickness of 10 nm.

(38) The second metal silicide layer 72 is arranged on the upper surface of the gate structure 3; the lower surface of the second metal silicide layer 72 is closely attached to the gate structure 3; and the second metal silicide layer 72 is made from TiSi.sub.2 and has a thickness of 10 nm.

(39) In this embodiment, positions of the source region 5 and the drain region 6 shown in FIG. 1 are merely examples and are not intended to limit the present disclosure; and the positions of the source region 5 and the drain region 6 can be exchanged.

(40) FIG. 2 is a flow chart of a manufacturing method of a hafnium oxide-based ferroelectric field effect transistor provided by an embodiment of the present disclosure.

(41) FIG. 3a to FIG. 3f are schematic diagrams of a manufacturing process of a hafnium oxide-based ferroelectric field effect transistor provided by an embodiment of the present disclosure.

(42) Referring to FIG. 2 and FIG. 3, an embodiment of the present disclosure further provides a manufacturing method of a hafnium oxide-based ferroelectric field effect transistor, which includes the steps of:

(43) S1, cleaning a substrate 1.

(44) S2, arranging an isolation region 2 around the substrate 1, where an upper surface of the isolation region 2 is not lower than that of the substrate 1, and a bottom surface of the isolation region 2 is higher than that of the substrate 1.

(45) S3, forming a multilayer film structure on the substrate 1,

(46) where the operation of forming the multilayer film structure in the S3 includes the following steps of:

(47) S31, forming a buffer layer 31 on the upper surface of the substrate 1.

(48) Optionally, the buffer layer 31 is formed by an atomic layer deposition process, a chemical vapor deposition process, a chemical oxidation process or a thermal oxidation process.

(49) S32, forming a floating gate electrode 32 on the upper surface of the buffer layer 31, where the floating gate electrode 32 is made from HfN.sub.x which includes x N atoms, where 0<x≤1.1; and the floating gate electrode 32 has a thickness of 5 nm to 50 nm.

(50) Optionally, the floating gate electrode 32 is formed by an atomic layer deposition process, a chemical vapor deposition process or a magnetron sputtering process.

(51) S33, forming a doped hafnium oxide film layer 33a on the upper surface of the floating gate electrode 32, where elements doped in the doped hafnium oxide film layer 33a include at least one from the group consisting of zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N).

(52) Optionally, the doped hafnium oxide film layer 33a is formed by an atomic layer deposition process, a metal-organic chemical vapor deposition process or a magnetron sputtering process.

(53) S34, forming a control gate electrode 34 on the upper surface of the doped hafnium oxide film layer 33a, where the control gate electrode 34 is made from HfN.sub.x which includes x N atoms, where 0<x≤1.1; and the control gate electrode 34 has a thickness of 5 nm to 50 nm.

(54) Optionally, the control gate electrode 34 is formed by a magnetron sputtering process, a chemical vapor deposition process or an atomic layer deposition process.

(55) S35, forming a film electrode layer 35 on the upper surface of the control gate electrode 34.

(56) Optionally, the film electrode layer 35 is formed by a magnetron sputtering process or a chemical vapor deposition process.

(57) S4, etching the multilayer film structure formed in the S3 to form a gate structure 3.

(58) Optionally, the etching process is a reactive ion etching process.

(59) S5, respectively forming a first lightly doped region 51a and a second lightly doped region 61a on the substrate 1 and on two sides of the gate structure 3 by adopting a lightly doped drain process.

(60) Optionally, the lightly doped drain process in the S5 includes the following step of:

(61) by taking the gate structure 3 formed in the S4 as a mask, respectively forming a first lightly doped region 51a and a second lightly doped region 61a on the two sides of the gate structure 3 by ion implantation.

(62) S6, forming side walls 4 on the two sides of the gate structure 3, where inner surfaces of the side walls 4 are closely attached to the gate structure 3.

(63) Specifically, the S6 includes the steps of: depositing an insulating dielectric layer on a device structure formed in the S5 by a chemical vapor deposition process, and etching the insulating dielectric layer by a reactive ion etching process to form the side walls 4.

(64) Optionally, the insulating dielectric layer is made from at least one of SiO.sub.2 and Si.sub.3N.sub.4.

(65) S7, respectively forming a first heavily doped region 52a and a second heavily doped region 62a in the first lightly doped region 51a and the second lightly doped region 61a on the two sides of the side walls 4.

(66) Optionally, the first heavily doped region 52a and the second heavily doped region 62a are respectively formed in the first lightly doped region 51a and the second lightly doped region 61a on the two sides of the side walls 4 by an iron implantation process.

(67) S8, depositing electrode metal on a device structure formed in the S7.

(68) Optionally, the electrode metal is deposited by a magnetron sputtering process or a chemical vapor deposition process.

(69) Optionally, the electrode metal is any one of Ti, Co and Ni.

(70) S9, performing rapid thermal annealing on a device structure formed in the S8 to activate ions implanted in the steps S5 and S7 to form a source region 5 and a drain region 6, forming a first metal silicide layer 71 on the source region 5 and the drain region 6, and forming a second metal silicide layer 72 on the upper surface of the gate structure 3.

(71) The step of activating the ions implanted in the steps S5 and S7 to form the source region 5 and the drain region 6 includes:

(72) S91, activating ions implanted in the first lightly doped region 51a and the first heavily doped region 52a to form an activated first lightly doped region 51b and an activated first heavily doped region 52b; and the activated first lightly doped region 51b and the activated first heavily doped region 52b form the source region 5.

(73) S92, activating ions implanted in the second lightly doped region 61a and the second heavily doped region 62a to form an activated second lightly doped region 61b and an activated second heavily doped region 62b; and the activated second lightly doped region 61b and the activated second heavily doped region 62b form the drain region 6.

(74) Sequences of step S91 and step S92 include but are not limited to the above sequences, can be synchronized, or can be appropriately adjusted according to actual needs.

(75) Where, the rapid thermal annealing operation in the S9 further includes:

(76) forming a ferroelectric phase in the doped hafnium oxide film layer to form a hafnium oxide-based ferroelectric film layer 33b.

(77) Optionally, the rapid thermal annealing operation in the step S9 is performed at a temperature of 400° C. to 1000° C.

(78) Optionally, the rapid thermal annealing operation in the step S9 is performed for 1-60 seconds.

(79) Optionally, the rapid thermal annealing operation is performed in vacuum or in an inert gas.

(80) Preferably, the inert gas is N2 or Ar.

(81) Optionally, the first metal silicide layer 71 and the second metal silicide layer 72 are made from any one of TiSi.sub.2, CoSi.sub.2 and NiSi.sub.2.

(82) Optionally, each of the first metal silicide layer 71 and the second metal silicide layer 72 has a thickness of 5 nm to 30 nm.

(83) S10, etching the electrode metal which is deposited in the S8 and unreacted during annealing in the S9 to obtain a hafnium oxide-based ferroelectric field effect transistor.

(84) Optionally, the etching process is a wet etching process.

(85) In the above embodiments, the positions of the first lightly doped region 51a and the second lightly doped region 61a shown in FIG. 3d and FIG. 3e are merely examples and are not intended to limit the present disclosure; the positions of the first lightly doped region 51a and the second lightly doped region 61a can be exchanged; and correspondingly, the positions of the first heavily doped region 52a and the second lightly doped region 62a in FIG. 3e, the positions of the activated first lightly doped region 51b and the activated second lightly doped region 61b in FIG. 3f, and the positions of the activated first heavily doped region 52b and the activated second heavily doped region 62b are adjusted correspondingly.

(86) A manufacturing method of the hafnium oxide-based ferroelectric field effect transistor of the present disclosure will be described below in conjunction with specific embodiments.

EMBODIMENT 1

(87) Referring to FIG. 2 and FIG. 3a to FIG. 3f, Embodiment 1 provides a manufacturing method of a hafnium oxide-based ferroelectric field effect transistor, where the selected substrate 1 is p-type doped Si (p-Si), and the manufacturing method includes the following steps:

(88) Step 1, referring to FIG. 2 and FIG. 3a, firstly, the substrate 1 is cleaned by a standard cleaning process according to a process flow S1. Subsequently, an isolation region 2 is formed by a local oxidation of silicon (LOCOS) process according to a process flow S2, and a region outside the isolation region 2 is defined as an active region.

(89) Step 2, referring to FIG. 2 and FIG. 3b, firstly, the substrate 1 is cleaned again by the standard cleaning process to remove an oxide layer from a surface of the active region; and a buffer layer 31 made from HfO.sub.2 and with a thickness of 5 nm is deposited by an atomic layer deposition process according to a process flow S31.

(90) Step 3, referring to FIG. 2 and FIG. 3b, HfN with a thickness of 10 nm is formed as a floating gate electrode 32 on the buffer layer 31 formed in the step 2 by a magnetron sputtering process according to a process flow S32.

(91) Step 4, referring to FIG. 2 and FIG. 3b, a doped hafnium oxide film layer 33a made from Hf.sub.0.5Zr.sub.0.5O.sub.2 and with a thickness of 10 nm is deposited on the floating gate electrode 32 formed in step 3 by an atomic layer deposition process according to a process flow S33.

(92) Step 5, referring to FIG. 2 and FIG. 3b, HfN with a thickness of 10 nm is deposited as a control gate electrode 34 on the doped hafnium oxide film layer 33a by a magnetron sputtering process according to a process flow S34.

(93) Step 6, referring to FIG. 2 and FIG. 3b, a film electrode layer 35 made from polysilicon and with a thickness of 50 nm is deposited on the HfN control gate electrode 34 formed in the step 5 by a chemical vapor deposition process according to a process flow S35.

(94) Step 7, referring to FIG. 2 and FIG. 3c, a multilayer film structure formed from the step 2 to the step 6 are etched by a reactive ion etching process according to a process flow S4 to form a gate structure 3.

(95) Step 8, referring to FIG. 2 and FIG. 3d, by taking the gate structure 3 formed in the step 7 as a mask, a first lightly doped region 51a and a second lightly doped region 61a are respectively formed by implanting As ions to the substrate 1 from two sides of the gate structure 3 by an ion implantation process according to a lightly doped drain process (LDD) in a process flow S5.

(96) In the Embodiment 1, the substrate 1 is made from p-type doped Si (p-Si), and the first lightly doped region 51a and the second lightly doped region 61a at this position are low-energy shallow junction lightly doped n regions (n−).

(97) Step 9, referring to FIG. 2 and FIG. 3e, firstly, a silicon dioxide layer with a thickness of 100 nm is deposited by a chemical vapor deposition process according to a process flow S6 to cover the gate structure 3 and the substrate 1; subsequently, the silicon dioxide layer is etched away by a dry etching process; and due to anisotropy, a part of silicon dioxide is retained on two sides of the gate structure 3 to form side walls 4.

(98) Step 10, referring to FIG. 2 and FIG. 3f, phosphorus ions are implanted into the substrate 1 from the two sides of the side walls 4 by an ion implantation process according to a process flow S7 after the side walls 4 are formed, so as to respectively form a first heavily doped region 52a and a second heavily doped region 62a in the first lightly doped region 51a and the second lightly doped region 61a on the two sides of the side walls 4.

(99) In the Embodiment 1, the substrate 1 is made from p-type doped Si (p-Si), and the first heavily doped region 52a and the second heavily doped region 62a at this position are n-type heavily doped regions (n+).

(100) Step 11, referring to FIG. 2 and FIG. 3f, electrode metal Ti with a thickness of 50 nm is deposited by a magnetron sputtering process according to a process flow S8 to cover the gate structure 3 and the substrate 1.

(101) Step 12, referring to FIG. 2 and FIG. 3f, a device structure formed in the step 11 is subjected to rapid thermal annealing (RTA) at 500° C. for about 60 seconds in an N2 atmosphere according to a process flow S9.

(102) Specifically, the step of rapid thermal annealing includes:

(103) 1. The ions implanted in the first lightly doped region 51a and the first heavily doped region 52a are activated to form an activated first lightly doped region 51b and an activated first heavily doped region 52b; and the activated first lightly doped region 51b and the activated first heavily doped region 52b form the source region 5.

(104) 2. The ions implanted in the second lightly doped region 61a and the second heavily doped region 62a are activated to form an activated second lightly doped region 61b and an activated second heavily doped region 62b; and the activated second lightly doped region 61b and the activated second heavily doped region 62b form the drain region 6.

(105) 3. The doped hafnium oxide film layer 33a is crystallized to form a hafnium oxide-based ferroelectric film 33b.

(106) 4. A first metal silicide layer 71 is formed on the source region 5 and the drain region 6, and a second metal silicide layer 72 is formed on the upper surface of the gate structure 3.

(107) Step 13, referring to FIG. 2 and FIG. 3F, the electrode metal deposited in the step 11 and unreacted during annealing in the step 12 is etched away by a wet etching process according to a process flow S10 to obtain a hafnium oxide-based ferroelectric field effect transistor.

EMBODIMENT 2

(108) Referring to FIG. 2 and FIG. 3a to FIG. 3f, Embodiment 2 provides a manufacturing method of a hafnium oxide-based ferroelectric field effect transistor, where the selected substrate 1 is p-type SOI base plate, and the manufacturing method includes the following steps:

(109) Step 1, referring to FIG. 2 and FIG. 3a, firstly, the substrate 1 is cleaned by a standard cleaning process according to a process flow S1. Subsequently, a silicon substrate at the isolation region 2 is etched by a reactive ion etching process according to a process flow S2 to form a Mesa structure on the substrate 1 to realize isolation, and a region outside the isolation region 2 is defined as an active region.

(110) Step 2, referring to FIG. 2 and FIG. 3b, firstly, the substrate 1 is cleaned again by the standard cleaning process to remove an oxide layer from a surface of the active region; and a buffer layer 31 made from Al.sub.2O.sub.3 and with a thickness of 5 nm is deposited by a chemical vapor deposition process according to a process flow S31.

(111) Step 3, referring to FIG. 2 and FIG. 3b, HfN.sub.0.5 with a thickness of 20 nm is formed as a floating gate electrode 32 on the buffer layer 31 formed in the step 2 by a chemical vapor deposition process according to a process flow S32.

(112) Step 4, referring to FIG. 2 and FIG. 3b, a doped hafnium oxide film layer 33a with a thickness of 15 nm is deposited on the floating gate electrode 32 formed in the step 3 by an atomic layer deposition process according to a process flow S33, where the doped hafnium oxide film layer 33a is made from aluminum-doped hafnium oxide (Al:HfO.sub.2), with a doping content of 4.8%.

(113) Step 5, referring to FIG. 2 and FIG. 3b, HfN.sub.0.5 with a thickness of 5 nm is deposited as a control gate electrode 34 on the doped hafnium oxide film layer 33a by a chemical vapor deposition process according to a process flow S34.

(114) Step 6, referring to FIG. 2 and FIG. 3b, a film electrode layer 35 made from W and with a thickness of 50 nm is deposited on the HfN.sub.0.5 control gate electrode 34 formed in the step 5 by a magnetron sputtering process according to a process flow S35.

(115) Step 7, referring to FIG. 2 and FIG. 3c, a multilayer film structure formed from the step 2 to the step 6 are etched by a reactive ion etching process according to a process flow S4 to form a gate structure 3.

(116) Step 8, referring to FIG. 2 and FIG. 3d, by taking the gate structure 3 formed in the step 7 as a mask, As ions are implanted into the substrate 1 from the two sides of the gate structure 3 to respectively form a first lightly doped region 51a and a second lightly doped region 61a by an ion implantation process according to a lightly doped drain process (LDD) in a process flow S5.

(117) In the Embodiment 2, the substrate 1 is made from p-type doped Si (p-Si), and the first lightly doped region 51a and the second lightly doped region 61a at this position are low-energy shallow junction lightly doped n regions (n−) 51a.

(118) Step 9, referring to FIG. 2 and FIG. 3e, firstly, a silicon dioxide layer with a thickness of 120 nm is deposited by a chemical vapor deposition process according to a process flow S6 to cover the gate structure 3 and the substrate 1; subsequently, the silicon dioxide layer is etched away by a dry etching process; and due to anisotropy, a part of silicon dioxide retained on two sides of the gate structure 3 to form side walls 4.

(119) Step 10, referring to FIG. 2 and FIG. 3f, phosphorus ions are implanted into the substrate 1 from the two sides of the side walls 4 by an ion implantation process according to a process flow S7 after the side walls 4 are formed, so as to respectively form a first heavily doped region 52a and a second heavily doped region 62a in the first lightly doped region 51a and the second lightly doped region 61a on the two sides of the side walls 4.

(120) In the Embodiment 2, the substrate 1 is made from p-type doped Si (p-Si), and the first heavily doped region 52a and the second heavily doped region 62a at this position are n-type heavily doped regions (n+).

(121) Step 11, referring to FIG. 2 and FIG. 3f, electrode metal Ni with a thickness of 80 nm is deposited by a magnetron sputtering process according to a process flow S8 to cover the gate structure 3 and the substrate 1.

(122) Step 12, referring to FIG. 2 and FIG. 3f, a structure formed from the step 1 to the step 11 is subjected to rapid thermal annealing (RTA) at 700° C. for about 30 seconds in an N.sub.2 atmosphere according to a process flow S9. In this step, formation principles and processes of the hafnium oxide-based ferroelectric film 33b, the source region 5, the drain region 6, the first metal silicide layer 71 and the second metal silicide layer 72 are the same as that in Embodiment 1, which are not repeated here.

(123) Step 13, referring to FIG. 2 and FIG. 3F, the electrode metal deposited in the step 11 and unreacted during annealing in the step 12 is etched away by a wet etching process according to a process flow S10 to obtain a hafnium oxide-based ferroelectric field effect transistor.

EMBODIMENT 3

(124) Referring to FIG. 2 and FIG. 3a to FIG. 3f, Embodiment 3 provides a manufacturing method of a hafnium oxide-based ferroelectric field effect transistor, where the selected substrate 1 is n-type doped Si (n-Si), and the manufacturing method includes the following steps:

(125) Step 1, referring to FIG. 2 and FIG. 3a, firstly, the substrate 1 is cleaned by a standard cleaning process according to a process flow S1. Subsequently, an isolation region 2 is formed on the substrate 1 by a shallow trench isolation (STI) process according to a process flow S2, and a region outside the isolation region 2 is defined as an active region.

(126) Step 2, referring to FIG. 2 and FIG. 3b, firstly, the substrate 1 is cleaned again by the standard cleaning process to remove an oxide layer from a surface of the active region; SiO.sub.2 with a thickness of 0.7 nm grows on the substrate 1 by a chemical oxidization process according to a process flow S31; La.sub.2O.sub.3 with a thickness of 3 nm is deposited by an atomic layer deposition process; and the grown SiO.sub.2 and La.sub.2O.sub.3 are together used as a buffer layer 31.

(127) Step 3, referring to FIG. 2 and FIG. 3b, HfN0.8 with a thickness of 15 nm is formed as a floating gate electrode 32 on the buffer layer 31 formed in the step 2 by a magnetron sputtering process according to a process flow S32.

(128) Step 4, referring to FIG. 2 and FIG. 3b, a doped hafnium oxide film layer 33a with a thickness of 8 nm is deposited on the floating gate electrode 32 formed in the step 3 by a magnetron sputtering process according to a process flow S33, where the doped hafnium oxide film layer 33a is made from Si-doped hafnium oxide (Si:HfO.sub.2), with a doping content of 4%.

(129) Step 5, referring to FIG. 2 and FIG. 3b, HfN.sub.1.1 with a thickness of 5 nm is deposited as a control gate electrode 34 on the doped hafnium oxide film layer 33a by a magnetron sputtering process according to a process flow S34.

(130) Step 6, referring to FIG. 2 and FIG. 3b, a film electrode layer 35 made from TiN and with a thickness of 80 nm is deposited on the HfN.sub.1.1 control gate electrode 34 formed in the step 5 by a chemical vapor deposition process according to a process flow S35.

(131) Step 7, referring to FIG. 2 and FIG. 3c, a multilayer film structure formed from the step 2 to the step 6 are etched by a reactive ion etching process according to a process flow S4 to form a gate structure 3.

(132) Step 8, referring to FIG. 2 and FIG. 3d, by taking the gate structure 3 formed in the step 7 as a mask, B ions are implanted into the substrate 1 from the two sides of the gate structure 3 to respectively form a first lightly doped region 51a and a second lightly doped region 61a by an ion implantation process according to a lightly doped drain process (LDD) in a process flow S5.

(133) In the Embodiment 3, the substrate 1 is made from n-type doped Si (n-Si), and the first lightly doped region 51a and the second lightly doped region 61a at this position are low-energy shallow junction lightly doped p regions (p−).

(134) Step 9, referring to FIG. 2 and FIG. 3e, firstly, a silicon dioxide layer with a thickness of 150 nm is deposited by a chemical vapor deposition process according to a process flow S6 to cover the gate structure 3 and the substrate 1; subsequently, the silicon dioxide layer is etched away by a dry etching process; and due to anisotropy, a part of silicon dioxide retained on two sides of the gate structure 3 to form side walls 4.

(135) Step 10, referring to FIG. 2 and FIG. 3f, B ions are implanted into the substrate 1 from the two sides of the side walls 4 by an ion implantation process according to a process flow S7 after the side walls 4 are formed, so as to respectively form a first heavily doped region 52a and a second heavily doped region 62a in the first lightly doped region 51a and the second lightly doped region 61a on the two sides of the side walls 4.

(136) In the Embodiment 3, the substrate 1 is made from n-type doped Si (n-Si), and the first heavily doped region 52a and the second heavily doped region 62a at this position are n-type heavily doped regions (p+).

(137) Step 11, referring to FIG. 2 and FIG. 3f, electrode metal Co with a thickness of 100 nm is deposited by a magnetron sputtering process according to a process flow S8 to cover the gate structure 3 and the substrate 1.

(138) Step 12, referring to FIG. 2 and FIG. 3f, a device structure formed in the step 11 is subjected to rapid thermal annealing (RTA) at 1000° C. for about 1 second in an Ar atmosphere according to a process flow S9. In this step, formation principles and processes of the hafnium oxide-based ferroelectric film layer 33b, the source region 5, the drain region 6, the first metal silicide layer 71 and the second metal silicide layer 72 are the same as that in Embodiment 1, which are not repeated here.

(139) Step 13, referring to FIG. 2 and FIG. 3F, the electrode metal deposited in the step 11 and unreacted during annealing in the step 12 is etched away by a wet etching process according to a process flow S10 to obtain a hafnium oxide-based ferroelectric field effect transistor.

(140) By adopting the hafnium oxide-based ferroelectric film, the manufacturing method of the hafnium oxide-based ferroelectric field effect transistor in this embodiment enables the manufactured hafnium oxide-based ferroelectric field effect transistor to have a better scalability, can improve a memory density of a memory, and solves the technical problems that an ferroelectric field effect transistor in the prior art is poor in scalability and limits an equal-proportion reduction process of devices. The HfN.sub.x (0<x≤1.1) with an excellent thermal stability is used for manufacturing the floating gate electrode and the control gate electrode; as an Hf series metal, the HfN.sub.x (0<x≤1.1) commendably avoids an interface reaction between the floating gate electrode and the control gate electrode and the hafnium oxide-based ferroelectric film in a crystallization annealing process in the prior art, avoids element diffusion, and improves electrical reliability of the ferroelectric field effect transistor. In addition, the HfN.sub.x can be simply etched, which is beneficial to integration of devices, and solves integration process problems caused by using Pt electrodes as the floating gate electrode and the control gate electrode in the prior art.

(141) The present disclosure aims to protect a hafnium oxide-based ferroelectric field effect transistor and a manufacturing method thereof, which have the following technical effects:

(142) 1. The HfN.sub.x (0<x≤1.1) with an excellent thermal stability is used for manufacturing the floating gate electrode and the control gate electrode; and as an Hf series metal, the HfN.sub.x (0<x≤1.1) commendably avoids an interface reaction between the floating gate electrode and the control gate electrode and the hafnium oxide-based ferroelectric film in a crystallization annealing process in the prior art, avoids element diffusion, and improves electrical reliability of the hafnium oxide-based ferroelectric field effect transistor.

(143) 2. The manufacturing method of a hafnium oxide-based ferroelectric field effect transistor provided by the present disclosure adopts a gate-first process, which can achieve a high integration density; moreover, a self-alignment process is introduced, that is, a gate structure formed after etching is used as a mask, and lightly doped regions are formed on two sides of the gate structure by an ion implantation process, which can lower the process difficulty.

(144) 3. By adopting an RTA technology, operations of the process are simplified; on the one hand, implanted ions are activated to form the source region and the drain region of the hafnium oxide-based ferroelectric field effect transistor; on the other hand, the doped hafnium oxide film layer is crystallized to form a ferroelectric phase, i. e., a hafnium oxide-based ferroelectric film is formed; and metal silicide layers can also be formed on the source region, the drain region and the gate structure to lower a contact resistance.

(145) It should be understood that the above specific embodiments of the present disclosure are merely used to illustrate or explain the principles of the present disclosure, and do not limit the present disclosure. Therefore, any modifications and equivalent substitutions, improvements and the like made without departing from the spirit and scope of the present disclosure should be included in the protection scope of the present disclosure. In addition, the appended claims of the present disclosure are intended to cover all changes and modifications that fall within the scope and boundaries, or equivalents of such scope and boundaries of the appended claims.