SELF-GATED RRAM CELL AND METHOD FOR MANUFACTURING THE SAME

Abstract

The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.

Claims

1. A self-gated Resistive Random Access Memory ‘RRAM’ cell, comprising: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6 gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode.

2. The self-gated RRAM cell according to claim 1, wherein in the stacked structure containing the multiple layers of conductive lower electrodes, the conductive lower electrodes are used as word lines in a vertical cross array structure, any two layers of conductive lower electrodes being isolated by an insulating dielectric layer, a top layer of conductive lower electrode being covered by an insulating dielectric layer, and a bottom layer of conductive lower electrode being isolated from a substrate by an insulating dielectric layer.

3. The self-gated RRAM cell according to claim 2, wherein the conductive lower electrode is made of any of conductive materials selected from a group constituted of metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO, or is made of alloy of any two or more conductive materials selected from a group constituted of metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO; and the conductive lower electrode is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

4. The self-gated RRAM cell according to claim 2, wherein the insulating dielectric layer is made of SiN, SiO, SiON, SiO.sub.2 doped with C, SiO.sub.2 doped with P or SiO.sub.2 doped with F; and the insulating dielectric layer is formed with a thickness of 10 nm-100 nm by chemical vapor deposition or sputtering.

5. The self-gated RRAM cell according to claim 2, wherein the stacked structure is constituted by two layers of conductive lower electrodes which are a first conductive lower electrode (301) and a second conductive lower electrode (302), the second conductive lower electrode (302) being formed on the first conductive lower electrode (301), and the first conductive lower electrode (301) being isolated from the second conductive lower electrode (302) by a second insulating dielectric layer (202), the second conductive lower electrode (302) being covered by a third insulating dielectric layer (203), and the first conductive lower electrode (301) being isolated from the substrate by a first insulating dielectric layer (201).

6. The self-gated RRAM cell according to claim 2, wherein the vertical trench goes through the insulating dielectric layer covering the multiple layers of conductive lower electrodes, the multiple layers of conductive lower electrodes and the insulating dielectric layers sandwiched between the multiple layers of conductive lower electrodes sequentially, and the bottom of the vertical trench is formed within the insulating dielectric layer under the bottom layer of conductive lower electrode.

7. The self-gated RRAM cell according to claim 1, wherein for the M.sub.8XY.sub.6 gated layer formed on the inner wall and the bottom of the vertical trench, M is any of Cu, Ag, Li, Ni or Zn, X is any of Ge, Si, Sn, C or N, and Y is any of Se, S, O or Te.

8. The self-gated RRAM cell according to claim 7, wherein the M.sub.8XY.sub.6 gated layer formed on the inner wall and the bottom of the vertical trench is further made of doped M.sub.8XY.sub.6 material, doping element(s) being one or more of N, P, Zn, Cu, Ag, Li, Ni, Zn, Ge, Si, Sn, C, N, Se, S, O, Te, Br, Cl, F or I.

9. The self-gated RRAM cell according to claim 1, wherein the M.sub.8XY.sub.6 gated layer formed on the inner wall and the bottom of the vertical trench is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

10. The self-gated RRAM cell according to claim 1, wherein the resistance transition layer formed on the surface of the M.sub.8XY.sub.6 gated layer is made of any of inorganic material CuS, AgS, AgGeSe, Cul.sub.xS.sub.y, ZrO.sub.2, HfO2, TiO.sub.2, SiO.sub.2, WO.sub.x, NiO, CuO.sub.x, ZnO, TaO.sub.x, CoO, Y.sub.2O.sub.3, Si, PCMO, SZO or STO, or is made of any of organic material TCNQ, PEDOT, P.sub.3HT or PCTBT, or is made of a material formed by the inorganic material or the organic material being doped and characteristic modified; and the resistance transition layer is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, spin coating, or deposition by magnetron sputtering.

11. The self-gated RRAM cell according to claim 1, wherein the conductive upper electrode formed within the vertical trench whose inner wall is covered by the M.sub.8XY.sub.6 gated layer and the resistance transition layer, an upper surface of the conductive upper electrode being flush with an upper surface of the insulating dielectric layer covering a top layer of conductive lower electrode.

12. The self-gated RRAM cell according to claim 11, wherein the conductive upper electrode is made of any of conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO, or is alloy made of any two or more conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO; and the conductive upper electrode is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

13. A manufacturing method of a self-gated Resistive Random Access Memory ‘RRAM’ cell, comprising: forming a stacked structure containing multiple layers of conductive lower electrodes; etching the stacked structure to form a vertical trench; forming a M.sub.8XY.sub.6 gated layer on an inner wall and a bottom of the vertical trench; forming a resistance transition layer on a surface of the M.sub.8XY.sub.6 gated layer; and forming a conductive upper electrode on a surface of the resistance transition layer, and filling the vertical trench with the conductive upper electrode.

14. The manufacturing method according to claim 13, wherein the step of forming the stacked structure containing the multiple layers of conductive lower electrodes comprises: sequentially forming an insulating dielectric layer on a substrate, forming a conductive lower electrode on the insulating dielectric layer, forming another insulating dielectric layer on the conductive lower electrode, forming another conductive lower electrode on the other insulating dielectric layer, and so on, so that the insulating dielectric layers and the conductive lower electrodes are formed alternately, and the stacked structure containing the multiple layers of the conductive lower electrodes is finally formed after an insulating dielectric layer is formed on a top layer of conductive lower electrode.

15. The manufacturing method according to claim 14, wherein the conductive lower electrode is formed by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering; and the insulating dielectric layer is formed by chemical vapor deposition or sputtering.

16. The manufacturing method according to claim 14, wherein the step of etching the stacked structure to form the vertical trench comprises: etching, using a photolithograph and etching method, the stacked structure through the insulating dielectric layer covering the multiple layers of conductive lower electrodes, the multiple layers of conductive lower electrodes, and the insulating dielectric layers sandwiched between the multiple layers of conductive lower electrodes, the etching being stopped in the insulating dielectric layer under a bottom layer of conductive lower electrode.

17. The manufacturing method according to claim 16, wherein the photolithograph is conventional photolithograph, electron beam exposure, or nanoimprint; and the etching is dry etching or wet etching, which uses a single-step etching process to form the trench in one step, or uses a multi-step etching process to etch the insulating dielectric layers and the conductive lower electrodes separately.

18. The manufacturing method according to claim 13, wherein the step of forming the M.sub.8XY.sub.6 gated layer on the inner wall and the bottom of the vertical trench comprises: forming the M.sub.8XY.sub.6 gated layer on the inner wall and the bottom of the vertical trench by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

19. The manufacturing method according to claim 13, wherein the step of forming the resistance transition layer on the surface of the M.sub.8XY.sub.6 gated layer comprises: forming the resistance transition layer on the surface of the M.sub.8XY.sub.6 gated layer by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, spin coating, or deposition by magnetron sputtering.

20. The manufacturing method according to claim 13, wherein the step of forming the conductive upper electrode on the surface of the resistance transition layer comprises: forming the conductive upper electrode within the vertical trench whose inner wall is covered by the M.sub.8XY.sub.6 gated layer and the resistance transition layer, by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

21. The manufacturing method according to claim 20, wherein the step of forming the conductive upper electrode on the surface of the resistance transition layer further comprises: planarizing the conductive upper electrode, the resistance transition layer and the M.sub.8XY.sub.6 gated layer to form bit lines of a vertical cross array structure, thereby forming a self-gated RRAM cell.

22. The manufacturing method according to claim 21, wherein the step of planarizing comprises: performing a planarization process on the conductive upper electrode, the resistance transition layer and the M.sub.8XY.sub.6 gated layer by a chemical mechanical polishing method, completely removing materials of horizontal parts of the conductive upper electrode, the resistance transition layer and the M.sub.8XY.sub.6 gated layer to complete patterning of the bit lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG. 1 is a schematic diagram of a cross array reading crosstalk phenomenon in a single-R structure;

[0038] FIG. 2 is a schematic diagram of a conventional RRAM vertical cross array integration;

[0039] FIG. 3 is a schematic structure diagram of a self-gated RRAM cell according to an embodiment of the present disclosure;

[0040] FIG. 4 is a flowchart of a method of manufacturing a self-gated RRAM cell according to an embodiment of the present disclosure; and

[0041] FIGS. 5 to 9 are process schematic diagrams of manufacturing a self-gated RRAM cell according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0042] Hereinafter, the present disclosure will be described more completely in the embodiments with reference to the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein. In the drawings, thicknesses of layers and areas are enlarged for clarity, but as a schematic diagram, they should not be regarded as strictly reflecting proportional relationships of their geometric sizes. The drawings are schematic diagrams of ideal embodiments of the present disclosure. The embodiments of the present disclosure should not be considered to be limited to particular shapes of the areas as shown in the drawings, but should include the resulting shapes. The drawings are only illustrative, but should not be construed as limiting the scope of the present disclosure.

[0043] A self-gated RRAM cell provided by the present disclosure comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6 gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode.

[0044] In the stacked structure containing the multiple layers of conductive lower electrodes, the conductive lower electrodes are used as word lines in a vertical cross array structure, any two layers of conductive lower electrodes being isolated by an insulating dielectric layer, a top layer of conductive lower electrode being covered by an insulating dielectric layer, and a bottom layer of conductive lower electrode being isolated from a substrate by an insulating dielectric layer.

[0045] As a preferred scheme, FIG. 3 shows a schematic structure diagram of a self-gated RRAM cell according to an embodiment of the present disclosure. The present embodiment uses a stacked structure with two layers of conductive lower electrodes, i.e., a stacked structure consisting of a first conductive lower electrode 301 and a second conductive lower electrode 302. However, the number of the stacked layers is not limited by the present embodiment.

[0046] As shown in FIG. 3, the RRAM cell comprises the first conductive lower electrode 301, the second conductive lower electrode 302, a M.sub.8XY.sub.6 gated layer 501, a resistance transition layer 601 and a conductive upper electrode 701, wherein the second conductive lower electrode 302 is formed on the first conductive lower electrode 301, and the first conductive lower electrode 301 is isolated from the second conductive lower electrode 302 by a second insulating dielectric layer 202, the second conductive lower electrode 302 is covered by a third insulating dielectric layer 203; and the M.sub.8XY.sub.6 gated layer 501 is formed on an inner wall of the vertical trench which is formed by etching the first conductive lower electrode 301 and the second conductive lower electrode 302, the vertical trench going through the third insulating dielectric layer 203 covering the second conductive lower electrode 302, the second conductive lower electrode 302, the second insulating dielectric layer 202 sandwiched between the first conductive lower electrode 301 and the second conductive lower electrode 302, and the first conductive lower electrode 301 sequentially, and a bottom of the vertical trench being formed within the first insulating dielectric layer 201 under the first conductive lower electrode 301. The resistance transition layer 601 is formed on a surface of the M.sub.8XY.sub.6 gated layer 501 which covers the inner wall of the vertical trench; the conductive upper electrode 701 is formed within the vertical trench whose inner wall is covered by the M.sub.8XY.sub.6 gated layer 501 and the resistance transition layer 601, an upper surface of the conductive upper electrode 701 being flush with an upper surface of the third insulating dielectric layer 203 which covers the second conductive lower electrode 302.

[0047] The conductive lower electrodes, e.g., the first conductive lower electrode 301 and the second conductive lower electrode 302 as shown in FIG. 3, may be made of any of conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO, or may be alloy made of any two or more conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO. The conductive lower electrodes may each be formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

[0048] The insulating dielectric layers, e.g., the first to third insulating dielectric layers 201, 202 and 203, may be made of SiN, SiO, SiON, SiO.sub.2 doped with C, SiO.sub.2 doped with P or SiO.sub.2 doped with F. The insulating dielectric layers may each be formed with a thickness of 10 nm-100 nm by chemical vapor deposition or sputtering,

[0049] In the M.sub.8XY.sub.6 gated layer 501, M is any of Cu, Ag, Li, Ni or Zn, X is any of Ge, Si, Sn, C or N, and Y is any of Se, S, O or Te. The M.sub.8XY.sub.6 gated layer 501 may further be made of doped M.sub.8XY.sub.6 material, doping element(s) being one or more of N, P, Zn, Cu, Ag, Li, Ni, Zn, Ge, Si, Sn, C, N, Se, S, O, Te, Br, Cl, F or L The M.sub.8XY.sub.6 gated layer 501 may be formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

[0050] The resistance transition layer 601 may be made of any of inorganic material CuS, AgS, AgGeSe, Cul.sub.xS.sub.y, ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, WO.sub.x, NiO, CuO.sub.x, ZnO, TaO.sub.x, CoO, Y.sub.2O.sub.3, Si, PCMO, SZO or STO, or made of any of organic material TCNQ, PEDOT, P.sub.3HT or PCTBT, or made of a material formed by the inorganic material or the organic material being doped and characteristic modified. The resistance transition layer 601 may be formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, spin coating, or deposition by magnetron sputtering.

[0051] The conductive upper electrode 701 is formed within the vertical trench whose inner wall is covered by the M.sub.8XY.sub.6 gated layer 501 and the resistance transition layer 601, an upper surface of the conductive upper electrode 701 being flush with an upper surface of the insulating dielectric layer (e.g., the third insulating dielectric layer 203 as shown in FIG. 3) which covers a top layer of conductive lower electrode. The conductive upper electrode 701 may be made of any of conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO, or may be alloy made of any two or more conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO.sub.2, CuTe, Cu.sub.3Ge, ITO or IZO. The conductive upper electrode 701 may be formed by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering. A thickness of the conductive upper electrode 701 is 1 nm-500 nm.

[0052] Based on the self-gated RRAM cell of the above embodiment of the present disclosure, an embodiment of the present disclosure further provides a manufacturing method of a self-gated RRAM cell. As shown in FIG. 4, the method comprises steps 10 to 50.

[0053] In step 10, a stacked structure containing multiple layers of conductive lower electrodes is formed.

[0054] In this step, an insulating dielectric layer is firstly formed on a substrate; then a conductive lower electrode is formed on the insulating dielectric layer; next, another insulating dielectric layer is formed on the conductive lower electrode; then another conductive lower electrode is formed on the other insulating dielectric layer, and so on, so that the insulating dielectric layers and the conductive lower electrodes are formed alternately, and the stacked structure containing the multiple layers of the conductive lower electrodes is finally formed after an insulating dielectric layer is formed on a top layer of conductive lower electrode.

[0055] The conductive lower electrode may be formed by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering; and the insulating dielectric layer may be formed by chemical vapor deposition or sputtering.

[0056] In step 20, the stacked structure is etched to form a vertical trench.

[0057] In this step, etching, the stacked structure is etched, using a photolithograph and etching method, through the insulating dielectric layer covering the multiple layers of conductive lower electrodes, the multiple layers of conductive lower electrodes, and the insulating dielectric layers sandwiched between the multiple layers of conductive lower electrodes, the etching being stopped in the insulating dielectric layer under a bottom layer of conductive lower electrode. The photolithograph is conventional photolithograph, electron beam exposure, or nanoimprint; and the etching is dry etching or wet etching, which uses a single-step etching process to form the trench in one step, or uses a multi-step etching process to etch the insulating dielectric layers and the conductive lower electrodes separately.

[0058] In step 30, a M.sub.8XY.sub.6 gated layer is formed on an inner wall and a bottom of the vertical trench.

[0059] In this step, the M.sub.8XY.sub.6 gated layer is formed by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

[0060] In step 40, a resistance transition layer is formed on a surface of the M.sub.8XY.sub.6 gated layer.

[0061] In this step, the resistance transition layer is formed by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, spin coating, or deposition by magnetron sputtering.

[0062] In step 50, a conductive upper electrode is formed on a surface of the resistance transition layer, and the vertical trench is filled with the conductive upper electrode.

[0063] In this step, the conductive upper electrode is formed within the vertical trench whose inner wall is covered by the M.sub.8XY.sub.6 gated layer and the resistance transition layer, by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

[0064] The step of forming the conductive upper electrode on the surface of the resistance transition layer further comprises: planarizing the conductive upper electrode, the resistance transition layer and the M.sub.8XY.sub.6 gated layer to form bit lines of the vertical cross array structure, thereby forming the self-gated RRAM cell. The step of planarizing comprises: performing a planarization process on the conductive upper electrode, the resistance transition layer and the M.sub.8XY.sub.6 gated layer by a chemical mechanical polishing method, completely removing materials of horizontal parts of the conductive upper electrode, the resistance transition layer and the M.sub.8XY.sub.6 gated layer to complete patterning of the bit lines.

[0065] As a preferred embodiment, a manufacturing process of a self-gated RRAM cell according to the present disclosure will be described in detail with reference to FIGS. 5 to 9. The process particularly comprises steps 1 to 5.

[0066] In step 1 multiple layers of patterned conductive lower electrodes are deposited.

[0067] As shown in FIG. 5, a stacked structure with multiple layers of conductive lower electrodes is formed on a Si substrate 100, the conductive lower electrodes being used as word lines in the vertical cross array structure and being isolated by the insulating dielectric sandwiched therebetween. As a preferred scheme, the present embodiment uses a stacked structure with two layers of conductive lower electrodes, i.e., a stacked structure consisting of a first conductive lower electrode 301 and a second conductive lower electrode 302. However, the number of the stacked layers is not limited by the present embodiment.

[0068] As shown in FIG. 5, the first conductive lower electrode 301 is isolated from the substrate 100 by a first insulating dielectric layer 201, the first conductive lower electrode 301 is isolated from the second conductive lower electrode 302 by a second insulating dielectric layer 202, and the second conductive lower electrode 302 is covered by a third insulating dielectric layer 203, wherein the first conductive lower electrode 301 and the second conductive lower electrode 302 may be formed by chemical electroplating or sputtering. As a preferred scheme, the first conductive lower electrode 301 and the second conductive lower electrode 302 in the present embodiment are made of metal W, and formed with a thickness of 5 nm-100 nm by sputtering.

[0069] The first to third insulating dielectric layers 201, 202 and 203 may be formed by chemical vapor deposition or sputtering, and may be made of SiN, SiO, SiON, SiO.sub.2 doped with C, SiO.sub.2 doped with P or SiO.sub.2 doped with F. As a preferred scheme, the first to third insulating dielectric layers 201, 202 and 203 in the present embodiment may be made of SiO.sub.2 and formed with a thickness of 10 nm-100 nm by chemical vapor deposition.

[0070] In step 2, a vertical trench is formed by etching.

[0071] As shown in FIG. 6, the third insulating dielectric layer 203, the second conductive lower electrode 302, the second insulating dielectric layer 202, the first conductive lower electrode 301 and the first insulating dielectric layer 201 are etched by a photolithograph and etching method, wherein the first conductive lower electrode 301 is etched through and the first insulating dielectric layer 201 is not etched through, so as to form the vertical trench 401. In this step, the photolithograph may be a pattern transfer technology, such as conventional photolithograph, electron beam exposure, nanoimprint etc.; and the etching may be dry etching or wet etching. Since the etching is performed on a plurality of thin films, a single-step etching process may be used to form the trench in one step, or a multi-step etching process may be used to etch the insulating dielectric layers and the conductive lower electrodes separately.

[0072] In step 3, a M.sub.8XY.sub.6 gated layer 501 is formed within the vertical trench.

[0073] As shown in FIG. 7, as a preferred embodiment, the M.sub.8XY.sub.6 gated layer 501 may be made of Cu.sub.8GeS.sub.6 or Ag.sub.8GeS.sub.6, and may be formed with a thickness of 5 nm-200 nm by deposition using a single target sputtering or a multi-target sputtering method.

[0074] In step 4, a resistance transition layer 601 is deposited on the M.sub.8XY.sub.6 gated layer 501 within the vertical trench 401.

[0075] As shown in FIG. 8, as a preferred embodiment, the resistance transition layer 601 may be made of GeS or HfO.sub.2, and may be prepared with a thickness of 1 nm-30 nm by sputtering or atomic chemical vapor deposition.

[0076] In step 5, a conductive upper electrode 701 is formed on the resistance transition layer 601 of the vertical trench 401.

[0077] As shown in FIG. 9, as a preferred embodiment, the conductive upper electrode 701 may be a multi-layer composite electrode made of one or more of Ti, TiN, Ta, TaN, Ru or Cu, and may be prepared with a thickness of 10 nm-1000 nm by sputtering, atomic chemical vapor deposition or electroplating.

[0078] In step 6, the conductive upper electrode 701, the resistance transition layer 601 and the M.sub.8XY.sub.6 gated layer 501 are planarized to form bit lines of the vertical cross array structure, i.e., forming the self-gated RRAM cell.

[0079] A planarization process may be performed on the conductive upper electrode 701, the resistance transition layer 601 and the M.sub.8XY.sub.6 gated layer 501 by chemical mechanical polishing, completely removing materials of horizontal parts of the conductive upper electrode 701, the resistance transition layer 601 and the M.sub.8XY.sub.6 gated layer 501 to complete patterning of the bit lines, which are particularly shown in FIG. 3.

[0080] Here, the manufacture of the self-gated RRAM unit with the self-gated function, as shown in FIG. 3, has been completed.

[0081] It may be understood that the above implementations are only exemplary implementations for illustrating the principles of the present disclosure, but the present disclosure is not limited to these. For the skilled in the art, various variations and improvements may be made without being apart from the sprit and substance of the present disclosure, which also fall into the protection scope of the present disclosure.