Fault Detection Circuit for a PWM Driver, Related System and Integrated Circuit

Abstract

Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Claims

1. A method of detecting a fault in a PWM signal having a switching period, switch-on duration and switch-off duration, the method comprising: determining a count value that is indicative of a switching period of the PWM signal; testing whether the count value that is indicative of the switching period is between a first threshold and a second threshold; generating an error signal when the switching period is not between the first and the second threshold; determining a count value that is indicative of the switch-on duration of the PWM signal; comparing the count value that is indicative of the switch-on duration with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration; generating a switch-on error signal when the switch-on duration is greater than the maximum switch-on duration; determining a count value that is indicative of the switch-off duration of the PWM signal; comparing the count value that is indicative of the switch-off duration with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration; and generating a switch-off error signal when the switch-off duration is greater than the maximum switch-off duration.

2. The method according to claim 1, wherein determining the count value comprises using a counter to generate a count value, wherein the count value is indicative of the switch-on duration when the PWM signal is high, and wherein the count value is indicative of the switch-off duration when the PWM signal is low.

3. The method according to claim 2, further comprising resetting the counter at each rising edge and each falling edge of the PWM signal.

4. The method according to claim 2, wherein where in the count value is incremented when the PWM signal has a first logic level and decremented when the PWM signal has a second logic level.

5. The method according to claim 4, wherein generating the switch-on error signal comprises comparing the count value with the switch-on threshold, and wherein generating the switch-off error signal comprises comparing the count value with the switch-off threshold.

6. The method according to claim 1, further comprising storing the first threshold, the second threshold, the switch-on threshold, the switch-off threshold in programmable memory.

7. The method according to claim 1, further comprising resetting the count value that is indicative of the switching period once for each PWM cycle of the PWM signal.

8. The method according to claim 7, further comprising receiving a PWM period signal comprising a pulse when a new PWM cycle of the PWM signal starts.

9. The method according to claim 7, wherein the count value that is indicative of the switching period is reset at each rising or each falling edge of the PWM signal.

10. A fault detection circuit for a PWM driver configured to generate a PWM signal having a given switching period, switch-on duration and switch-off duration, the fault detection circuit comprising: a first sub-circuit being configured to: determine a count value that is indicative of a switching period of the PWM signal, test whether the count value that is indicative of the switching period is between a first threshold and a second threshold, and generate an error signal when the switching period is not between the first and the second threshold; and a second sub-circuit being configured to: determine a count value that is indicative of the switch-on duration of the PWM signal, compare the count value that is indicative of the switch-on duration with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration, generate a switch-on error signal when the switch-on duration is greater than the maximum switch-on duration, determine a count value that is indicative of the switch-off duration of the PWM signal, compare the count value that is indicative of the switch-off duration with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration, and generate a switch-off error signal when the switch-off duration is greater than the maximum switch-off duration.

11. The fault detection circuit according to claim 10, wherein the second sub-circuit comprises one counter configured to generate one count value, wherein the one count value is indicative of the switch-on duration when the PWM signal is high, and wherein the one count value is indicative of the switch-off duration when the PWM signal is low.

12. The fault detection circuit according to claim 11, wherein the second sub-circuit comprises a counter reset circuit configured to reset the one counter at each rising edge and each falling edge of the PWM signal.

13. The fault detection circuit according to claim 11, wherein the one counter is an up-and-down counter configured to increase the one count value when the PWM signal has a first logic level and decrease the one count value when the PWM signal has a second logic level.

14. The fault detection circuit according to claim 13, wherein the second sub-circuit comprises: a first comparator configured to generate the switch-on error signal by comparing the one count value with the switch-on threshold; and a second comparator configured to generate the switch-off error signal by comparing the one count value with the switch-off threshold.

15. The fault detection circuit according to claim 10, wherein the first threshold and the second threshold or the switch-on threshold and the switch-off threshold are stored in a programmable memory.

16. The fault detection circuit according to claim 10, wherein the first sub-circuit comprises a counter configured to generate the count value that is indicative of the switching period and a further counter reset circuit configured to reset the counter once for each PWM cycle of the PWM signal.

17. The fault detection circuit according to claim 16, wherein the further counter reset circuit is configured to receive, from the PWM driver, a PWM period signal comprising a pulse when a new PWM cycle of the PWM signal starts.

18. The fault detection circuit according to claim 16, wherein the further counter reset circuit is configured to reset the counter at each rising or each falling edge of the PWM signal.

19. A system comprising: a PWM driver configured to generate a PWM signal having a given switching period, switch-on duration and switch-off duration; and a fault detection circuit configured to determine a count value that is indicative of a switching period of the PWM signal, test whether the count value that is indicative of the switching period is between a first threshold and a second threshold, and generate an error signal when the switching period is not between the first and the second threshold; and determine a count value that is indicative of the switch-on duration of the PWM signal, compare the count value that is indicative of the switch-on duration with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration, generate a switch-on error signal when the switch-on duration is greater than the maximum switch-on duration, determine a count value that is indicative of the switch-off duration of the PWM signal, compare the count value that is indicative of the switch-off duration with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration, and generate a switch-off error signal when the switch-off duration is greater than the maximum switch-off duration.

20. The system according to claim 19, wherein the PWM driver is configured to generate the PWM signal as a function of a control signal, and wherein the system comprises a threshold circuit configured to determine the first threshold, the second threshold, the switch-on threshold, or the switch-off threshold as a function of the control signal.

21. The system according to claim 20, wherein the system further comprises a control unit configured to generate the control signal.

22. The system according to claim 21, wherein the control unit comprises a software programmed microprocessor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

[0040] FIGS. 1, 2 and 3 shows solutions for driving a motor;

[0041] FIG. 4 show a typical PWM signal;

[0042] FIGS. 5a and 5b show typical PWM failures;

[0043] FIGS. 6 and 7 show prior-art solutions for detecting a PWM failure;

[0044] FIG. 8 shows an embodiment of a PWM driver and a respective fault detection circuit comprising two sub-circuits;

[0045] FIG. 9 shows an example of the signals generated by the PWM driver of FIG. 8;

[0046] FIGS. 10 an 11 show an embodiment of the first sub-circuit of the fault detection circuit of FIG. 8;

[0047] FIG. 12 show a first embodiment of the second sub-circuit of the fault detection circuit of FIG. 8;

[0048] FIGS. 13, 14 and 15 show possible embodiments of the second sub-circuit of FIG. 12;

[0049] FIG. 16 show a second embodiment of the second sub-circuit of the fault detection circuit of FIG. 8;

[0050] FIG. 17 show a third embodiment of the second sub-circuit of the fault detection circuit of FIG. 8; and

[0051] FIGS. 18 and 19 show a fourth embodiment of the second sub-circuit of the fault detection circuit of FIG. 8.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0052] In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0053] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0055] In the following FIGS. 8 to 19 parts, elements or components which have already been described with reference to FIGS. 1 to 7 are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

[0056] As mentioned in the foregoing, the present disclosure relates to a fault detection circuit for a PWM signal generator.

[0057] FIG. 8 shows the general architecture of a PWM system in accordance with the present disclosure.

[0058] In the embodiment considered, the system comprises a PWM driver 40 and a fault detection circuit 46.

[0059] In various embodiments, the PWM driver 40 comprise at least a PWM signal generator 400, such as the module 30 described in the foregoing, such as a configurable hardware module or a software programmed microprocessor, generating a PWM signal PWM having a given frequency and duty cycle (see also, the description with respect to FIG. 4).

[0060] In various embodiments, the PWM signal generator 400 is configured to generate a low power PWM signal PWM, e.g., a signal with a maximum voltage between 3.0 and 5 V and maximum current below 100 mA. In this case, the PWM signal generator circuit 40 may also comprise a driver circuit 402 configured to convert the low power PWM signal PWM provided by the circuit 400 in a higher power signal PWM.sub.HP, i.e., a signal having a higher maximum voltage and/or maximum current. For example, in various embodiments, the driver circuit 402 may comprise a half-bridge arrangement 20 (see e.g., FIG. 1).

[0061] In various embodiments, the PWM driver 40, in particular the PWM signal generator 400, is configured to generate the signal PWM as a function of one or more control signals 42 indicating one or more requested characteristics of the signal PWM. For example, in the embodiment considered, the one or more control signals 42 are generated by a control unit 44. For example, these control signal(s) 42 may indicate only the duty cycle or switch-on period T.sub.ON and the switching period T.sub.PWM may be constant. In alternative or in addition, the control signal(s) 42 may indicate the switching period T.sub.PWM. In various embodiments, the control signal(s) 42 may also vary for each PWM cycle.

[0062] For example, in various embodiments considered, the control unit 44 may be a software programmed microprocessor of a microcontroller and the low power signal generator 400 and possibly the driver 402 may be a dedicated hardware module of the same microcontroller. For example, in this case, the operation of the PWM signal generator circuit 40 may be controlled via so called Special Function Registers (SFR) of this microcontroller.

[0063] In the embodiment considered, the system comprises moreover a fault detection circuit 46. In various embodiments, also the fault detection circuit 46 may be a hardware module of the microcontroller comprising the control unit 44 and/or the PWM driver 40.

[0064] In the embodiment considered, the fault detection circuit 46 receives a PWM period signal PS, e.g., a series of pulses with a period equals to the period T.sub.PWM, generated by the PWM driver 40, e.g., by the circuit 400. As shown in FIG. 9, the PWM period signal PS may indicate the start of each PWM cycle or period and may correspond to a pulsed signal being set, e.g., to “high” for one or more clock cycles when a new PWM cycle starts.

[0065] In the embodiment considered, the fault detection circuit 46 receives moreover one of the PWM signals generated by the PWM signal generator 40, such as the low power signal PWM or the high-power signal PWM.sub.HP, e.g., one of the signal IN, DRV.sub.1/DRV.sub.2 or OUT shown in FIG. 1.

[0066] In various embodiments, the PWM period signal PS may be routed internally to the fault detection circuit 46 and the PWM output signal PWM/PWM.sub.HP may be externally routed (e.g., via an external connection of the pins of the microcontroller) to the fault detection circuit 46. Such an external routing may be requested by safety requirements to cover also package faults.

[0067] In various embodiments, the fault detection circuit 46 moreover receives one or more control signals 48 indicating one or more fault detection characteristics. In the embodiment considered, the control signal(s) 48 are generated by a block 50 configured to determine the control signal(s) 48 indicating the fault detection characteristics as a function of the control signal(s) 42 indicating one or more requested characteristics of the PWM signal. For example, the block 50 may be a dedicated hardware module, such as a dedicated hardware model of the microcontroller comprising the control unit 44, or a software module of the control unit 44.

[0068] In various embodiments, the fault detection circuit 46 comprises two submodules 460 and 480. The first submodule 460 is configured to analyses the switching period T.sub.PWM of the signal PWM. Conversely, the second submodule 480 is configured to analyses the switch-on and switch-off periods of the signal PWM.

[0069] FIG. 10 shows a first embodiment of the submodule 460.

[0070] In the embodiment considered, the PWM driver 40, in particular the low power signal generator 400, is driven using a first clock signal CLK.sub.1. Conversely, the submodule 460 is driven using a second clock signal CLK.sub.2. Generally, the clock signals CLK.sub.1 and CLK.sub.2 may also be the same clock signal, e.g., the clock signal of the control unit 44.

[0071] As mentioned in the foregoing, the submodule 460 is configured to analyses the switching period T.sub.PWM of the signal PWM. For this reason, the submodule 460 is configured to determine by means of the signal PS whether the duration of the PWM period is within given limits.

[0072] Specifically, in the embodiment considered, the submodule 460 comprises a digital counter 4600 and a counter reset circuit 4602. More specifically, in the embodiment considered, the counter reset circuit 4602 is configure to generate a reset signal RST adapted to reset the counter 4600 when the signal PS indicates that a new PWM cycle has started. Generally, this circuit 4602 is purely optional, because the signal PS could already correspond to a signal being adapted to reset the counter 4600, such as a signal being set to high only for short period, such as one clock cycle, at the beginning of each PWM cycle. Accordingly, the counter 4600 is configured to vary (i.e., increase or decrease depending on the type of counter used) a count value CNT.sub.1 at each clock event of the clock signal CLK.sub.2 and reset the count value CNT.sub.1 when the signal PS indicates the start of a new PWM cycle.

[0073] In the embodiment considered, the submodule 460 comprises also two comparators 4604 and 4606 configured to compare the count value CNT.sub.1 of the counter 4600 with a first threshold TH.sub.1 and a second threshold TH.sub.2, respectively. For example, these thresholds TH.sub.1 and TH.sub.2 may be stored in respective registers 4608 and 4610, and the content of these registers may be programmed via the block 50 via respective signals 48.sub.1 and 48.sub.2.

[0074] FIG. 11 shows an embodiment of the operation of the submodule 460, wherein a synchronous up-counter 4600 is used. Accordingly, in the embodiment considered, the counter 4600 is configure to reset the count value CNT.sub.1 as a function the signal PS at the beginning of each PWM cycle and then increase the count value CNT.sub.1 in accordance with the clock signal CLK.sub.2. Moreover, when the count value CNT.sub.1 is greater than the threshold TH.sub.1, the comparator 4604 will change the respective output signal CMP.sub.1, e.g., set the output CMP.sub.1 of the comparator 4604 to high. Similarly, when the count value CNT.sub.1 is greater than the threshold TH.sub.2, the comparator 4606 will change the respective output signal.

[0075] As shown in FIG. 11, in case the PWM period is correct, the output of the comparator 4604 should be high and the output of the comparator 4606 should be low when a new PWM cycle starts, i.e., the count value CNT.sub.1 should be greater than the first threshold TH.sub.1, but smaller than the second threshold TH.sub.2. Accordingly, the block 50 should set the content of the registers 4608 and 4610 in order to satisfy these conditions. For example, in various embodiment the block 50 may be configured to set the registers 4608 and 4610 according to the following relations:

T.sub.H=C.sub.PWM.sub._.sub.CLOCK−X.sub.1  (4)

TH.sub.2=C.sub.PWM.sub._.sub.CLOCK+X.sub.2  (5)

where C.sub.PWM.sub._.sub.CLOCK corresponds to the PWM period T.sub.PWM in number of clock cycles of the clock signal CLK.sub.2, and X.sub.1 and X.sub.1 are one or more clock cycle of the same clock representing the tolerance accepted for the PWM period T.sub.PWM.

[0076] Accordingly, when the PWM period is correct, the count value CNT.sub.1 should be between the first threshold TH.sub.1 and the second threshold TH.sub.2 at the end of each PWM cycle, i.e., when the counter 4600 is reset.

[0077] Conversely, when the count value CNT.sub.1 reaches the second threshold TH.sub.2 during a PWM cycle, i.e., before the counter 4600 is reset, the PWM cycle is too long and an error should be created. For example, in the embodiment considered, this may be achieved by using the output of the comparator 4606 as an error signal ERR.sub.2 indicating that the PWM period is too long.

[0078] Conversely, the PWM period is too short, when the count value CNT.sub.1 does not reach the first threshold TH.sub.1 during a PWM cycle, i.e., before the counter 4600 is reset. For example, in the embodiment considered this is achieved by means of a verification circuit 4612, which receives at input the reset signal RST from the counter reset circuit 4602 (or possibly the signal PS) and the comparison signal from the comparator 4604. In particular, this verification circuit 4612 is configured to generate an error signal ERR.sub.1, indicating that the count value CNT.sub.1 was smaller than the first threshold TH.sub.1 when a new PWM period started, i.e., when a new reset of the counter 4600 occurred.

[0079] In various embodiments, once having detected an error, the sub-circuit 460 may store the value of the error signals ERR.sub.1 and/or ERR.sub.2 in a memory, such as register or flip-flop. For example, in various embodiments, each error signal is connected to the set input of a set-reset flip-flop or latch.

[0080] FIG. 12 shows a first embodiment of the submodule 480.

[0081] As mentioned before, the second submodule 480 is configured to analyses the switch-on and switch-off durations of the PWM signal.

[0082] In the embodiment considered, the submodule 480 comprises two circuits 482.sub.ON and 482.sub.OFF configured to determine respectively whether the switch-on and switch-off durations of the PWM period are within given limits.

[0083] In the embodiments considered, the circuit 482.sub.ON and 482.sub.OFF have substantially the architecture of the circuit 460 shown in FIG. 10.

[0084] FIG. 13 shown in this regards a generic circuit 482 which may be used for both circuits 482.sub.ON and 482.sub.OFF. Specifically, also in this case, the circuit 482 comprises a counter 4820 (possibly having associated therewith a counter reset circuit 4822), two comparators 4824 and 4826 (possibly having associated therewith a respective threshold registers 4828 and 4830), and a verification circuit 4832. Specifically, the circuit operate similar to the submodule 460, with the only difference that the counter 4820 is enabled either when the PWM signal is high (for the circuit 482.sub.ON) or when the PWM signal is low (for the circuit 482.sub.OFF).

[0085] Accordingly, similar to the circuit 460, the counter 4820 will be reset at each new PWM period and the counter 4820 will vary (increase or decrease) the count value CNT.sub.2 of the counter 4820 at each clock cycle. However, in this case, the counter 4820 is only enabled when the PWM signal is high (for the circuit 482.sub.ON) or low (for the circuit 482.sub.OFF), i.e., the count value CNT.sub.2 is indicative of the switch-on/switch-off duration of the signal PWM. Accordingly, similar to the circuit 460, this count value may be compared at the comparators 4824 and 4826 with two threshold values TH.sub.3 and TH.sub.4.

[0086] For example, in case of the circuit 482.sub.ON, the comparator 4826 will generate an error signal ERR.sub.4 when the count value CNT.sub.2 is greater than the threshold TH.sub.4, thereby indicating that the switch-on duration was too long. Conversely, the verification circuit 4832 is configured to generate an error signal ERR.sub.3 when the count value CNT.sub.2 was smaller than the first threshold TH.sub.3 and a new PWM period started, thereby indicating that the switch-on duration was too short.

[0087] Similarly, in case of the circuit 482.sub.OFF, the comparator 4826 will generate an error signal ERR.sub.6 when the count value CNT.sub.2 is greater than the threshold TH.sub.4, thereby indicating that the switch-off duration was too long. Conversely, the verification circuit 4832 is configured to generate an error signal ERR.sub.5 when the count value CNT.sub.2 was smaller than the first threshold TH.sub.3 and a new PWM period started, thereby indicating that the switch-off duration was too short.

[0088] Generally, instead of using the PWM period signal PS, the counter reset circuit 4822 may also operate with the signal PWM in order to detect a new PWM period. For example, in this case, the counter reset circuit 4822 may detect the rising edges (or alternatively the falling edges) in the signal PWM in order to reset the counter 4820. This embodiment permits thus to detect spikes in the signal PWM, because such spikes will reset the counter 4820. The same applies also to the counter reset circuit 4602 of the circuit 460. Accordingly, in general, the signal PS is purely optional.

[0089] FIG. 14 shows a second embodiment of the circuit 482, in which the reset signal RST provided by the circuit 4822 corresponds directly to the PWM signal (for the circuit 482.sub.OFF) or to the inverted PWM signal (for the circuit 482.sub.ON). In this case, the counter 4820 does also not require an enable port.

[0090] In fact, as shown in FIG. 15 at the example of the circuit 482.sub.ON, the reset signal will maintain the counter 4820 reset when the PWM signal is low and the counter 4820 will start to count when the signal PWM is high. Accordingly, the verification circuit 4832 may determine whether the comparison signal CMP.sub.2 at the output of the comparator 4824 is set at the next rising edge of the reset signal RST.

[0091] The above embodiments do, however, not take into account that indeed a relationship exists between the switch-on duration and the switch-off duration. In fact, assuming that the duration T.sub.PWM of the PWM cycle is correct (which is already verified by the circuit 460), a too long switch-on duration T.sub.ON (signal ERR.sub.4 is set) will automatically imply a too short switch-off duration T.sub.OFF (signal ERR.sub.5 is set) and similarly a too short switch-on duration T.sub.ON (signal ERR.sub.3 is set) will automatically imply a too long switch-off duration T.sub.OFF (signal ERR.sub.6 is set).

[0092] Accordingly, it is also sufficient to use only one of the circuits 482.sub.ON or 482.sub.OFF or, when using both circuits, the blocks 4824, 4828 and 4832 are redundant.

[0093] In this regards FIG. 16 shows an embodiment of the complete submodule 480 with reduced complexity, in which the blocks 4824, 4828 and 4832 have been removed.

[0094] Accordingly, in the embodiment considered, the submodule 480 comprises two counter 4820.sub.ON and 4820.sub.OFF. The first counter 4820.sub.ON is enabled when the signal PWM is high and reset when the signal PWM is low. As mentioned in the foregoing, this may be achieved by means of an inverter in the counter reset circuit 4822, i.e., the reset signal RST.sub.ON for the counter 4820.sub.ON may correspond to the inverted signal PWM. Conversely, the second counter 4820.sub.OFF is enabled when the signal PWM is low and reset when the signal PWM is high. As mentioned in the foregoing, this may be achieved by using the signal PWM directly as reset signal RST.sub.OFF for the counter 4820.sub.OFF.

[0095] Accordingly, in the embodiment considered, the count value CNT.sub.2,ON of the counter 4820.sub.ON will be indicative of the switch-on duration T.sub.ON and the count value CNT.sub.2,OFF of the counter 4820.sub.OFF will be indicative of the switch-off duration T.sub.OFF.

[0096] In the embodiment considered, the count value CNT.sub.2,ON is compared at a comparator 4826.sub.ON with a threshold TH.sub.ON in order to determine whether the switch-on duration T.sub.ON is too long and the output of the comparator 4826.sub.ON is used as error signal ERR.sub.ON. As mentioned in the forgoing, the threshold TH.sub.ON may be stored in a register 4830.sub.ON, which may be programmable via the module 50 by means of a control signal 48.sub.ON.

[0097] Similarly, the count value CNT.sub.2,OFF may be compared at a comparator 4826.sub.OFF with a threshold TH.sub.OFF in order to determine whether the switch-off duration T.sub.OFF is too long and the output of the comparator 4826.sub.OFF may be used as error signal ERR.sub.OFF. Also in this case, the threshold TH.sub.OFF may be stored in a register 4830.sub.OFF, which may be programmable via the module 50 by means of a control signal 48.sub.OFF.

[0098] This embodiment does, however, not take into account that indeed only one of the counters 4820.sub.ON or 4820.sub.OFF will be enabled at a given time.

[0099] Accordingly, indeed a single counter may be used for the submodule 480.

[0100] FIG. 17 shows a first embodiment of the submodule 480 with a single counter 4800.

[0101] Specifically, in the embodiment considered, the counter 4800 is configured to reset a count value CNT.sub.3 in response to a reset signal RST. Specifically, this reset signal RST is generated by a counter reset circuit 4802 at each rising edge and at each falling edge of the signal PWM. Accordingly, the counter 4802 varies (increases or decreases based on the counter used) the count value CNT.sub.3 until a new rising or falling edge occurs in the signal PWM.

[0102] In the embodiment considered, the count value CNT.sub.3 is provided to a comparator 4806. Specifically, this comparator 4806 is configured to compare, as a function of the value of the signal PWM, the count value CNT.sub.3 either with a switch-on threshold TH.sub.ON (signal PWM is high) or a switch-off threshold TH.sub.OFF (signal PWM is low). For example, in the embodiment considered, the selection is performed by means of a multiplexer 4814. Again, these thresholds may be stored in respective registers 4810.sub.ON and 4810.sub.OFF, which may be programmable via the module 50 by means of control signals 48.sub.ON and 48.sub.OFF.

[0103] Accordingly, when the signal PWM is high, the count value CNT.sub.3 is indicative for the switch-on duration T.sub.ON and the comparator 4806 indicates whether the switch-on duration T.sub.ON is too long, e.g., greater than the threshold TH.sub.ON. Conversely, when the signal PWM is low, the count value CNT.sub.3 is indicative for the switch-off duration T.sub.OFF and the comparator 4806 indicates whether the switch-off duration T.sub.OFF is too long, e.g., greater than the threshold TH.sub.OFF. Accordingly, a simple de-multiplexer 4816 receiving at input the comparison signal provided by the comparator 4806 and driven by means of the signal PWM may be used in order to generate respective error signal ERR.sub.ON and ERR.sub.OFF indicating whether the switch-on duration T.sub.ON or switch-off duration T.sub.OFF are too long, respectively.

[0104] FIG. 18 shows an alternative embodiment of the submodule 480 wherein an up-and-down counter 4800 is used, thereby avoiding the need for multiplexers and de-multiplexers.

[0105] Specifically, in the embodiment considered, the counter 4800 is configured to reset a count value CNT.sub.3 in response to a reset signal RST. Specifically, this reset signal RST is generated by a counter reset circuit 4802 at each rising and each falling edge of the signal PWM. Accordingly, the counter 4800 varies (increases or decreases based on a selection signal) the count value CNT.sub.3 until a new rising of failing edge in the signal PWM occurs. Specifically, the counter 4800 is configure to increase or decreases the count value CNT.sub.3 as a function of the value of the signal PWM. For example, in the embodiment considered, the count value CNT.sub.3 is increased when the signal PWM is high and the count value CNT.sub.3 is decreased when the signal PWM is low.

[0106] In the embodiment considered, the count value CNT.sub.3 is provided to two comparators 4806.sub.ON and 4806.sub.OFF.

[0107] Specifically, the comparator 4806.sub.ON is configured to compare the count value CNT.sub.3 with a switch-on threshold TH.sub.ON, and the comparator 4806.sub.OFF is configured to compare the count value CNT.sub.3 with a switch-off threshold TH.sub.OFF.

[0108] Accordingly, as shown in FIG. 18, when the signal PWM is high, the count value CNT.sub.3 may have a positive value being indicative of the switch-on duration T.sub.ON and the comparator 4806.sub.ON indicates whether the switch-on duration T.sub.ON is too long, i.e., greater than the threshold TH.sub.ON being set to a positive value. Conversely, when the signal PWM is low, the count value CNT.sub.3 may have a negative value being indicative of the switch-off duration T.sub.OFF and the comparator 4806.sub.OFF indicates whether the switch-off duration T.sub.OFF is too long, i.e., smaller than the threshold TH.sub.OFF being set usually to a negative value. Accordingly, in the embodiment considered, the outputs of the comparators 4806.sub.ON and 4806.sub.OFF may be used as error signal ERR.sub.ON and ERR.sub.OFF indicating whether the switch-on duration T.sub.ON or switch-off duration T.sub.OFF are too long, respectively.

[0109] Accordingly, in the embodiment considered, the counter reset circuit 4802 detects the logic level of the signal PWM and, on each logic level change, it resets the counter 4800. Moreover, the signal PWM indicates whether the counter 4800 has to operate as an up-counter or a down-counter, e.g., the counter 4800 may count up if the logic level of the signal PWM is high and count down if the logic level of the signal PWM is low.

[0110] As result, in case of correct operation, the counter 4800 counts as shown in the FIG. 19. If the duration of the switch-on time T.sub.ON of the PWM signal is longer than the expected one, the comparator 4806.sub.ON output changes and a failure is signaled via the signal ERR.sub.ON. Conversely, if the duration of the switch-off time T.sub.OFF of the PWM signal is longer than the expected one, the comparator 4806.sub.OFF output changes and a failure is signaled via the signal ERR.sub.OFF.

[0111] The setting of the thresholds TH.sub.ON and TH.sub.OFF is performed in time by the module 50 by means of control signal 48.sub.ON and 48.sub.OFF, e.g., when the PWM configuration parameters 42 change and/or at the being of a new PWM period. As mentioned in the foregoing, preferably these thresholds are determined as a function of the PWM configuration parameters 42.

[0112] Generally, the proper selection of the thresholds TH.sub.ON and TH.sub.OFF is application dependent. For example, in case the counter 4800 behaves as an up-counter when the signal PWM is high, the module 50 may use the following relations:

TH.sub.ON=C.sub.RES,UP+(C.sub.PWM.sub._.sub.ON,N+X.sub.3)  (6)

TH.sub.OFF=C.sub.RES,DOWN−(C.sub.PWM.sub._.sub.OFF1,N+C.sub.PWM.sub._.sub.OFF1,N−1+X.sub.4)  (7)

where C.sub.RES,UP and C.sub.RES,DOWN are the reset values of the counter 4800 when operating as up-counter or down-counter, respectively, C.sub.PWM.sub._.sub.ON,N, C.sub.PWM.sub._.sub.OFF1,N and C.sub.PWM.sub._.sub.OFF2,N−1 are respectively the switch-on time T.sub.ON of the PWM period N, the initial off-time T.sub.OFF, of the PWM period N and the final off-time T.sub.OFF2 of the PWM period N−1 in number of clock cycle of the clock signal CLK.sub.2, and X.sub.3 and X.sub.4 are one or more clock cycle of the same clock representing the accepted tolerance.

[0113] Similarly, in case the counter 4800 behaves as a down-counter when the signal PWM is high, the module 50 may use the following relations:

TH.sub.ON=C.sub.RES,DOWN−(C.sub.PWM.sub._.sub.ON,N+X.sub.3)  (8)

TH.sub.OFF=C.sub.RES,UP+(C.sub.PWM.sub._.sub.OFF1,N+C.sub.PWM.sub._.sub.OFF1,N−1+X.sub.4)  (9)

[0114] In this case, however, also the inputs of the comparators 4604 and 4606 have to be switched, i.e., the comparator 4604 indicates an error when the count value CNT.sub.3 is smaller than the threshold TH.sub.ON and the comparator 4606 indicates an error when the count value CNT.sub.3 is greater than the threshold TH.sub.OFF.

[0115] In various embodiments, once having detected an error, the sub-circuit 480 may store the values of the error signals ERR.sub.ON and/or ERR.sub.OFF in a memory, such as register or flip-flop. For example, in various embodiments, each error signal is connected to the set input of a set-reset flip-flop or latch.

[0116] Thus, generally, the sub-circuit 480 determines a count value being indicative of the switch-on duration T.sub.ON and a count value being indicative of the switch-off duration T.sub.OFF. For example, the same counter 4800 is used for this purpose in the embodiments shown in FIGS. 17 and 18,

[0117] Next, the sub-circuit 480 compares the count value being indicative of the switch-on duration T.sub.ON with a switch-on threshold TH.sub.ON in order to determine whether the switch-on duration T.sub.ON is greater than a maximum switch-on duration. As mentioned in the foregoing, based on the operation of the counter, the comparison may indeed determine at the circuit level whether the count value is smaller than a maximum threshold value. However, this comparison still determines whether the switch-on duration T.sub.ON is greater than a maximum switch-on duration, and possibly generates an error signal ERR.sub.ON when the switch-on duration T.sub.ON is greater than the maximum switch-on duration.

[0118] Similarly, the sub-circuit 460 compares the value being indicative of the switch-off duration with a switch-off threshold TH.sub.OFF in order to determine whether the switch-off duration T.sub.OFF is greater than a maximum switch-off duration, and possibly generates an error signal ERR.sub.OFF when the switch-off duration T.sub.OFF is greater than the maximum switch-off duration.

[0119] The solutions disclosed herein have thus significant advantages with respect to the known solutions. In fact, similar to the read-back method shown in FIG. 7, the fault detection circuit 460 operates with the real PWM signal, permitting thus a monitoring also of high-power PWM signals. However, the solution directly detects possible PWM failures at most at the end of the PWM cycle, without affecting significantly the overall device size.

[0120] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.