Method and Apparatus for Phase Alignment in Semi-Resonant Power Converters to Avoid Switching of Power Switches Having Negative Current Flow

Abstract

Each phase of a multi-phase voltage converter includes a power stage, passive circuit, synchronous rectification (SR) switch, and control circuit. Each passive circuit couples its power stage to an output node of the voltage converter, and is switchably coupled to ground by the SR switch. The current through the SR switch has a half-cycle sinusoidal shape with a resonant frequency determined by the reactance of the passive circuit. The control circuit generates signals to control switches within the power stage and the SR switches. The control circuit measures current through the SR switch of each phase, and determines which of the phases has SR switch current which returns to zero the quickest. This phase is identified as a master, and the other phases of the voltage converter are aligned to this master phase such that none of the SR switches is turned off when negative current is flowing through it.

Claims

1. A multi-phase voltage converter, comprising: a plurality of phases, each phase comprising: a high-side switch connected between an input voltage terminal and a switching node; a low-side switch connected between the switching node and ground; a passive circuit connecting the switching node to a common output node of the multi-phase voltage converter; and a synchronous rectification (SR) switch connected between the passive circuit and ground and through which a half-cycle sinusoidal-like current is conducted when turned on; and a control circuit operable to: identify, from the plurality of phases having the SR switch through which the half-cycle sinusoidal-like current returns to zero more quickly than the half-cycle sinusoidal-like current returns to zero in the SR switches of other phases of the plurality of phases; and align the phases for a switching cycle based on a switching period of the master phase, so that none of the SR switches turn off at a negative current level.

2. The multi-phase voltage converter of claim 1, wherein the control circuit is operable to identify the master phase during a calibration mode which precedes a normal operational mode of the multi-phase voltage converter.

3. The multi-phase voltage converter of claim 2, wherein the control circuit is operable to measure the current of each phase using a fixed switching frequency in the calibration mode and compare the current measurements to identify the master phase.

4. The multi-phase voltage converter of claim 2, wherein the control circuit is operable to re-enter the calibration mode after a period of normal operation so as to identify a new master phase, the new master phase having the SR switch through which the half-cycle sinusoidal-like current returns to zero more quickly than the half-cycle sinusoidal-like current returns to zero in the SR switches of other phases of the plurality of phases.

5. The multi-phase voltage converter of claim 1, wherein the control circuit is operable to vary the switching period of the master phase from cycle-to-cycle.

6. The multi-phase voltage converter of claim 1, wherein for a present switching cycle, the control circuit is operable to use the switching period of the master phase from an immediately preceding switching cycle as a reference period for aligning the phases in the present switching cycle.

7. The multi-phase voltage converter of claim 6, wherein the control circuit is operable to adjust the reference period responsive to a transient condition at a load coupled to the multi-phase voltage converter so that the phases remain aligned during the transient condition.

8. The multi-phase voltage converter of claim 7, wherein the control circuit is operable to increase the reference period by a first predetermined amount responsive to a step-up transient condition at the load so that the phases remain aligned during the step-up transient condition.

9. The multi-phase voltage converter of claim 7, wherein the control circuit is operable to decrease the reference period by a second predetermined amount responsive to a step-down transient condition at the load so that the phases remain aligned during the step-down transient condition.

10. The multi-phase voltage converter of claim 6, wherein for the present switching cycle, the control circuit is operable to increment a counter at a defined frequency over the reference period for the immediately preceding switching cycle and align the phases based on the counter output and the number of phases.

11. The multi-phase voltage converter of claim 1, wherein for each phase, the passive circuit comprises an LC tank coupled to the switching node of that phase and a center-tapped inductor for coupling the LC tank to an output capacitor of the multi-phase voltage converter, and the SR switch is coupled between the center-tapped inductor and ground.

12. A method of phase alignment for a multi-phase voltage converter, each phase of the multi-phase voltage converter including a high-side switch connected between an input voltage terminal and a switching node, a low-side switch connected between the switching node and ground, a passive circuit connecting the switching node to a common output node of the multi-phase voltage converter, and a synchronous rectification (SR) switch connected between the passive circuit and ground and through which a half-cycle sinusoidal-like current is conducted when turned on, the method comprising: identifying, from the multiple phases of the voltage converter, a master phase having the SR switch through which the half-cycle sinusoidal-like current returns to zero more quickly than the half-cycle sinusoidal-like current returns to zero in the SR switches of other ones of the multiple phases; and aligning the phases for a switching cycle based on a switching period of the master phase, so that none of the SR switches turn off at a negative current level.

13. The method of claim 12, wherein the master phase is identified during a calibration mode that precedes a normal operational Triode of the multi-phase voltage converter.

14. The method of claim 13, wherein identifying the maker phase comprises: measuring the current of each phase at a fixed frequency in the calibration mode; and comparing the current measurements to identify the master phase.

15. The method of claim 13, further comprising: re-entering the calibration mode after a period of normal operation so as to identify a new master phase, the new master phase having the SR switch through which the half-cycle sinusoidal-like current returns to zero more quickly than the half-cycle sinusoidal-like current returns to zero in the SR switches for other ones of the multiple phases.

16. The method of claim 12, wherein the switching period of the master phase is varied from cycle-to-cycle.

17. The method of claim 12, wherein aligning the phases comprises: using the switching period of the master phase from an immediately preceding switching cycle as a reference period for aligning the phases in a present switching cycle.

18. The method of claim 17, further comprising: adjusting the reference period responsive to a transient condition at a load coupled to the multi-phase voltage converter so that the phases remain aligned during the transient condition.

19. The method of claim 18, wherein adjusting the reference period comprises: increasing the reference period by a first predetermined amount responsive to a step-up transient condition at the load so that the phases remain aligned during the step-up transient condition.

20. The method of claim 18, wherein adjusting the reference period comprises: decreasing the reference period by a second predetermined amount responsive to a step-down transient condition at the load so that the phases remain aligned during the step-down transient condition.

21. The method of claim 17, wherein using the switching period of the master phase from the immediately preceding switching cycle as a reference period for aligning the phases in the present switching cycle comprises: incrementing a counter, during the present switching cycle, at a defined frequency over the reference period for the immediately preceding switching cycle; and aligning the phases based on the counter output and the number of phases.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0014] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description that follows.

[0015] FIG. 1 illustrates a block diagram of an embodiment of a multi-phase voltage converter including a control circuit, wherein each phase includes a power stage, a passive circuit, and a synchronous rectification (SR) switch stage.

[0016] FIG. 2 illustrates a circuit diagram of an embodiment for one phase of a voltage converter such as that illustrated in FIG. 1.

[0017] FIG. 3 illustrates voltage and current waveforms as might be generated in one phase of a semi-resonant voltage converter such as that shown in FIG. 1.

[0018] FIG. 4 illustrates a pulse-width-modulated (PWM) waveform as might be used to control a high-side control switch in a variable-frequency voltage converter such as that shown in FIG. 1.

[0019] FIG. 5 illustrates PWM waveforms for controlling the high-side switch in each of multiple phases of a voltage converter such as that of FIG. 1.

[0020] FIG. 6 illustrates PWM waveforms for controlling the high-side switches for each of multiple phases, and waveforms for the current through SR switches for each of multiple phases in a voltage converter such as that of FIG. 1.

[0021] FIG. 7 illustrates PWM waveforms for controlling the high-side switches for each of multiple phases, and waveforms for the current through SR switches for each of multiple phases in a voltage converter such as that of FIG. 1 after the phases have been aligned to a master phase.

[0022] FIG. 8 illustrates PWM waveforms for controlling the high-side switches in a two-phase version of a voltage converter such as that of FIG. 1, and waveforms for the current through the SR switch of a non-master phase, wherein the waveforms have been adjusted, in response to transient load changes, such that negative current through the SR switches is avoided when the SR switches are turned off.

[0023] FIG. 9 illustrates a flow diagram corresponding to a method for identifying a master phase and aligning the phases of a multi-phase voltage converter.

DETAILED DESCRIPTION

[0024] Embodiments described herein provide techniques for aligning the switch timing of power switches within each of the phases in a multi-phase voltage converter, such that synchronous rectification (SR) switches in each phase are not turned off when negative current is flowing through them. The SR switches are included in a power converter topology that includes a transformer/center-tapped inductor (hereinafter referred to simply as a center-tapped inductor), and are used for coupling the center-tapped inductor to ground. Such a topology allows for high voltage-conversion ratios without requiring isolation. Because of its ability to support high voltage-conversion ratios, this topology is particularly appropriate for applications requiring an output power supply that provides a relatively low voltage and a relatively high current. This translates into relatively high current levels flowing through the SR switches including, potentially, negative currents. Such negative currents, particularly if they have a large magnitude, may damage the SR switches. Additionally, such negative currents discharge the capacitor(s) at the output of the voltage converter, thereby leading to reduced efficiency. Hence, negative current flows through the SR switches should be avoided. The techniques described below ensure that the SR switches are turned off when the current flowing through them is zero or positive.

[0025] Various embodiments of multi-phase voltage converter circuits and methods within multi-phase voltage converters will be provided in the following detailed description and the associated figures. The described embodiments provide particular examples for purposes of explanation, and are not meant to be limiting. Features and aspects from the example embodiments may be combined or re-arranged except where the context does not allow this.

[0026] FIG. 1 illustrates an embodiment of a multi-stage voltage converter 100 that is configured to input power from a power source V.sub.IN and output power for driving a load 120. The voltage converter 100 supplies a current I.sub.OUT to the load 120 and to a capacitor C.sub.0 that serves to filter an output voltage V.sub.OUT. The voltage converter of FIG. 1 includes multiple phases 130, 180, 190. Phase 1 (130), which is taken as representative of the multiple phases, is illustrated in block diagram form with the understanding that the other phases would be similarly configured.

[0027] As illustrated, phase 1 (130) includes a passive circuit 134 that couples a powerstage 132 to the voltage converter output V.sub.OUT. The power stage 132 inputs switch control signals HS1.sub.CTRL and LS1.sub.CTRL for controlling switches therein. The switches within the power stage 132 typically require drivers (not shown for ease of illustration). The passive circuit 134 is coupled to a synchronous rectification (SR) switch stage 138, which serves to switchably couple the passive circuit 134 to ground. The SR switch stage 138 includes an SR switch (not shown), which also typically requires a driver (not shown for ease of illustration).

[0028] A control circuit 110 controls the switches of the power stage and the SR switch stage for each of the phases of the voltage converter 100. The control circuit 110 determines a switching frequency for the voltage converter based upon the load requirements, and drives switch control signals (e.g., HS1.sub.CTRL, LS1.sub.CTRL, SR1.sub.CTRL) for each of the phases of the voltage converter 100. These control signals are typically pulse-width-modulated (PWM) waveforms, each of which is driven with a frequency and duty cycle determined by the control circuit 110 based upon the requirements of the load 120. The control circuit 110 includes a load transient detector 115, which will typically input the output voltage V.sub.OUT or a measurement thereof, for purposes of detecting load transients. The switching frequency is variable and changes as the load requirements change.

[0029] The control circuit 110 may be implemented using analog hardware components (such as transistors, amplifiers, diodes, and resistors), may be implemented using processor circuitry including primarily digital components, or may be implemented using a combination of analog hardware components and processor circuitry. The processor circuitry may include one or more of a digital signal processor (DSP), a general-purpose processor, and an application-specific integrated circuit (ASIC). The control circuit 110 may also include memory, e.g., non-volatile memory such as flash, that includes instructions or data for use by processor circuitry. The control circuit 110 inputs several sensor signals (e.g., I.sub.OUT, V.sub.OUT, current measurements for the SR switch stages of each phase) to estimate the power requirements for the load 120 and to otherwise aid in the generation of the switch control signals.

[0030] In order to maintain stability and reduce ripple at the output of the voltage converter 100, the multiple phases of the voltage converter are typically driven using the same switching frequency during a switch cycle of the voltage converter 100. The control circuit 110 determines the load requirements at a given point in time. Based upon these load requirements and, possibly, the switching frequency for the current cycle, the control circuit 110 will determine a switching frequency (and associated time period) for an upcoming (next) cycle. For a given phase of the voltage converter, this upcoming switch frequency (and associated time period) is used to generate the PWM waveforms for each of the switches in the given phase (e.g., HS1.sub.CTRL, LS1.sub.CTRL, SR1.sub.CTRL) for the upcoming switch cycle. Versions of these PWM waveforms that are delayed (staggered) in time are used to drive the switches in the other phases of the voltage converter for the upcoming switch cycle. The control circuit 110 repeats this process for each switch cycle. To further explain this timing, a circuit implementation for a single phase, e.g., phase 1 (130), of the voltage converter 100 will now be described followed by a description of the switch timing used in the single phase. This description will then be extrapolated to multiple phases of the voltage converter 100.

[0031] Techniques for determining the switching frequency and duty cycles based upon the load requirements of a voltage converter are, generally, well-known in the art. Such conventional techniques will not be further elaborated upon herein, in order to avoid obfuscating the unique aspects of the invention, which are described.

[0032] FIG. 2 illustrates a circuit diagram 200 that shows one phase 230 of a voltage converter such as that shown in FIG. 1. The phase circuit 230 is replicated to realize a multi-phase voltage converter such as that of FIG. 1. For ease of illustration, such other phases are not shown in FIG. 2, but it is understood that they exist in a multi-stage voltage converter and that their circuitry is similar or equivalent to the phase circuit 230 that is shown.

[0033] An input voltage V.sub.IN is input to a power stage 232 at a high-side switch Q.sub.HS that is coupled to a low-side switch Q.sub.LS at a switching node V.sub.SW. The low-side switch Q.sub.LS is, in turn, connected to ground. Each of these switches Q.sub.HS, Q.sub.LS is controlled by a respective driver 232a, 232b as shown. The switching node V.sub.SW of the power stage 232 is coupled to a passive circuit 234, which provides an output current I.sub.PH.sub._.sub.OUT and voltage V.sub.OUT to a load 220. The passive circuit 234 includes a resonant tank comprised of a capacitor C.sub.RES and an inductor L.sub.RES. The inductor L.sub.RES may merely be the leakage inductance (e.g., the inherent parasitic inductance of the circuit wiring), or it may be an actual inductor component together with the leakage inductance. Moreover, the inductance represented by L.sub.RES is typically variable, because the inductance value will often vary over temperature. The inductor L.sub.RES is coupled to a transformer/center-tapped inductor 236 having N1 primary-side windings 236a and N2 secondary-side windings 236b. The turns ratio N2/N1 determines the output/input voltage ratio of the center-tapped inductor 236 when it is conducting current, (Conversely, the ratio N1/N2 determines the output/input current ratio of the center-tapped inductor 236.) For the illustrated circuit, a magnetizing inductor L.sub.A is connected across the center-tapped inductor 236. An SR switch stage 238 is connected to the center-tapped inductor 236 and serves to couple its center tap to ground when the SR switch stage 238 is conducting. The SR switch stage 238 includes an SR switch Q.sub.SR, and, typically, a driver 238a that is coupled to a control terminal (e.g., a gate) of the SR switch Q.sub.SR.

[0034] The high-side, low-side, and SR switches Q.sub.HS, Q.sub.LS, Q.sub.SR are shown in FIG. 2 as enhancement-mode metal-oxide semiconductor field-effect transistors (MOSFETs), but other switch devices may be used. For example, junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), or other types of power transistors may be preferred in some applications. The switches of the power stage 232 and of the SR switch stage 238 (e.g., Q.sub.HS, Q.sub.LS, Q.sub.SR) may be integrated on the same semiconductor die, may each be provided on separate dies, or may otherwise be spread across a plurality of semiconductor dies. The drivers for the switches may be integrated on the same semiconductor die(s) as their corresponding switches, or may be provided on separate dies.

[0035] A control circuit 210 generates PWM signals HS.sub.CTRL, LS.sub.CTRL, and SR.sub.CTRL that are coupled to the drivers 232a, 232b, 238a that control the switches Q.sub.HS, Q.sub.LS, Q.sub.SR in the circuit 230 for the illustrated phase. The control circuit 210 determines the frequency and duty cycle of the PWM signals HS.sub.CTRL, LS.sub.CTRL, SR.sub.CTRL so as to meet the power requirements of the load 220. In a semi-resonant voltage converter such as that illustrated in FIG. 2, the high-side and low-side switches Q.sub.HS, Q.sub.LS of the power stage 232 are controlled such that these switches do not conduct at the same time. A typical switching cycle of the voltage converter phase 230 begins with a “dead time” during which none of the switches Q.sub.HS, Q.sub.LS Q.sub.SR are conducting. This is followed by a “T.sub.ON” period during which the high-side switch Q.sub.HS is conducting, but the low-side switch Q.sub.LS and the SR switch Q.sub.SR are not conducting. A “T.sub.OFF” period follows this, during which the high-side switch Q.sub.HS is not conducting, but the low-side switch Q.sub.LS and the SR switch Q.sub.SR are conducting,

[0036] The control circuit 210 includes a load transient detector 215 that functions similarly to the load transient detector 115 of FIG. 1. Additionally, the control circuit 210 inputs a measurement of the current for the SR switch Q.sub.SR using a current sampler 218.

[0037] FIG. 3 illustrates waveforms 300 for the output current I.sub.PH.sub._.sub.OUT from the phase circuit 230, the voltage at the switch node V.sub.SW, and the resonant and magnetizing currents I.sub.RES, I.sub.M of the voltage converter 200 during a switch cycle. At the start of a dead time period DT0, the phase output current I.sub.PH.sub._.sub.OUT and the magnetizing current I.sub.M are at a minimum value I.sub.MIN, which is negative. None of the power switches Q.sub.HS, Q.sub.LS, Q.sub.SR are conducting during the dead time DT0, i.e., the control circuit 210 generates PWM signals HS.sub.CTRL=0, LS.sub.CTRL=0, SR.sub.CTRL=0. The negative current I.sub.MIN charges the output capacitance of the low-side switch Q.sub.LS and causes the switch node voltage V.sub.SW to rise to a level near V.sub.IN during the dead time DT0. At the end of the dead time DT0, the high-side power switch Q.sub.HS is turned on whereas the low-side switch Q.sub.LS and SR switch Q.sub.SR remain off, e.g., by setting HS.sub.CTRL=1, LS.sub.CTRL=0, and SR.sub.CTRL=0 at the end of DT0. This state is maintained for an interval of time denoted “T.sub.ON.” During T.sub.ON, the switch node voltage V.sub.SW is tied to V.sub.IN through the high-side power switch Q.sub.HS, and the phase output current I.sub.PH.sub._.sub.OUT and the magnetizing current I.sub.M of the voltage converter phase 230 rise in a linear manner, e.g., until the magnetizing current I.sub.M reaches a maximum value I.sub.MAX. The magnetizing current I.sub.M associated with the LC tank formed by the resonance capacitor C.sub.RES, the inductor L.sub.RES and the magnetizing inductor L.sub.M accounts for the rise in the phase output current I.sub.PH.sub._.sub.OUT during T.sub.ON. (With the SR switch Q.sub.SR disabled, almost no current flows through the center-tapped inductor 236 meaning that magnetizing current I.sub.M≈I.sub.RES.)

[0038] During the next interval of the switching cycle, denoted as “T.sub.OFF,” the high-side switch Q.sub.HS is turned off, while the low-side switch Q.sub.LS and the SR switch Q.sub.SR are turned on, e.g., by setting HS.sub.CTRL=0, LS.sub.CTRL=1 and SR.sub.CTRL=1. The switch node voltage V.sub.sw drops to and remains at zero during the T.sub.OFF interval, because the switch node V.sub.SW is coupled to ground though the low-side switch Q.sub.LS. Also during the T.sub.OFF interval, a resonance is formed between resonance capacitor C.sub.RES and inductor L.sub.RES, and results in a resonant current I.sub.RES. A portion of this current, i.e., I.sub.PRIM=I.sub.RES−I.sub.M, flows through into the primary-side winding 236a of the center-tapped inductor 236, and leads to a current I.sub.SEC=(N1/N2)*(I.sub.RES−I.sub.M) flowing through the secondary-side winding 236b of the center-tapped inductor 236. The output current I.sub.PH.sub._.sub.OUT of the phase 230 is, thus, the current I.sub.M flowing through the magnetizing inductor L.sub.M minus the current I.sub.SEC flowing through the secondary-side winding 236b, i.e., I.sub.PH.sub._.sub.OUT=I.sub.M−(N1/N2)*(I.sub.RES−I.sub.M)=I.sub.M+(N1/N2)*(I.sub.M−I.sub.RES). If the interval T.sub.OFF is optimized with respect to the resonant frequency, the SR switch Q.sub.SR can be turned off when its current is substantially zero in order to achieve soft-switching of the SR switch Q.sub.SR.

[0039] The current I.sub.PH.sub._.sub.OUT that is output by the voltage converter phase 230 initially rises during T.sub.OFF, as given by I.sub.PH.sub._.sub.OUT=I.sub.M+(N1/N2)(I.sub.M−I.sub.RES), and subsequently falls. This current takes on the shape of the positive half of a sinusoidal cycle. The time instant at which I.sub.RES and I.sub.M are equal represents the point at which current stops flowing through the center-tapped inductor 236, i.e., all of the current I.sub.RES is flowing through the magnetizing inductor L.sub.M. With no current flowing through the primary-side winding 236a of the center-tapped inductor, no current is induced on the secondary-side winding 236b and, hence, no current flows through the SR switch Q.sub.SR. Ideally, both the low-side switch Q.sub.LS and the SR switch Q.sub.SR are turned off at this instant, and the dead time DT1 for the next cycle begins, i.e., the switches Q.sub.HS, Q.sub.LS, Q.sub.SR are all disabled by setting HS.sub.CTRL=0, LS.sub.CTRL=0, and SR.sub.CTRL=0.

[0040] FIG. 4 illustrates a waveform 400 corresponding to the timing of the control signal HS.sub.CTRL for a high-side switch Q.sub.HS such as that shown in FIG. 2. The voltage converter 200 of FIG. 2, and the control circuit 210 therein, use a variable switching frequency to accommodate variations in the power requirements of the load 220. For a given switch cycle k of the voltage converter 200, the control circuit 210 determines a switching period Tsw[k] based upon measurements taken in the previous cycle (k−1). The measurements estimate the load's power requirements by measuring or estimating, e.g., the output voltage V.sub.PUT of the voltage converter 200, For example and as shown in FIG. 4, the switching period Tsw[k] may be a function of an output voltage V.sub.OUT that is measured in cycle (k−1). The switching period Tsw[k] for the current switch cycle may also be based upon the switching period Tsw[k−1] of the previous switch cycle, i.e., the switch period Tsw[k] for the current cycle may be determined by adjusting the switch period Tsw[k−1] from the previous switch cycle (k−1).

[0041] FIG. 5 illustrates an extrapolation of the waveform of FIG. 4, which only considers the control signal for a single phase, for multiple phases of a multi-phase voltage converter. FIG. 5 illustrates waveforms 500 corresponding to high-side control signals HS1.sub.CTRL, HS2.sub.CTRL, . . . HSq.sub.CTRL for multiple phases of an N-phase voltage converter such as the voltage converter 100 of FIG. 1. As similarly described regarding the waveform of FIG. 4, a cycle period Tsw, together with a “T.sub.ON” interval, are determined for a cycle (k−1) based upon measurements during cycle (k−2). This is illustrated by the PWM waveform HS1.sub.CTRL, which represents the control signal for a high-side switch Q.sub.HS included as part of the first phase in the multi-phase voltage converter 100. This first phase may be considered as a “leading” phase, in that the timings for the other phases are driven from this phase. For a typical implementation, the start times for the other (non-leading) phases are evenly distributed throughout the cycle period Tsw[k−1]. Consider, for example, an example in which the voltage converter 100 has three (3) phases, and a cycle of the first (leading) phase begins at time to and has a cycle period of Tsw[k−1]. Then, the control signal HS1.sub.CTRL for the first phase would rise at time to, the control signal HS2.sub.CTRL for the second phase would rise at time t.sub.0+(1/3)*Tsw[k−1], and the control signal HS3.sub.CTRL for the third phase would rise at time t.sub.0+(2/3)*Tsw[k−1]. The other control signals, e.g., for controlling low-side and SR switches, for the non-leading phases, would likewise be delayed versions of the control signals for the leading phase.

[0042] A counter having a clock period of Tclk is used to implement the cycle period Tsw[k−1], and to determine the transition times for the PWM control signals, e.g., HS.sub.CTRL, LS.sub.CTRL, SR.sub.CTRL, for each of the phases in the multi-phase voltage converter 100. For the second phase of the N-phase voltage converter 100, the control signal HS2.sub.CTRL thus rises when the counter equals (1/N)*Tsw[k−1]/Tclk clock periods after the beginning of the switch cycle (k−1). For a q.sup.th phase, a control signal HS.sub.CTRK rises when the counter equals ((q-1)/N)*Tsw[k−1]/Tclk clock periods after the beginning of the switch cycle (k−1). As described thus far, the switch cycle periods Tsw[k−1] are the same for all of the phases (leading and non-leading), but it is possible that the cycle period could by adjusted for the non-leading phases. This may not preferred due to the additional complexity, the limited advantage of this, and the potential for creating additional ripple in the output voltage and/or current.

[0043] FIG. 6 illustrates waveforms 600 associated with an N-phase voltage converter such as that shown in FIG. 1. Waveforms are illustrated for the PWM high-side control signals HS1.sub.CTRL, HS2.sub.CTRL, . . . HSN.sub.CTRL of each phase. Superimposed on these are waveforms corresponding to the currents I.sub.SR1, I.sub.SR2, . . . I.sub.SRN flowing through the SR switches Q.sub.SR for each of the phases. As similarly explained regarding FIG. 5, the high-side control signals HS1.sub.CTRL, HS2.sub.CTRL, . . . HSN.sub.CTRL are staggered such that the signals corresponding to the non-leading phases (phases 2 to N) are delayed versions of the signal for the leading phase (phase 1). This is illustrated for phase 2, wherein the high-side control signal HS2.sub.CTRL for cycle (k−1) has a rising edge that is (1/N)*Tsw[k−1] later in time than the rising edge for the high-side control signal HS1.sub.CTRL for cycle (k−1). Similarly for phase N (the last phase), the high-side control signal HSN.sub.CTRL for cycle (k−1) has a rising edge that is ((N-1)/N)*Tsw[k−1] later than the rising edge for the high-side control signal HS1.sub.CTRL for cycle (k−1). The waveforms 600 of FIG. 6 presume that the switching period for a given cycle, e.g., Tsw[k−1], has been calculated in the preceding cycle, e.g., k−2, and that this switch period may be used both as the switch period and to determine the stagger (delay) times for starting the cycles of the non-leading phases. For ease of explanation, the switch periods illustrated in FIG. 6 do not change for the three (3) illustrated cycles k−1, k, k+1.

[0044] For a given phase, current flows through its SR switch, e.g., Q.sub.SR, when the SR switch is conducting. The PWM control signal SR.sub.CTRL for an SR switch Q.sub.SR determines when that SR switch conducts. As explained in the description of FIG. 3, the PWM control signal SR.sub.CTRL only enables its corresponding SR switch during the off interval (“T.sub.OFF”) of the high-side switch QHs for the phase. In FIG. 6, this corresponds to the time interval when a high-side control signal, e.g., HS1.sub.CTRL, is low.

[0045] The currents flowing through the SR switches take on the shape of the upper half cycle of a sinusoid. This is readily seen in FIG. 6 for the current I.sub.SR1 that flows through the SR switch Q.sub.SR for phase 1 of the voltage converter 100. For each cycle (e.g., k−1, k), the half-cycle sinusoidally-shaped current returns to zero at the beginning of the dead-time interval that immediately precedes the rising edge of the high-side PWM control signal HS1.sub.CTRL. The rising edge of the high-side PWM control signal HS1.sub.CTRL signifies the start of the next cycle (e.g., k, k+1) of the voltage converter 100. (For ease of illustration, the “dead time” is not shown in FIG. 6, but it is understood that the PWM control signal SR1.sub.CTRL would actually disable the current I.sub.SR1 at the start of a dead time interval during which none of the switches are conducting.)

[0046] The control circuit 110 of the voltage converter 100 adjusts the PWM signal timings, e.g., HS1.sub.CTRL, LS1.sub.CTRL, SR1.sub.CTRL, so that the SR switch Q.sub.SR of phase 1 is turned off at approximately the time when the current I.sub.SR1 flowing through this SR switch Q.sub.SR is zero. The control circuit 110 may determine these timings using a measurement/estimation of the current I.sub.SR1 as input to the current sampler 218 illustrated in FIG. 2. The current I.sub.SR1 may be measured by using the effective on-state resistance (R.sub.dson) of the SR switch Q.sub.SR and the voltage across the SR switch Q.sub.SR, or by using a current mirror. The current measurement, for I.sub.SR1 or otherwise, may also be accomplished by using other standard means such as measuring the voltage across a sensing resistor, or by using direct current sensing (DCR) techniques.

[0047] The interval during which the half-cycle sinusoidal current I.sub.SR1 is positive is determined by the components in the passive circuit 234 of the circuit 230 for phase 1 of the voltage converter 200, e.g., the values of the LC resonant tank given by C.sub.RES, L.sub.RFS, the value of the magnetizing inductor L.sub.M, and the inductance of the center-tapped inductor 236. Stated alternatively, the components of the passive circuit 234 have a resonant (natural) frequency that determines the time interval corresponding to the positive half-cycle sinusoidal current I.sub.SR1. While this time interval may be calculated based on the component values, the component values will vary from circuit-to-circuit and, additionally, will vary according to the operating conditions (e.g., temperature) of the voltage converter 100. Hence, an empirical technique that makes use of a measurement of I.sub.SR1, as described above, is preferred.

[0048] Consider, now, the passive circuits (corresponding to the passive circuit 134 of phase 1) for the other phases (e.g., phases 2 to N) of the voltage converter 100. The reactance in the passive circuits for these other phases will differ from those of phase 1, and, hence, will have different resonant (natural) frequencies than the passive circuit 134 of phase 1. This means that the time interval for the half-cycle sinusoidal currents I.sub.SR2, . . . I.sub.SRN will differ from the time interval for I.sub.SR1. This is shown in FIG. 6 where the time interval for the half-cycle sinusoid corresponding to the current I.sub.SR2 through the SR switch Q.sub.SR for phase 2 is longer (slower) than that of phase 1. With the high-side control signal HS2.sub.CTRL of phase 2 being a delayed version of the high-side control signal HS1.sub.CTRL of phase 1, i.e., having the same T.sub.ON and T.sub.OFF intervals, this means that the control signal SR2.sub.CTRL turns off the SR switch Q.sub.SR for phase 2 while positive current I.sub.SR2 is still being conducted. This is illustrated in FIG. 6 for each of the shown cycles k−1, k, k+1.

[0049] For phase N, the interval for the half-cycle sinusoid corresponding to the current I.sub.SRNthrough the SR switch Q.sub.SR is shorter (faster) than that of phase 1. Hence, the control signal SRN.sub.CTRL does not turn off the SR switch Q.sub.SR for phase N until after the current I.sub.SR2 has crossed zero. This means that negative current is being conducted for the interval immediately before the SR switch Q.sub.SR for phase N is turned off, as shown in FIG. 6. As explained previously, it is undesirable to conduct negative current through any of the SR switches Q.sub.SR, e.g., in a direction opposite to the arrow shown in FIG. 2 for ISR.

[0050] By generating PWM control signals HS.sub.CTRL, LS.sub.CTRL, SR.sub.CTRL, and measuring the current through the SR switches Q.sub.SR for each of the phases, the control circuit 110 is able to determine which of the phases are ‘fast’ and which are ‘slow,’ i.e., what the relative resonant frequencies of the different phases are. The control circuit 110 can then re-order (align) its control of the phases in order to avoid negative current flow through any of the SR switches Q.sub.SR.

[0051] FIG. 7 illustrates waveforms 700 corresponding to the high-side PWM control signals HS1.sub.CTRL, HS2.sub.CTRL, . . . HSN.sub.CTRL and the currents I.sub.SR1, I.sub.SR2, . . . I.sub.SRN flowing through the SR switches Q.sub.SR for each of the phases, after the control circuit 110 has aligned (re-ordered) the phases. In one embodiment, the control circuit 110 performs a calibration for the voltage converter 100. This is done by running the voltage converter 100 using all of the phases to drive some load, wherein one phase (e.g., phase 1) is arbitrarily set as a leading phase for the voltage converter 100. In one sub-embodiment, the switching frequency is set to a fixed value for the calibration mode and is not dependent upon any load requirements. During the calibration mode for the first embodiment or its sub-embodiment, the control circuit 110 measures the currents I.sub.SR1, I.sub.SR2, . . . I.sub.SRN through the switches Q.sub.SR for each of the phases, and orders the phases from “fastest,” i.e., the phase having the current I.sub.SR with the shortest half-cycle sinusoid interval, to the “slowest.” The voltage converter 100 subsequently enters a normal operational mode during which the control circuit 110 uses the identified fastest phase as a master phase. The control circuit 110 generates PWM control signals HS.sub.CTRL, LS.sub.CTRL, SR.sub.CTRL, for the master phase, and then generates corresponding delayed versions of these PWM control signals to drive the switches Q.sub.SR of the other (non-master) phases. Using the example waveforms illustrated in FIG. 6, phase N is indicated as being the fastest and, hence, would be chosen as the master phase. This is shown in FIG. 7, where the high-side PWM control signal HSN.sub.CTRL is illustrated as starting each of the cycles k−1, k, k+1. The PWM control signals for the other phases follow those of the master phase, (phase N). Because the non-master phases use the same duty cycles, e.g., T.sub.ON, T.sub.OFF, as the master phase and the time intervals for the half-cycle sinusoidal currents are longer for the non-master phases, the switches Q.sub.SR of the non-master phases are turned off before the currents I.sub.SR1, . . . I.sub.SR2 through them reach or go below zero. Hence, negative current flows through the switches Q.sub.SR are avoided.

[0052] As explained in the first embodiment above, the phase alignment (re-ordering) is performed in a calibration mode that precedes the normal operational mode of the voltage converter 100. In a second embodiment that may be an alternative to or in addition to the first embodiment, the control circuit 110 may align (or re-align) the phase timings after normal operational mode has begun. Such re-aligning may be advantageous when the reactance of the passive circuits 234, etc., varies considerably over time and/or operating condition. For example, inductance values often vary with temperature. The re-alignment may be performed at regular or irregular intervals, e.g., on a periodic basis or whenever the control circuit 110 detects some change in operating condition. Alternatively, the control circuit 110 may constantly monitor the currents I.sub.SR1, I.sub.SR2, . . . I.sub.SRN and whenever a new “fastest” phase is identified, then a re-alignment of the phase timings is performed using the newly-identified fastest phase as the master. In some implementations, it may be desired to only determine a new master phase when a new “fastest” phase is faster than the current master phase by a predetermined threshold. This will prevent excessive re-alignment of the phases which, in addition to added complexity in the control circuit 110, may lead to additional ripple in the output V.sub.OUT of the voltage converter 110.

[0053] Once the master phase is determined and the voltage converter 100 is running in normal operational mode, the control circuit 110 varies the switching period of the master phase from cycle-to-cycle. In order to implement the variable switching frequency, e.g., by adjusting the switch periods, T.sub.ON intervals, and T.sub.OFF intervals for the switch cycles, the control circuit is operable to increment a counter at a defined frequency over the reference period for the immediately preceding switching cycle and to align the phases based on the counter output and the number of phases.

[0054] The prior explanations described a voltage converter in which the switch period Tsw[k] for the master phase has already been determined at the beginning of a cycle k. This determined switch period can be used for setting the T.sub.ON and T.sub.OFF periods within cycle k, as well as for determining the start times for cycles of the non-master phases that follow the timing of the master (leading) phase. In order to more quickly react to load changes, a voltage converter may alter the switch period without waiting until the next start cycle of the master phase. More particularly, the switch period Tsw[k] may be adjusted for non-master phases in the middle of a cycle of the master phase. However, the start of a switch period (e.g., for cycle k) for a non-master phase is based upon the switch period from a previous cycle of the master phase, henceforth denoted as Tsw.sub.m[k−1]. This will now be explained, by way of example, for a 2-phase voltage converter having waveforms as illustrated in FIG. 8.

[0055] FIG. 8 illustrates waveforms 800 associated with a load transient, and will be used for explaining sub-embodiments that avoid switching SR switches off when they have negative currents, as may occur due to load transients. For ease of illustration, the waveforms 800 are shown for a voltage converter having two (2) phases, but it should be understood that the techniques described below are readily extrapolated to voltage converters having more than two phases. The voltage converter generating the waveforms 800 of FIG. 8 may be a 2-phase version of the voltage converter 100 illustrated in FIG. 1. Phase 1 has been previously selected as the master phase, e.g., during a calibration mode, and the current I.sub.SR1 flowing through the SR switch for phase 1 is zero (or nearly zero) when this switch is turned off. The current I.sub.SR2 flowing through the SR switch for phase 2 is slightly positive when this switch is turned off, at least for a steady-state operational period during which there are no load transients.

[0056] A load transient (e.g., a sharp increase in the current required by a load 120 of the voltage converter 100) occurs at an instant of time 810, and is indicated by a drop in the output voltage V.sub.OUT of the voltage converter 100. This may be detected by the load transient detector 115 that monitors the output voltage V.sub.OUT. As illustrated in FIG. 8, the load transient occurs during switching cycle k of phase 1 and phase 2. More particularly, the transient 810 occurs when phase 1 is in the T.sub.OFF interval of cycle k, whereas phase 2 is in the T.sub.ON interval of its cycle k. Note, however, that the described techniques are not restricted to cases in which transients occur with the timing shown in FIG. 8. The techniques are also applicable to other timings including, e.g., cases in which load transients occur during the T.sub.ON interval phase 1 and the T.sub.OFF interval of phase 2.

[0057] The duty cycle (T.sub.ON interval) of the switch period for the 2.sup.nd cycle of phase 2 is increased in response to the load transient. This increase is made so that the voltage converter 100 may supply more power to the load 120. This is shown in FIG. 8 where the T.sub.ON interval of the switch period Tsw.sub.2[k] is seen to increase relative to the T.sub.ON interval of the previous switch period Tsw.sub.2[k−1]. However, the start of the next cycle (k+1) for phase 2 is triggered relative to the previous switch period Tsw.sub.m[k] of the master phase. This means that the phase 2 switch period Tsw.sub.2[k+1] will begin at a point in time that is ½*Tsw.sub.m[k] after the start of the corresponding cycle for phase 1, i.e., the start of Tsw.sub.m[k+1]. The net effect of this is that the switch period Tsw.sub.2[k] is prematurely ended. The SR switch for phase 2 is turned off at a time instant 820 when there is a significant positive current I.sub.SR2 flowing through the switch. This is illustrated in FIG. 8 by the SR switch current I.sub.SR2 during the period denoted “T.sub.OFF NARROW.”

[0058] The next switch period of phase 2, i.e., Tsw.sub.2[k+2], is started at a point in time that is ½*Tsw.sub.m[k+1] after the start of cycle (k+2) for the master phase. The load transient has increased the period for the master phase at cycle (k+1), i.e., Tsw.sub.m[k+1] is longer than the previous period Tsw.sub.m[k]. The net effect of this for phase 2 is that the beginning of the cycle (k+2) is delayed. For cycle (k+1) of phase 2, the switch period Tsw.sub.2[k+1] is too long and, more importantly, has an off interval (denoted by “T.sub.OFF WIDE”) that allows the SR switch current I.sub.SR2 to pass through zero and turn negative before the SR switch is turned off 830.

[0059] The effect of a step-up load transient, as described above, is that a misalignment is created for the non-master phase 2 and, hence, the SR switch Q.sub.SR for phase 2 is switched off when negative current is flowing through it.

[0060] The above problem is mitigated by detecting a step-up load transient, e.g., by using the load transient detector 115 within the control circuit 110 of the voltage converter 100, and adjusting the control signal timing in response to this detection. The resultant waveforms are shown in FIG. 8 beside the label “WITH MODIFICATION” Here, the start of the switch period Tsw.sub.2[k+1] is delayed by a time change denoted “Tx.” This also increases the switch time period Tsw.sub.2[k]. (The resultant periods Tsw.sub.2[k+1] and Tsw.sub.2[k] as denoted as “modified”) As shown, the T.sub.OFF period is thus increased, as denoted by “T.sub.OFF ADJUSTED,” in order to allow adequate time for the SR switch current I.sub.SR2 to decrease further before the SR switch is turned off. Additionally, this delayed start of Tsw.sub.2[k+1] effectively steals “Tx” time from the T.sub.OFF interval at the end of Tsw.sub.2[k+1]. Hence, the T.sub.OFF interval that was previously too wide, as denoted by “T.sub.OFF WIDE,” is now adjusted so that the SR switch current I.sub.SR2 at the time instant 830 is no longer negative. As a result of the modified waveform timings, the SR switch is not turned off while negative current is flowing through it even under transient load conditions.

[0061] The time delta Tx for delaying the start of a next switch cycle (and increasing the time period for a current switch cycle) is preferably set to the difference between the TON intervals for Tsw.sub.2[k] and Tsw.sub.m[k−1]. Alternatively, the time delay Tx could be set to a predetermined value.

[0062] FIG. 8 and the description above address the case of a step-up load transient, and explain how adjustments may be made to maintain phase alignment such that the SR switches in the voltage converter 100 are not turned off when negative current is flowing through them. Conversely, the situation is reversed when a step-down transient is detected. For this case, the start of the next switch cycle for the non-master phase would need to be advanced in time by a time delta Tx. (This is the same as shortening the current switch cycle.) The value for Tx may be given by the difference between the T.sub.ON intervals for Tsw.sub.2[k] and Tsw.sub.m[k−1], or it may be set to a predetermined value.

[0063] FIG. 9 illustrates an embodiment of a method for aligning the phases in a multi-phase voltage converter, such as the voltage converter 100 of FIG. 1. The method may be implemented within a multi-phase voltage converter 100 as illustrated in FIG. 1, and uses techniques similar to those described above regarding the control circuit 110 of the voltage converter 100.

[0064] The method begins by identifying 920 a master phase from among the phases in a voltage converter. This is accomplished by generating control signals, such as PWM signals, to control high-side, low-side, and SR switches for each phase of the voltage converter, using techniques as described previously for the control circuit 110 of FIG. 1, and having waveform timings 600 as shown in FIG. 6. Currents through the SR switches, each of which has a half-cycle sinusoidal shape, are then measured to identify which phase has the SR current that returns to zero the fastest, as illustrated in the waveforms of FIG. 6. The identified phase is determined to be the master phase. The control signal timings for the other phases are then aligned 940 to the timings of the master phase, such that none of the SR switches turn off when the current flowing through them is at a negative level.

[0065] As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0066] It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0067] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.