DML Driver

Abstract

A predriver includes a first transistor for receiving a signal at a gate thereof, a load resistance, a first peaking inductor, a second peaking inductor, a second transistor for receiving a control voltage at a gate thereof, a third transistor for receiving a control voltage at a gate thereof, an inductor for suppressing the group delay, a first peaking capacitor, a second peaking capacitor, and a peaking resistance.

Claims

1-4. (canceled)

5. A DML driver comprising: a first transistor configured to receive a first signal at a gate thereof; a first resistance connected at a first end thereof with a first power supply voltage; a first inductor connected at a first end thereof with a second end of the first resistance and connected at a second end thereof with a drain of the first transistor; a second inductor connected at a first end thereof with the drain of the first transistor and connected at a second end thereof with an input terminal of a post driver to supply a driving current to a laser diode; a second transistor configured to receive a first control voltage at a gate thereof, connected at a source thereof with the first power supply voltage, and connected at a drain thereof with a node between the first resistance and the first inductor; a third transistor configured to receive a second control voltage at a gate thereof, connected at a drain thereof with a source of the first transistor, and connected at a source thereof with a second power supply voltage; a third inductor connected at a first end thereof with a drain of the third transistor and connected at a second end thereof with the second power supply voltage; a first capacitor connected at a first end thereof with a drain of the third transistor and connected at a second end thereof with the second power supply voltage; a second capacitor connected at a first end thereof with a drain of the third transistor; and a second resistance connected at a first end thereof with a second end of the second capacitor and connected at a second end thereof with the second power supply voltage.

6. The DML driver according to claim 5, further comprising a third resistance inserted between the source of the first transistor and the drain of the third transistor.

7. The DML driver according to claim 5, further comprising a third resistance inserted between the drain of the third transistor and the first end of the third inductor.

8. The DML driver according to claim 5, further comprising a fourth transistor inserted between a node between the first and second inductors and the drain of the first transistor to receive a bias voltage at a gate thereof, connected at a drain thereof with the node between the first and second inductors, and connected at a source thereof with the drain of the first transistor.

9. A DML driver comprising: a first transistor configured to receive a first signal at a base thereof; a first resistance connected at a first end thereof with a first power supply voltage; a first inductor connected at a first end thereof with a second end of the first resistance and connected at a second end thereof with a collector of the first transistor; a second inductor connected at a first end thereof with the collector of the first transistor and connected at a second end thereof with an input terminal of a post driver to supply a driving current to a laser diode; a second transistor configured to receive a first control voltage at a base thereof, connected at an emitter thereof with the first power supply voltage, and connected at a collector thereof with a node between the first resistance and the first inductor; a third transistor configured to receive a second control voltage at a base thereof, connected at a collector thereof with an emitter of the first transistor, and connected at an emitter thereof with a second power supply voltage; a third inductor connected at a first end thereof with a collector of the third transistor and connected at a second end thereof with the second power supply voltage; a first capacitor connected at a first end thereof with a collector of the third transistor and connected at a second end thereof with the second power supply voltage; a second capacitor connected at a first end thereof with a collector of the third transistor; and a second resistance connected at a first end thereof with a second end of the second capacitor and connected at a second end thereof with the second power supply voltage.

10. The DML driver according to claim 9, further comprising a third resistance inserted between the emitter of the first transistor and the collector of the third transistor.

11. The DML driver according to claim 9, further comprising a third resistance inserted between the collector of the third transistor and the first end of the third inductor.

12. The DML driver according to claim 9, further comprising a fourth transistor inserted between a node between the first and second inductors and the collector of the first transistor to receive a bias voltage at a base thereof, connected at a collector thereof with the node between the first and second inductors, and connected at an emitter thereof with the collector of the first transistor.

13. A method of arranging a DML driver, the method comprising: providing a first transistor comprising a gate at which a first signal is received; connecting a first end of a first resistance with a first power supply voltage; connecting a first end of a first inductor with a second end of the first resistance and connecting a second end of the first inductor with a drain of the first transistor; connecting a first end of a second inductor with the drain of the first transistor and connecting a second end of the second inductor with an input terminal of a post driver to supply a driving current to a laser diode; connecting a source of a second transistor with the first power supply voltage and connecting a drain of the second transistor with a node between the first resistance and the first inductor, wherein the second transistor comprises a gate at which a first control voltage is received; connecting a drain of a third transistor with a source of the first transistor and connecting a source of the third transistor with a second power supply voltage, wherein the third transistor comprises a gate at which a second control voltage is received; connecting a first end of a third inductor with a drain of the third transistor and connecting a second end of the third inductor with the second power supply voltage; connecting a first end of a first capacitor with a drain of the third transistor and connecting a second end of the first capacitor with the second power supply voltage; connecting a first end of a second capacitor with a drain of the third transistor; and connecting a first end of a second resistance with a second end of the second capacitor and connecting a second end of the second resistance with the second power supply voltage.

14. The method according to claim 13, further comprising inserting a third resistance between the source of the first transistor and the drain of the third transistor.

15. The method according to claim 13, further comprising inserting a third resistance between the drain of the third transistor and the first end of the third inductor.

16. The method according to claim 13, further comprising: inserting a fourth transistor between a node between the first and second inductors and the drain of the first transistor to receive a bias voltage at a gate thereof; connecting a drain of the fourth transistor with the node between the first and second inductors; and connecting a source of the fourth transistor with the drain of the first transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a circuit diagram showing a configuration of a DML driver in accordance with an embodiment of the present invention.

[0011] FIG. 2 is a view showing the parasitic capacitances of a post driver and a predriver of FIG. 1.

[0012] FIG. 3 is a view for illustrating the effect of the DML driver in accordance with an embodiment of the present invention.

[0013] FIG. 4 is a view for illustrating the effect of the equalizer adjusting function of the DML driver in accordance with an embodiment of the present invention.

[0014] FIG. 5 is a view showing the optical output waveform of a LD single body.

[0015] FIG. 6 is a view showing the optical output waveform in the case where the DML driver in accordance with an embodiment of the present invention and the LD are merged.

[0016] FIG. 7 is a circuit diagram showing the configuration of a DML driver in accordance with another embodiment of the present invention.

[0017] FIG. 8 is a circuit diagram showing the configuration of a DML driver in accordance with another embodiment of the present invention.

[0018] FIG. 9 is a circuit diagram showing the configuration of a DML driver in accordance with another embodiment of the present invention.

[0019] FIG. 10 is a view showing the EO response characteristic and the group delay characteristic of a LD.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

First Embodiment

[0020] Below, embodiments of the present invention will be described by reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a configuration of a DML driver in accordance with an embodiment of the present invention. The DML driver of the present embodiment includes a post driver 2 for supplying a driving current I.sub.LD to a LD 1, and a predriver 3 for driving the post driver 2 in response to an inputted modulation signal V.sub.in.

[0021] The post driver 2 is assumed to be a driver including a transistor (not shown), and capable of driving the LD 1. In embodiments of the present invention, to the post driver 2, a driver circuit with a given configuration is applicable.

[0022] The predriver 3 has an equalizer function of suppressing the group delay in the vicinity of the relaxation oscillation frequency f.sub.r of the LD 1, and a peaking function of performing improvement of the band. Specifically, the predriver 3 includes an NMOS transistor M.sub.1n for receiving a modulation signal V.sub.in at the gate, a load resistance R.sub.1 connected at one end thereof with a power supply voltage V.sub.1 (first power supply voltage), a peaking inductor L.sub.1 connected at one end thereof with the other end of the load resistance R.sub.1, and connected at the other end thereof with the drain of the transistor M.sub.1n, a peaking inductor L.sub.2 connected at one end thereof with the drain of the transistor M.sub.1n, and connected at the other end thereof with the input terminal of the post driver 2, a PMOS transistor M.sub.1p for receiving a control voltage V.sub.con_p (first control voltage) at the gate thereof, connected with the power supply voltage V.sub.1 at the source thereof, and connected with the node between the load resistance R.sub.1 and the peaking inductor L.sub.1 at the drain thereof, an NMOS transistor M.sub.xn for receiving a control voltage V.sub.con_n (second control voltage) at the gate, connected with the source of the transistor M.sub.1n at the drain thereof, and connected with a grounding voltage GND (a second power supply voltage lower than the first power supply voltage) at the source, an inductor L.sub.x for suppressing the group delay connected at one end thereof with the drain of the transistor M.sub.xn, and connected at the other end thereof with the grounding voltage GND, a peaking capacitor C.sub.x connected at one end thereof with the drain of the transistor M.sub.xn, and connected at the other end thereof with the grounding voltage GND, a peaking capacitor C.sub.y connected at one end thereof with the drain of the transistor M.sub.xn, and a peaking resistance R.sub.x connected at one end thereof with the other end of the peaking capacitor C.sub.y, and connected at the other end thereof with the grounding voltage GND.

[0023] FIG. 2 is a view showing the parasitic capacitances of the post driver 2 and the predriver 3 shown in FIG. 1. C.sub.1 is the parasitic capacitance of the transistor M.sub.1n, and C.sub.2 is the parasitic capacitance of the transistor (not shown) of the input part of the post driver 2. The parasitic capacitance C.sub.1 is the parasitic capacitance between drain-source when the transistor M.sub.1n is a FET, and is the parasitic capacitance between collector-emitter when the transistor M.sub.1n is a bipolar transistor. When the transconductance of the transistor M.sub.1n is set at g.sub.m, the gain Av of the predriver 3 can be expressed by Equation (1) using the following Laplace function.

[00001]$\begin{array}{cc}\mathrm{Equation}\left(1\right)& \\ .Math.A_v\left(s\right).Math.=\frac{C_{x}s+\frac{1}{L_{x}s}+\frac{1}{R_x+\frac{1}{C_{y}s}}}{C_{2}s+\frac{1}{L_{2}s+\frac{1}{C_{1}s+\frac{1}{R_1+L_{1}s}}}}{g}_m& \left(1\right)\end{array}$

[0024] The s in Equation (1) is the Laplace operator. The part 30 of FIG. 2 including the load resistance R.sub.1 and the peaking inductors L.sub.1 and L.sub.2 forms the peaking function part. At the peaking function part 30, the larger the values of the load resistance R.sub.1 and the peaking inductors L.sub.1 and L.sub.2 are, the larger the peaking amount of the EO response characteristic becomes. Further, the smaller the parasitic capacitances C.sub.1 and C.sub.2 are, the larger the peaking amount becomes.

[0025] Further, for the load impedance between V.sub.1-L.sub.1, the PMOS transistor M.sub.1p is connected in parallel with the load resistance R.sub.1. When the control voltage V.sub.con_p to be inputted to the gate of the PMOS transistor M.sub.1p is increased, the transistor M.sub.1p is put in an OFF state, and the load impedance becomes R.sub.1. Conversely, when the control voltage V.sub.con_p is decreased, the transistor M.sub.1p is put in an ON state, and the load impedance becomes the impedance value in parallel with the ON resistance of the transistor M.sub.1p and the load resistance R.sub.1, and becomes a smaller value than R.sub.1. In other words, it becomes possible to adjust the peaking amount of the EO response characteristic by the control voltage V.sub.con_p.

[0026] The part 31 of FIG. 2 including the inductor L.sub.x forms the group delay suppressing function part. The inductor Lx can suppress the peak of the group delay amount in the vicinity of the relaxation oscillation frequency f.sub.r of the LD 1.

[0027] The part 32 of FIG. 2 including the peaking capacitors C.sub.x and C.sub.y and the peaking resistance R.sub.x forms the peaking function part in the high region. The peaking function part 32 can suppress the reduction of the group delay amount of the LD 1 in the high region and the reduction of the group delay amount of the inductor L.sub.x.

[0028] Further, the control voltage V.sub.con_n to be inputted to the gate of the NMOS transistor M.sub.x connected in parallel with the peaking capacitor C.sub.x can adjust the peaking amount in the high region of the EO response characteristic. For example, when the control voltage V.sub.con_n is decreased, the transistor M.sub.x is put into an OFF state, resulting in a high impedance between drain-source of the transistor M.sub.xn. Whereas, when the control voltage V.sub.con_n is increased, the transistor M.sub.xn is put into an ON state, resulting in a low impedance between drain-source of the transistor M.sub.xn.

[0029] When a high impedance is caused between drain-source of the transistor M.sub.xn, the impedance in parallel with the transistor M.sub.xn and the capacitor C.sub.x is also increased. For this reason, the peaking amount in the high region by the peaking function part 32 is suppressed. Conversely, when a low impedance is caused between drain-source of the transistor M.sub.xn, the impedance in parallel with the transistor M.sub.xn and the capacitor C.sub.x is also reduced, resulting in an increase in peaking amount in the high region.

[0030] The peaking function parts 30 and 32 and the group delay suppressing function part 31 can implement the equalizer function. Even when a difference is caused in frequency characteristic among individual LD 1's, the adjustment of the control voltages V.sub.con_n and V.sub.con_p can adjust the equalizer according to each individual LD 1.

[0031] FIG. 3 is a view for illustrating the effect of the DML driver of the present embodiment. Line 100 in graph (a) of FIG. 3 represents the EO response characteristic of the LD 1 single body, and line 101 represents the EO response characteristic of the combination of the DML driver and the LD 1 of the present embodiment. Line 102 represents the transmission characteristic in the injection current I.sub.LD to the LD 1. Further, line 103 in graph (b) of FIG. 3 represents the group delay characteristic of the LD 1 single body, and line 104 represents the group delay characteristic of the combination of the DML driver and the LD 1 of the present embodiment.

[0032] The peaking function parts 30 and 32 and the group delay suppressing function part 31 can improve the band of the EO response characteristic without increasing the resonant peak of the EO response characteristic as shown in FIG. 3. This enables suppression of the group delay as shown in FIG. 3.

[0033] FIG. 4 is a view for illustrating the effect of the equalizer adjusting function of the DML driver of the present embodiment. Line 200 of FIG. 4 represents the EO response characteristic of the combination of the DML driver and the LD 1 when the control voltages V.sub.con_p and V.sub.con_n are set at given voltage values, respectively. Lines 201 and 202 of FIG. 4 represent the EO response characteristics of the combination of the DML driver and the LD 1 when the control voltage V.sub.con_p is decreased and the control voltage V.sub.con_n is increased relative to the case of line 200. Line 203 of FIG. 4 represents the EO response characteristic of the combination of the DML driver and the LD 1 when the control voltage V.sub.con_p is increased and the control voltage V.sub.con_n is decreased relative to the case of line 200. FIG. 4 indicates that the adjustment of the control voltages V.sub.con_p and V.sub.con_n can adjust the peaking amount as described up to this point.

[0034] FIG. 5 is a view showing the results determined by simulating the optical output waveform of the LD 1 single body. FIG. 6 is a view showing the results determined by simulating the optical output waveform when the DML driver of the present embodiment and the LD 1 are combined. FIGS. 5 and 6 indicate that the eye opening is improved by the DML driver of the present embodiment.

Second Embodiment

[0035] A second Embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing a configuration of a DML driver in accordance with the second embodiment of the present invention, where the same configuration as that of FIG. 1 is given the same reference numerals and signs. The DML driver of the present embodiment includes a post driver 2 and a predriver 3a.

[0036] The predriver 3a of the present embodiment includes a resistance R.sub.add inserted between the source of the transistor M.sub.1n and the drain of the transistor M.sub.xn in the predriver 3 of the first embodiment. Thus, in the present embodiment, the linearization function can be added to the predriver 3a. When the post driver 2 also has the linearization function, it becomes possible to drive the LD 1 even when the signal V.sub.in to be inputted to the predriver 3a is a signal required to have linearity such as a PAM (Pulse Amplitude Modulation) signal or a DMT (Discrete MultiTone) signal.

Third Embodiment

[0037] A third embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a DML driver in accordance with the third embodiment of the present invention, where the same configuration as that of FIG. 1 is given the same reference numerals and signs. The DML driver of the present embodiment includes a post driver 2 and a predriver 3b.

[0038] The predriver 3b of the present embodiment includes a resistance R.sub.add inserted between the drain of the transistor M.sub.xn and one end of the inductor L.sub.x in the predriver 3 of the first embodiment. In the present embodiment, as compared with the configuration of the second embodiment, it is possible to reduce the impedance added to the source of the transistor M.sub.1n in the high region, and it is possible to increase the gain of the driver. For this reason, it becomes possible to improve the frequency band.

Fourth Embodiment

[0039] A fourth embodiment of the present invention will be described. FIG. 9 is a circuit diagram showing the configuration of a DML driver in accordance with the fourth embodiment of the present invention, where the same configuration as that of FIG. 1 is given the same reference numerals and signs. The DML driver of the present embodiment includes a post driver 2 and a predriver 3c.

[0040] The predriver 3c of the present embodiment includes an NMOS transistor M.sub.2n, in which a direct-current bias voltage V.sub.2 is inputted to the gate, the drain is connected with the node of the inductors L.sub.1 and L.sub.2, and the source is connected with the drain of the transistor M.sub.1n, inserted in the predriver 3 of the first embodiment. The bias voltage V.sub.2 is desirably set so that the transistors M.sub.1n and M.sub.2n operate in the saturation region.

[0041] In the present embodiment, the transistors M.sub.1n and M.sub.2n are connected in a cascode type, which can suppress the mirror effect in the transistor M.sub.1n. For this reason, it is possible to further improve the frequency characteristic of the DML driver.

[0042] Incidentally, in the first to fourth embodiments, the examples were shown in which a FET was used as the transistor M.sub.1n, M.sub.2n, M.sub.xn, or M.sub.1p. However, it is also acceptable that a NPN bipolar transistor is used as the transistor M.sub.1n, M.sub.2n, or M.sub.xn, and a PNP bipolar transistor is used as the transistor M.sub.1p. When a bipolar transistor is used, in the description in the first to fourth embodiments, it is essential only that the gate is replaced with the base, the drain is replaced with the collector, and the source is replaced with the emitter.

INDUSTRIAL APPLICABILITY

[0043] Embodiments of the present invention are applicable to the technology of directly modulating the optical output of a LD.

REFERENCE SIGNS LIST

[0044] 1 Laser diode [0045] 2 Post driver [0046] 3, 3a, 3b, 3c Predriver [0047] M.sub.1n, M.sub.2n, M.sub.xn, M.sub.1p Transistor [0048] R.sub.1, R.sub.x, R.sub.add Resistance [0049] L.sub.1, L.sub.2, L.sub.x Inductor [0050] C.sub.x, C.sub.y Capacitor [0051] 30, 32 Peaking function part [0052] 31 Group delay suppressing function part