Logic Gate Device

Abstract

A logic gate device comprising a probe structure having an interface contact, a first logic input for receiving a first light pulse having a first carrier-envelope phase that encodes an input state of the first logic input and a second logic input for receiving a second light pulse having a second carrier-envelope phase that encodes an input state of the second logic input. The probe structure is arranged to be irradiated by the first light pulse to generate a first current component within the probe structure that depends on the first carrier-envelope phase and to be irradiated by the second light pulse to generate a second current component within the probe structure that depends on the second carrier-envelope phase. The interface contact is arranged to output a sum current that comprises the first and second current component, wherein the sum current encodes a logic output state of a logic output.

Claims

1. A logic gate device comprising a probe structure having an interface contact, a first logic input for receiving a first light pulse having a first carrier-envelope phase φ.sub.A that encodes an input state of the first logic input and a second logic input for receiving a second light pulse having a second carrier-envelope phase φ.sub.B that encodes an input state of the second logic input, wherein the probe structure is arranged to be irradiated by the first light pulse in a first interaction region to generate a first current component within the probe structure that depends on the first carrier-envelope phase φ.sub.A, wherein the second logic input is arranged to be irradiated by the second light pulse in a second interaction region to generate a second current component within the probe structure that depends on the second carrier-envelope phase φ.sub.B, wherein the interface contact is arranged to output a sum current that comprises the first and second current component, wherein the sum current encodes a logic output state of a logic output of the logic gate device.

2. The logic gate device according to claim 1, wherein the input state of the first logic input is encoded in a phase value of the first carrier-envelope phase φ.sub.A that causes the first light pulse to generate the first current component due to a net polarization of virtual charge carriers within the probe structure.

3. The logic gate device according to claim 1, wherein the input state of the second logic input is encoded in a phase value of the second carrier-envelope phase φ.sub.B that causes the second light pulse to generate the second current component due to a net momentum of real charge carriers within the probe structure.

4. The logic gate device according to claim 1, wherein the input state of the second logic input is encoded in a phase value of the second carrier-envelope phase φ.sub.B that causes the second light pulse to generate the second current component due to a net polarization of virtual charge carriers within the probe structure.

5. The logic gate device according to claim 1, wherein the first interaction region is at least partly separate from the second interaction region.

6. The logic gate device according to claim 1, wherein the first interaction region encompasses a boundary region between the probe structure and the interface contact.

7. The logic gate device according to claim 1, wherein the second interaction region is separate from a boundary region between the probe structure and the interface contact.

8. The logic gate device according to claim 1, wherein the first current component is generated having a first lifetime that is smaller than a second lifetime of the second current component, wherein the probe structure is arranged to be irradiated with at least one additional first light pulse received via the first logic input during the second lifetime, wherein the additional first light pulse generates an additional first current component within the probe structure, wherein the interface contact is arranged to output an additional sum current that comprises the additional first current component and the second current component, wherein the additional sum current encodes an additional logic output state of the logic output of the logic gate device.

9. The logic gate device according to claim 1, wherein the probe structure has a smaller extent in a height direction than in a transverse direction, the height direction being orientated perpendicular to the transverse direction, wherein the interface contact is positioned at a lateral side of the probe structure, the lateral side limiting the probe structure in the transverse direction.

10. The logic gate device according to claim 9, wherein the first interaction region and the second interaction region are located next to each other in the transverse direction.

11. The logic gate device according to claim 1, wherein the probe structure comprises a material having a conduction and a valence band.

12. The logic gate device according to claim 11, wherein the probe structure is a graphene structure.

13. The logic gate device according to claim 1, wherein the first and/or second light pulses are laser pulses.

14. The logic gate device according to claim 1, wherein the first and/or second light pulses are free-space laser pulses.

15. The logic gate device according to claim 1, wherein the sum current encodes a first output state of the logic output for the sum current being larger than a predetermined threshold current, wherein the sum current encodes a second output state of the logic output for the sum current being at most equal to a predetermined threshold current.

16. Optoelectronic system comprising a logic gate device, the logic gate device comprising a probe structure having an interface contact, a first logic input for receiving a first light pulse having a first carrier-envelope phase φ.sub.A that encodes an input state of the first logic input and a second logic input for receiving a second light pulse having a second carrier-envelope phase φ.sub.B that encodes an input state of the second logic input, wherein the probe structure is arranged to be irradiated by the first light pulse in a first interaction region to generate a first current component within the probe structure that depends on the first carrier-envelope phase φ.sub.A, wherein the second logic input is arranged to be irradiated by the second light pulse in a second interaction region to generate a second current component within the probe structure that depends on the second carrier-envelope phase φ.sub.B, wherein the interface contact is arranged to output a sum current that comprises the first and second current component, wherein the sum current encodes a logic output state of a logic output of the logic gate device, the optoelectronic system further comprising a first light source for generating the first light pulse and a second light source for generating the second light pulse, and a control device for controlling the first and second light source, wherein the control device is configured to control the first light source to generate the first carrier-envelope phase φ.sub.A in dependence on the input state of the first logic input and to control the second light source to generate the second carrier-envelope phase φ.sub.B in dependence on the input state of the second logic input.

17. Method for implementing a logic gate, the method comprising: providing a first light pulse having a first carrier-envelope phase, the first carrier-envelope phase encoding an input state of a first logic input, providing a second light pulse having a second carrier-envelope phase, the second carrier-envelope phase encoding an input state of a second logic input, irradiating a probe structure with the first light pulse in a first interaction region to generate a first current component within the probe structure that depends on the first carrier-envelope phase, irradiating the probe structure with the second light pulse in a second interaction region to generate a second current component within the probe structure that depends on the second carrier-envelope phase. outputting a sum current that comprises the first and second current component, wherein the sum current encodes a logic output state of a logic output of the logic gate device.

Description

[0080] Exemplary embodiments and functions of the present disclosure are described herein in conjunction with the following drawings, showing schematically:

[0081] FIG. 1 a logic gate device according to the present disclosure;

[0082] FIG. 2 a top view of a probe structure of the logic gate device;

[0083] FIG. 3 excitation of virtual charge carriers:

[0084] FIG. 4 a vector potential and an electric field of a light pulse having a carrier-envelope phase of 0 rad;

[0085] FIG. 5 a band structure of the probe structure and excitation of real charge carriers:

[0086] FIG. 6 a vector potential and an electric field of a light pulse having a carrier-envelope phase of π/2 rad;

[0087] FIG. 7 carrier-envelope phase values, current components and output states for a NOR gate;

[0088] FIG. 8 carrier-envelope phase values, current components and output states for a NAND gate;

[0089] FIG. 9 carrier-envelope phase values, current components and output states for an OR gate;

[0090] FIG. 10 carrier-envelope phase values, current components and output states for an AND gate:

[0091] FIG. 11 an experimental setup to demonstrate formation of a first and second current component within the probe structure;

[0092] FIG. 12 measured values of amplitudes and phases of a sum current within the probe structure;

[0093] FIG. 13 a demodulated dependence of the sum current on a relative phase difference and a global phase shift of carrier-envelope phases of two light pulses;

[0094] FIG. 14 the sum current in dependence of a first carrier-envelope phase of a first light pulse and a second carrier-envelope phase of a second light pulse;

[0095] FIG. 15 a method for implementing a logic gate according to the present disclosure.

[0096] FIG. 1 depicts a logic gate device 1 according to the present disclosure. The logic gate device 1 comprises a probe device 100 having a probe structure 110 that is placed on a substrate 140. FIG. 2 depicts the probe device 100 in a top view parallel to a height direction 101.

[0097] The probe structure 110 is configured as a photoconductor and made from monolayer graphene that is epitaxially grown from the substrate 140, which is a 4H-Silicon Carbide (SiC) substrate. As can be seen from FIG. 2, the probe structure 110 has an extent 106 in a transverse direction 102 that is larger than an extent 107 in a further transverse direction 103, wherein the transverse direction 102 and the further transverse direction 103 are orientated perpendicular to each other and perpendicular to the height direction 101. Thereby, the extent 106 in the transverse direction 102 is 5 μm and the extent 107 in the further transverse direction 103 is 1.8 μm.

[0098] At a lateral side 110, which delimits the probe structure 110 in the transverse direction 102, the probe structure 110 is connected to a first interface contact 120, which is configured as a gold structure. The first interface contact 120 constitutes a logic output 152 of the logic gate device 1. A second interface contact 122, which is also a gold structure, is located at an opposite side of the probe structure 110 along the transverse direction 102. The first and second interface contact 120, 122 have a height of 30 nm in the height direction 101. As can be seen from FIG. 1, the first interface contact 120 is connected to a measurement device 150 and the second interface contact 122 is connected to ground.

[0099] A control device 200 comprises a first light source 210 and a second light source 220. The first light source 210 irradiates first light pulses 212 via a first logic input of the logic gate device 1 into a first interaction region 130 and the second light source 220 irradiates second light pulses 222 via a second logic input 12 of the logic gate device 1 into a second interaction region 132. As can be seen from FIG. 2, the first interaction region 130 is located in a boundary region 125 at the boundary between the first interface contact 120 and the probe structure 110. The second interaction region 132 is placed in a bulk region of the probe structure 110, which is separated from the boundary region 125.

[0100] The interaction regions 130, 132 are defined by the transverse dimensions of the light pulses 212, 222 in a plane spanned by the transverse directions 102, 103 at the probe structure 110. Thereby, the first interaction region 130 has a size 131 along the transverse direction 102 and the second interaction region 132 has a size 133 along the transverse direction 102, wherein each size 131, 133 amounts to 3.6 μm. A separation 139 between the first and second interaction region 130, 132 is 2.5 μm. Thereby, the sizes 131, 133 are given by the 1/e.sup.2 intensity radii of the light pulses 212, 222.

[0101] The first light pulses 212 encode input states of the first logic input 10 in their carrier-envelope phases and the second light pulses 222 encode input states of the second logic input 12 in their carrier-envelope phases. Exemplarily, the control device 200 is configured to receive the input states to be encoded in the carrier-envelope phases of the first light pulses 212 via a first control input 201 and to receive the input states to be encoded in the carrier-envelope phases of the second light pulses 222 via a second control input 202. The control device 200 then adjusts the carrier-envelope phases of the first light pulses 212 based on the input states received via the first control input 201 and the carrier-envelope phases of the second light pulses 222 based on the input states received via the second control input 202.

[0102] The first and second logic inputs 10, 12 are each configured as binary inputs and the corresponding input states may each assume a first input state, which corresponds to a logic 0, and a second input state, which corresponds to a logic 1. At least one of the two input states of the first logic input 10 are encoded in a carrier-envelope phase value of the first light pulse 212 that generates a non-zero current component within the first interaction region 130 of the probe structure 110. Likewise, at least one of the two input states of the second logic input 12 are encoded in a carrier-envelope phase value of the second light pulse 222 that generates a non-zero current component within the second interaction region 132 of the probe structure 110.

[0103] With the logic gate device 1, the non-zero current components within the first interaction region 130 are generated due to a net polarization of virtual charge carriers that are excited by first light pulses 212 that have a carrier-envelope phase of 0 rad or π rad. The excitation of virtual charge carriers is schematically shown in FIG. 3, while FIG. 4 depicts the time evolution of a corresponding first light pulse 212 with a carrier-envelope phase value of 0 rad.

[0104] As can be seen from FIG. 4 for a carrier-envelope phase of 0 rad, the peak value 302 of the electric field 301 (also denoted E in FIG. 4) of the light pulse 212 coincides with the peak value of 306 of the pulse envelope 305. The corresponding vector potential 303 (also denoted A in FIG. 4) appears shifted by π/2 rad with respect to the electric field 301 so that the peak value 304 of the vector potential 303 is also shifted by π/2 rad with respect to the peak value 306 of the pulse envelope 305.

[0105] As can also be seen from FIG. 4, the electric field 301 has different magnitudes for positive and negative field amplitudes. Since virtual charge carriers 310 within the probe structure 110 directly follow the instantaneous electric field 301, the different magnitudes for positive and negative field amplitudes impart a net polarization 320 on the transiently deflected charge carriers 310, as it is schematically illustrated in FIG. 3. Thereby, the net polarization 320 within the first interaction region 130, which is located in the boundary region 125 between the probe structure 110 and the first interface contact 120, is probed by the interaction structure 120, which functions as a symmetry breaking structure that captures the transiently deflected virtual charge carriers 310.

[0106] The captured virtual charge carriers 310 then lead to a non-zero current component that is established between the first interface contact 120 and the second interface contact 122. The direction or sign of this current component with respect to the transverse direction 102 depends on the orientation of the peak value 302 of the electric field 301 with respect to the transverse direction 102, whereby the current component is reversed when switching the carrier-envelope phase between 0 rad and π rad.

[0107] The second interaction region 132 is separated from the boundary region 125 of the first interface contact 120 and also from any other symmetry breaking structure, such as a comparable boundary region around the second interface contact 122. The second interaction region 132 is centered in between the interface contacts 120, 122. This suppresses spatial symmetry breaking. While the second light pulse 222 also excites a polarization response within the second interaction region 132, this polarization response is not probed by the interface contacts 120, 122. Therefore, carrier-envelope phase values of 0 rad or r rad of the second light pulse 222 do not generate any measurable non-zero current component within the probe structure 110.

[0108] The non-zero current components within the second interaction structure 132 are generated by the second light pulses 222 by imparting a net momentum onto real charge carriers within the probe structure 110 with second light pulses 222 that have carrier-envelope phases of ±π/2 rad.

[0109] FIG. 5 depicts the band structure of the probe structure in momentum (k) space with the valence band VC and the conduction band CB, wherein k denotes the component of the momentum that is parallel to the transverse direction 102. Charge carriers 312 are excited from the valence band VC to the conduction band CB by interaction with the second light pulse 222, for example, by multiphoton absorption or Landau-Zener tunneling.

[0110] The charge carriers 312 generate a non-zero current component within the probe structure 110 if the second light pulse 222 imprints a net momentum 322 parallel to the transverse direction 102 on them by generating an asymmetric population of the conduction band CB with respect to the direction of the momentum component k. Asymmetry and thus also the imparted current is maximized for a vector potential 303 of the second light pulse 222 that has the largest difference in magnitude for positive and negative amplitudes. This is the case for light pulses 212, 222 that have an electric field 301 with a carrier-envelope phase of ±π/2 rad. Since the asymmetric population of the conduction band CB with the charge carriers 312 represents a momentum of the charge carriers 312 that persists after passage of the laser pulses 222, the charge carriers 312 represent real charge carriers.

[0111] FIG. 6 depicts the vector potential 303 and the electric field 301 of a light pulse having a carrier-envelope phase of π/2 rad. The maximum amplitude 304 of the vector potential 303 coincides with the peak 306 of the pulse envelope 305, while a maximum amplitude 302 of the electric field 301 appears shifted by π/2 rad with respect to the peak 306 of the envelope 305.

[0112] As can also be seen from FIG. 6, the electric field 301 is anti-symmetric with respect to the peak 306 of the pulse envelope 305 and thus exhibits equal amplitudes in the negative and positive electric field direction. Light pulses 212, 222 having a carrier-envelope phase of ±π/2 rad therefore do not generate a net polarization 320 of charge carriers within the probe structure 110. Likewise, as can exemplarily be seen from FIG. 4, the vector potential 303 of light pulses 212, 222 with a carrier-envelope phase of 0 rad or π rad is anti-symmetric with respect to the peak 306 of the pulse envelope 305, so that these light pulses 212, 222 do not generate a net momentum 322 of charge carriers 312 within the probe structure 110.

[0113] In summary, maximum values of the first current component are generated for carrier-envelope phase values of the first light pulses 212 that are shifted by π/2 rad from carrier-envelope phase values for which the second light pulses 222 generate maximum values of the second current component. Furthermore, the maximum values of the first current component are generated for carrier-envelope phase values of the first light pulses 212 for which the second light pulses 222 only generate a zero current within the second interaction region 132 and vice versa.

[0114] In an exemplary embodiment of the logic gate device 1, the input values of the first logic input 10 and the input values of the second logic input 12 are encoded in carrier-envelope phase values of the first and second light pulses 212, 222 that realize a NOR gate. FIG. 7 depicts the corresponding carrier-envelope phase values, first and second current components and resulting output states of the logic output 152.

[0115] A first input state of the first logic input 10 corresponding to a logic 0 is encoded in a carrier-envelope phase of the first light pulse 212 of φ.sub.A=+π/2 rad and a second input state of the first logic input 10 corresponding to a logic 1 is encoded in a carrier-envelope phase of the first light pulse 212 of φ.sub.A=0 rad. Furthermore, a first input state of the second logic input 12 corresponding to a logic 0 is encoded in a carrier-envelope phase of the second light pulse 222 of φ.sub.B=+π/2 rad and a second input state of the second logic input 12 corresponding to a logic 1 is encoded in a carrier-envelope phase of the second light pulse 222 of φ.sub.B=−π/2 rad.

[0116] The carrier-envelope phase φ.sub.A=+π/2 rad of the first input state of the first logic input 10 generates, within the first interaction region 130, a first current component 21 that is zero, which is depicted as a circle in a schematic sketch of the probe structure 110 in FIG. 7. The carrier-envelope phase φ.sub.A=0 rad of the second input state of the first logic input 10 generates a first current component 21 within the first interaction region 130, which has a maximum current value and points away from the first interface contact 120. This is depicted as a left-pointing arrow in the schematic sketch of the probe structure 110 in FIG. 7. The carrier-envelope phase φ.sub.B=+π/2 rad of the first input state of the second logic input 12 generates a second current component 22 within the second interaction region 132, which has a maximum current value and points towards the first interface contact 120. This is depicted as a right-pointing arrow in FIG. 7. Finally, the carrier-envelope phase φ.sub.B=−π/2 rad of the second input state of the second logic input 12 generates a second current component 22 within the second interaction region 132, which has a maximum current value and points away from the first interface contact 120. This is depicted as a left-pointing arrow in FIG. 7.

[0117] With the logic gate device 1, a positive current direction of a sum current within the probe structure 110 is defined parallel to the transverse direction 102. A positive sum current 20 flowing from the probe structure 110 into the first interface contact 120 that exceeds a predetermined threshold current of +2 pA encodes a logic 1 and a sum current that does not exceed the predetermined threshold current encodes a logic 0.

[0118] As it is indicated in FIG. 7, if the carrier-envelope phase φ.sub.A=+π/2 rad of the first light pulse 212 encodes the first input state of the first logic input 10 that corresponds to a logic 0 and if the carrier-envelope phase φ.sub.B=+π/2 rad of the second light pulse 222 encodes the first input state of the second logic input 12 that corresponds to a logic 0, the first current component 21 and the second current component 22 add up to a sum current 20 that is larger than +2 pA and that thus encodes a logic 1. If the carrier-envelope phase φ.sub.A=0 rad of the first light pulse 212 encodes the second input state of the first logic input 10 that corresponds to a logic 1 and the carrier-envelope phase φ.sub.B=+π/2 rad of the second light pulse 222 encodes the first input state of the second logic input 12 that corresponds to a logic 0, the first current component 21 and the second current component 22 cancel each other and thus generate a sum current 20 that is smaller than +2 pA and that thus encodes a logic 0.

[0119] If the carrier-envelope phase φ.sub.A=+π/2 rad encoding the first input state of the first logic input 10 corresponds to a logic 0 and the carrier-envelope phase φ.sub.B=−π/2 rad encoding the second input state of the second logic input 12 corresponds to a logic 1, the first current component 21 and the second current component 22 add up to a sum current 20 that is negative and thus smaller than +2 pA and that thus encodes a logic 0. Finally, if the carrier-envelope phase φ.sub.A=0 rad encoding the second input state of the first logic input 10 corresponds to a logic 1 and the carrier-envelope phase φ.sub.B=−π/2 rad encoding the second input state of the second logic input 12 also corresponds to a logic 1, the first current component 21 and the second current component 22 add up to a sum current 20 that is negative and thus smaller than +2 pA and that thus encodes a logic 0.

[0120] With another embodiment of the logic gate device 1, the input values of the first logic input 10 and the input values of the second logic input 12 are encoded in carrier-envelope phase values of the first and second light pulses 212, 222 that realize a NAND gate. FIG. 8 depicts the corresponding carrier-envelope phase values φ.sub.A, φ.sub.B, first and second current components 21, 22 and resulting output states of the logic output 152.

[0121] The first input state of the first logic input 10, which first input state corresponds to a logic 0, is encoded in a carrier-envelope phase of φ.sub.A=π rad that generates a first current component 21 having maximum amplitude and being directed from the probe structure 110 into the first interface contact 120. The second input state of the first logic input 10, which second input state corresponds to a logic 1, is encoded in a carrier-envelope phase of φ.sub.A=−π/2 rad that generates a zero current as first current component 21. The first input state of the second logic input 12, which first input state corresponds to a logic 0, is encoded in a carrier-envelope phase of φ.sub.B=+π/2 rad that generates a second current component 22 having maximum amplitude and being directed from the probe structure 110 into the first interface contact 120. The second input state of the second logic input 12, which second input state corresponds to a logic 1, is encoded in a carrier-envelope phase of φ.sub.B=0 rad that generates a zero current as second current component 22.

[0122] As long as at most one of the input states of the first and second logic input 10, 12 corresponds to a logic 0, the respective carrier-envelope phases φ.sub.A, φ.sub.B of the first and second light pulses 212, 222 generate a current component 21, 22 that is directed towards the first interface contact 120. The sum current 20 then exceeds a current of +2 pA, corresponding to an output state of the logic output 152 that is a logic 1. If both input states of the first and second logic input 10, 12 correspond to a logic 1, both the first and second current component 21, 22 are a zero current. The sum current 20 is then below the predetermined threshold of +2 pA, corresponding to a logic 0.

[0123] In another embodiment of the logic gate device 1, the input values of the first logic input 10 and the input values of the second logic input 12 are encoded in carrier-envelope phase values φ.sub.A, φ.sub.B of the first and second light pulses 212, 222 that realize an OR gate. FIG. 9 depicts the corresponding carrier-envelope phase values φ.sub.A, φ.sub.B, first and second current components 21, 22 and resulting output states of the logic output 152.

[0124] The first input state of the first logic input 10 (corresponding to a logic 0) is encoded in a carrier-envelope phase of φ.sub.A=+π/2 rad that generates the first current component 21 as zero current. The second input state of the first logic input 10 (corresponding to a logic 1) is encoded in a carrier-envelope phase of φ.sub.A=π rad that generates the first current component 21 having maximum amplitude and being directed from the probe structure 110 into the first interface contact 120. The first input state of the second logic input 12 (corresponding to a logic 0) is encoded in a carrier-envelope phase of φ.sub.B=0 rad that generates the second current component 22 as zero current. The second input state of the second logic input 12 (corresponding to a logic 1) is encoded in a carrier-envelope phase of φ.sub.B=+π/2 rad that generates the second current component 22 having maximum amplitude and being directed from the probe structure 110 into the first interface contact 120.

[0125] If both input states of the first and second logic input 10, 12 correspond to a logic 0, the associated carrier-envelope phases φ.sub.A, φ.sub.B of the first and second light pulses 212, 222 generate first and second current components 21, 22 that are zero. The sum current 20, which is also zero, and the output state of the logic output 152 corresponds to a logic 0. For all other combinations of input states, at least one of the carrier-envelope phase values φ.sub.A, φ.sub.B of the first and second light pulses 212, 222 are adjusted to generate a first or second current component 21, 22 that has maximum amplitude and is directed from the probe structure 110 into the first interface contact 120. The corresponding sum current 20 then exceeds the threshold of +2 pA, thus encoding a logic 1 at the logic output 152.

[0126] FIG. 10 depicts carrier-envelope phase values, first and second current components and resulting output states of the logic output 152 for an embodiment of the logic gate device 1, in which the input values of the first logic input 10 and the input values of the second logic input 12 are encoded in carrier-envelope phase values φ.sub.A, φ.sub.B of the first and second light pulses 212, 222 that realize an AND gate. The first input state of the first logic input 10 (corresponding to a logic 0) is encoded in a carrier-envelope phase of φ.sub.A=0 rad that generates the first current component 21 having maximum amplitude and being directed away from the first interface contact 120 into the probe structure 110. The second input state of the first logic input 10 (corresponding to a logic 1) is encoded in a carrier-envelope phase of φ.sub.A=π rad that generates the first current component 21 having maximum amplitude and being directed from the probe structure 110 into the first interface contact 120. The first input state of the second logic input 12 (corresponding to a logic 0) is encoded in a carrier-envelope phase of φ.sub.B=−π/2 rad that generates the second current component 22 having maximum amplitude and being directed away from the first interface contact 120 into the probe structure 110. The second input state of the second logic input 12 (corresponding to a logic 1) is encoded in a carrier-envelope phase of φ.sub.B=+π/2 rad that generates the second current component 22 having maximum amplitude and being directed from the probe structure 110 into the first interface contact 120.

[0127] If both input states of the first and second logic input 10, 12 correspond to a logic 0, the associated carrier-envelope phase values φ.sub.A, φ.sub.B of the first and second light pulses 212, 220 generate first and second current components 21, 22 that are directed away from the first interface contact 120 and have maximum amplitude. The corresponding sum current 20 then is below the predetermined threshold of +2 pA and the output state of the logic output 152 corresponds to a logic 0. If one of the input states of the first and second logic input 10, 12 corresponds to a logic 0 and the other one of the input states corresponds to a logic 1, the associated carrier-envelope phase values φ.sub.A, φ.sub.B of the first and second light pulses 212, 220 generate first and second current components 21, 22 that have maximum amplitudes and opposite directions. Therefore, the first and second current components 21, 22 cancel each other and the sum current 20 is below the predetermined threshold of +2 pA. The output state of the logic output 152 then corresponds to a logic 0. If both input states of the first and second logic input 10, 12 correspond to a logic 1, the associated carrier-envelope phases φ.sub.A, φ.sub.B of the first and second light pulses 212, 222 generate first and second current components 21, 22 that have maximum amplitude and are directed from the probe structure 110 into the first interface contact 120. The corresponding sum current 20 then exceeds the predetermined threshold of +2 pA and the output state of the logic output 152 corresponds to a logic 1.

[0128] FIG. 11 depicts an experimental setup to demonstrate formation of the first and second current component 21, 22 within the probe structure, as well as formation of the sum currents 20 within the probe structure 110 that represent the output states of the logic operations shown in FIGS. 7 to 10.

[0129] A control device 200 comprises a laser source 230 that is configured to output carrier-envelope phase stabilized laser pulses from which the first and second light pulses 212, 222 are deduced. The laser pulses have a FWHM duration of 6 fs at a center wavelength of 800 nm and a repetition rate of 80 MHz. The laser source 230 has a laser, which is a titanium sapphire laser, that generates the laser pulses.

[0130] The laser pulses are fed to a further beam splitter 240 that equally splits the laser pulses in a first laser pulse propagating via a first interferometer arm A and a second laser pulse propagating via a second interferometer arm B. The first interferometer arm A comprises a first phase adjustment device 250 that is controllable to adjust the carrier-envelope phase φ.sub.A of the first laser pulse and the second interferometer arm B comprises a second phase adjustment device 252 that is controllable to adjust the carrier-envelope phase φ.sub.B of the second laser pulse. Each phase adjustment device 250, 252 is exemplarily configured as a pair of SiO2 wedges that are controllable to move laterally through the path of the first and second laser pulse and thereby vary the thickness of the glass material that is passed by the first and second laser pulses.

[0131] The interferometer arm A additionally comprises a pulse separation adjustment device 245 that is configured to adjust a temporal separation between the first and second laser pulse. Thereby, the first laser pulse is delayed by a temporal delay of 130 fs with respect to the second laser pulse. The interferometer arm B comprises a steering device 255 that is exemplarily configured as an adjustable mirror and that introduces an angle between the second laser pulse traveling through interferometer arm B and the first laser pulse traveling through interferometer arm A in the far field. In the near field, the second laser pulse is displaced with respect to the first laser pulse.

[0132] The first and second laser pulses are focused by a focusing device 260, which is exemplarily configured as an off-axis parabolic mirror that focuses both laser pulses, to the logic gate device 1. Due to the angle controlled by the steering device 255, the first laser pulse is focused as the first light pulse 212 to the first interaction region 130 and the second laser pulse is focused as the second light pulse 222 to the second interaction region 132. The beam path of the first laser pulse then constitutes the first logic input 10 and the beam path of the second laser pulse constitutes the second logic input 12. Both light pulses 212, 222 reach a peak field strength of 2.3 V/nm on the probe structure 110.

[0133] The first interface contact 120 of the probe structure 110 is connected to a measurement device 150 that comprises a transimpedance amplifier 161 and a lock-in amplifier 165. The second interface contact 122 is connected to ground. The lock-in amplifier 165 is furthermore connected to a signal generator 236 that is also connected to the laser source 230.

[0134] The measurement device 150 is configured to measure the sum current 20 by performing a dual-phase lock-in detection that is referenced to a periodic modulation of the carrier-envelope phase of the laser pulse generated by the laser source 230. Thereby, a modulation signal 237 of the signal generator 236 adjusts the carrier-envelope phase of the laser source 230, which is periodically modulated with a modulation frequency of f=3.3 kHz. The lock-in amplifier 165 receives this modulation signal 237 from the signal generator 236 and outputs a lock-in amplitude 166 and lock-in phase 167 of a periodic component of the sum current 20 at the frequency of the modulation signal 237. An evaluation device 170 of the measurement device 150 receives the lock-in amplitude 166 and the lock-in phase 167 and determines the direction and amplitude of the sum current 20 for specific values of the carrier-envelope phase φ.sub.A of the first light pulse 212 and the carrier-envelope phase φ.sub.B of the second light pulse 222.

[0135] FIG. 12 depicts the measured values of the lock-in amplitude 166 (circles) and the lock-in phase 167 (squares) of the sum current 20 in dependence on a relative phase difference Δφ=φ.sub.A−φ.sub.B of the carrier-envelope phase φ.sub.A of the first light pulse 212 and the carrier-envelope phase φ.sub.B of the second light pulse 222 that is introduced by the phase adjustment devices 250, 252.

[0136] The evaluation device 170 is configured to determine the direction of the sum current 20 for the specific phase values of the first and second carrier-envelope phases φ.sub.A, φ.sub.B used in the various logic gates depicted in FIGS. 7 to 10. The evaluation device 170 thereby demodulates the harmonic oscillation of the sum current 20 based on the lock-in phase 167 and amplitude 166 shown in FIG. 12 by assuming a sinusoidal variation of the sum current 20 according to j(Δφ,Δφ.sub.g)=√{square root over (2)}.Math.j.sub.rms(Δφ).Math.sin (Δφ.sub.g−ϑ(Δφ)) with Δφ.sub.g=2π.Math.f.Math.t being a global phase shift due to the periodic variation of the carrier-envelope phase of the laser pulse output by the laser source 230 at frequency f and time t, ϑ(Δφ) the lock-in phase 167 and j.sub.rms(Δφ) the lock-in amplitude 166. The demodulated dependence of j(Δφ,Δφ.sub.g) on Δφ and Δφ.sub.g is depicted in FIG. 13.

[0137] The evaluation device 170 is further configured to transform the demodulated dependence of j(Δφ,Δφ.sub.g) on Δφ and Δφ.sub.g into a basis consisting of the carrier-envelope phase values φ.sub.A and φ.sub.B of the first and second light pulses 212, 222 according to

j(φ.sub.A,φ.sub.B)=j(Δφ=(φ.sub.A−φ.sub.B)mod 2π,Δφ.sub.g=φ.sub.B).

[0138] FIG. 14 depicts the sum current 20 in this basis. As can be seen from the carrier-envelope phase values φ.sub.A, φ.sub.B used for the NOR gate shown in FIG. 7, the sum current 20 exceeds the threshold value of j=+2 pA for φ.sub.A=φ.sub.B=π/2, while it is below this threshold value for the other phase combinations (φ.sub.A=0; φ.sub.B=π/2). (φ.sub.A=π/2; φ.sub.B=3π/2) (equivalent to (φ.sub.A=π/2; φ.sub.B=−π/2)) and (φ.sub.A=0; φ.sub.B=3π/2) (equivalent to (φ.sub.A=0; φ.sub.B=−π/2)).

[0139] Furthermore, for the carrier-envelope phase values VA, fs used for the NAND gate shown in FIG. 8, the sum current 20 exceeds the threshold value of j=+2 pA for phase combinations (φ.sub.A=π; φ.sub.B=π/2).Math.(φ.sub.A=3π/2; φ.sub.B=π/2) (equivalent to (φ.sub.A=−π/2; φ.sub.B=π/2)) and (φ.sub.A=π; φ.sub.B=0), while it is below this threshold value for (φ.sub.A=3π/2; φ=0) (equivalent to (φ.sub.A=−π/2; φ.sub.B=0)).

[0140] For the carrier-envelope phase values φ.sub.A, φ.sub.B used for the OR gate shown in FIG. 9, the sum current 20 is below the threshold value of j=+2 pA for the phase combination (φ.sub.A=π/2; φ.sub.B=0), while it is above this threshold value for (φ.sub.A=π; φ.sub.B=0), (φ.sub.A=π/2; φ.sub.B=π/2) and (φ.sub.A=π; φ.sub.B=π/2).

[0141] Finally, for the carrier-envelope phase values φ.sub.A, φ.sub.B used for the AND gate shown in FIG. 10, the sum current 20 is below the threshold value of j=+2 pA for the phase combinations (φ.sub.A=0; φ.sub.B=3π/2) (equivalent to (φ.sub.A=0; φ.sub.B=−π/2)), (φ.sub.A=π; φ.sub.B=3π/2) (equivalent to (φ.sub.A=π; φ.sub.B=−π/2) and (φ.sub.A=0; φ.sub.B=π/2), while it is above this threshold for the phase combination (φ.sub.A=π; φ.sub.B=π/2).

[0142] The results obtained from the experimental setup (FIG. 11) shown in FIGS. 13 and 14 thus unambiguously demonstrate that the sum current 20 is generated within the probe structure 110 and at the interface contact 122 and that the sum current produces logic output states that depend on the respective phase combinations φ.sub.A, φ.sub.B of the carrier-envelope phases of the light pulses 112, 122 in a way that the logic gate device 1 implements the NOR gate when encoding the logic input states in the carrier-envelope phase values φ.sub.A, φ.sub.B shown in FIG. 7, the NAND gate when encoding the logic input states in the carrier-envelope phase values φ.sub.A, φ.sub.B shown in FIG. 8, the OR gate when encoding the logic input states in the carrier-envelope phase values φ.sub.A, φ.sub.B shown in FIG. 9 and the AND gate when encoding the logic input states in the carrier-envelope phase values φ.sub.A, φ.sub.B shown in FIG. 10.

[0143] FIG. 15 depicts a method 500 for implementing a logic gate according to the present disclosure. The method 500 comprises providing 505 the first light pulse 212 having the first carrier-envelope phase φ.sub.A and providing 510 the second light pulse 222 having the second carrier-envelope phase φ.sub.B. The method 500 furthermore comprises irradiating 515 the probe structure with the first light pulse 212 in the first interaction region 130 and irradiating 520 the probe structure 110 with the second light pulse 222 in the second interaction region 132. Furthermore, the method comprises outputting 525 the sum current at the first interface contact 120.

REFERENCE NUMERAL LIST

[0144] 1 logic gate device [0145] 10 first logic input [0146] 12 second logic input [0147] 20 sum current [0148] 21 first current component [0149] 22 second current component [0150] 100 probe device [0151] 101 height direction [0152] 102 transverse direction [0153] 103 further transverse direction [0154] 105 extent in height direction [0155] 106 extent in transverse direction [0156] 107 extent in further transverse direction [0157] 110 probe structure [0158] 112 lateral side [0159] 120 first interface contact [0160] 122 second interface contact [0161] 125 boundary region [0162] 130 first interaction region [0163] 131 size of first interaction region [0164] 132 second interaction region [0165] 133 size of second interaction region [0166] 139 separation [0167] 140 substrate [0168] 150 measurement device [0169] 152 logic output [0170] 161 transimpedance amplifier [0171] 165 lock-in amplifier [0172] 166 lock-in amplitude [0173] 167 lock-in phase [0174] 170 evaluation device [0175] 200 control device [0176] 201 first control input [0177] 202 second control input [0178] 210 first light source [0179] 212 first light pulse [0180] 214 first carrier-envelope phase [0181] 220 second light source [0182] 222 second light pulse [0183] 224 second carrier-envelope phase [0184] 230 laser source [0185] 236 signal generator [0186] 237 modulation signal [0187] 240 beam splitter [0188] 245 delay device [0189] 250 first phase adjustment device [0190] 252 second phase adjustment device [0191] 255 steering device [0192] 260 focusing device [0193] 301 electric field [0194] 302 maximum amplitude of the electric field [0195] 303 vector potential [0196] 304 maximum amplitude of the vector potential [0197] 305 envelope [0198] 306 peak of the envelope [0199] 310 virtual charge carriers [0200] 312 real charge carriers [0201] 320 net polarization [0202] 322 net momentum [0203] 500 method [0204] 505 providing first light pulse [0205] 510 providing second light pulse [0206] 515 irradiating with first light pulse [0207] 520 irradiating with second light pulse [0208] 525 output sum current [0209] CB conduction band [0210] VB valence band [0211] k momentum