NORMALLY-OFF MODE POLARIZATION SUPER JUNCTION GaN-BASED FIELD EFFECT TRANSISTOR AND ELECTRICAL EQUIPMENT

Abstract

This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type In.sub.yGa.sub.1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12 and a p-type In.sub.zGa.sub.1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the Al.sub.xGa.sub.1-xN layer 12. The gate electrode 20 may be provided on the p-type In.sub.zGa.sub.1-zN layer 19 via a gate insulating film. At a non-operating time, n.sub.0≤n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 formed in the undoped GaN layer 11/the Al.sub.xGa.sub.1-xN layer 12 hetero-interface just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18.

Claims

1-10. (canceled)

11. A normally-off mode polarization super junction GaN-based field effect transistor, comprising: a first undoped GaN layer, an Al.sub.xGa.sub.1-xN layer (0<x<1) on the first undoped GaN layer, a second undoped GaN layer having an island-like shape on the Al.sub.xGa.sub.1-xN layer, a p-type GaN layer on the second undoped GaN layer, a p-type In.sub.yGa.sub.1-yN layer (0<y<1) on the p-type GaN layer, a source electrode on the Al.sub.xGa.sub.1-xN layer, a drain electrode on the Al.sub.xGa.sub.1-xN layer, a first gate electrode electrically connected to the p-type In.sub.yGa.sub.1-yN layer; and a p-type In.sub.zGa.sub.1-zN layer (0<z<1) and a second gate electrode thereon on the Al.sub.xGa.sub.1-xN layer which are located beside one end of the second undoped GaN layer on the side of the source electrode, the Al.sub.xGa.sub.1-xN layer having a protrusion having an island-like shape as the same as the second undoped GaN layer on an upper part just below the second undoped GaN layer, the p-type In.sub.zGa.sub.1-zN layer and the second gate electrode being provided on a flat upper surface of a part of the Al.sub.xGa.sub.1-xN layer which is located beside the protrusion, the first gate electrode and the second gate electrode being provided independently each other, the p-type GaN layer existing on the whole surface of the second undoped GaN layer or on only one side of the surface of the second undoped GaN layer on the side of the source electrode, the p-type In.sub.yGa.sub.1-yN layer existing on only one side of the surface of the p-type GaN layer on the side of the source electrode if the p-type GaN layer exists on the whole surface of the second undoped GaN layer or existing on the whole surface or a part of the surface of the p-type GaN layer if the p-type GaN layer exists on only one side of the surface of the second undoped GaN layer on the side of the source electrode,
n.sub.0≤n.sub.1<n.sub.2<n.sub.3 and n.sub.0<( 1/1000)×n.sub.3 being satisfied at a non-operating time if the concentration of a two-dimensional electron gas formed in the first undoped GaN layer in the vicinity part of a hetero-interface between the first undoped GaN layer and the Al.sub.xGa.sub.1-xN layer just below the second gate electrode is denoted as n.sub.0, the concentration of the two-dimensional electron gas just below the first gate electrode is denoted as n.sub.1, the concentration of the two-dimensional electron gas in a polarization super junction region is denoted as n.sub.2 and the concentration of the two-dimensional electron gas in a part between the polarization super junction region and the drain electrode is denoted as n.sub.3,
p.sub.1>p.sub.2 being satisfied if the concentration of a two-dimensional hole gas formed in the second undoped GaN layer in the vicinity part of a hetero-interface between the second undoped GaN layer and the Al.sub.xGa.sub.1-xN layer just below the first gate electrode is denoted as p.sub.1 and the concentration of the two-dimensional hole gas in the polarization super junction region is denoted as p.sub.2.

12. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 11 wherein the In composition y and the thickness t of the p-type In.sub.yGa.sub.1-yN layer are selected to satisfy y×t≤0.20×5 [nm] and the In composition z and the thickness t of the p-type In.sub.zGa.sub.1-zN layer are selected to satisfy z×t≤0.20×5 [nm].

13. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 11 wherein the first gate electrode and the second gate electrode are electrically connected each other and act as one gate electrode.

14. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 11 wherein the first gate electrode and the source electrode are electrically connected each other and the first gate electrode acts as a field plate.

15. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 11 wherein the first gate electrode is fixed to a positive potential with respect to the potential of the source electrode.

16. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 11 wherein the first gate electrode, the second gate electrode and the source electrode are electrically connected each other and the transistor operates as a diode.

17. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 11 wherein the second gate electrode is provided on the p-type InzGa1-zN layer via a gate insulating film.

18. Electrical equipment, comprising: at least a transistor, the transistor being a normally-off mode polarization super junction GaN-based field effect transistor, comprising: a first undoped GaN layer, an Al.sub.xGa.sub.1-xN layer (0<x<1) on the first undoped GaN layer, a second undoped GaN layer having an island-like shape on the Al.sub.xGa.sub.1-xN layer, a p-type GaN layer on the second undoped GaN layer, a p-type In.sub.yGa.sub.1-yN layer (0<y<1) on the p-type GaN layer, a source electrode on the Al.sub.xGa.sub.1-xN layer, a drain electrode on the Al.sub.xGa.sub.1-xN layer, a first gate electrode electrically connected to the p-type In.sub.yGa.sub.1-yN layer; and a p-type In.sub.zGa.sub.1-zN layer (0<z<1) and a second gate electrode thereon on the Al.sub.xGa.sub.1-xN layer which are located beside one end of the second undoped GaN layer on the side of the source electrode, the Al.sub.xGa.sub.1-xN layer having a protrusion having an island-like shape as the same as the second undoped GaN layer on an upper part just below the second undoped GaN layer, the p-type In.sub.zGa.sub.1-zN layer and the second gate electrode being provided on a flat upper surface of a part of the Al.sub.xGa.sub.1-xN layer which is located beside the protrusion, the first gate electrode and the second gate electrode being provided independently each other, the p-type GaN layer existing on the whole surface of the second undoped GaN layer or on only one side of the surface of the second undoped GaN layer on the side of the source electrode, the p-type In.sub.yGa.sub.1-yN layer existing on one side of the surface of the p-type GaN layer on the side of the source electrode if the p-type GaN layer exists on the whole surface of the second undoped GaN layer or existing on the whole surface or a part of the surface of the p-type GaN layer if the p-type GaN layer exists on only one side of the surface of the second undoped GaN layer on the side of the source electrode,
n.sub.0≤n.sub.1<n.sub.2<n.sub.3 and n.sub.0<( 1/1000)×n.sub.3 being satisfied at a non-operating time if the concentration of a two-dimensional electron gas formed in the first undoped GaN layer in the vicinity part of a hetero-interface between the first undoped GaN layer and the Al.sub.xGa.sub.1-xN layer just below the second gate electrode is denoted as n.sub.0, the concentration of the two-dimensional electron gas just below the first gate electrode is denoted as n.sub.1, the concentration of the two-dimensional electron gas in a polarization super junction region is denoted as n.sub.2 and the concentration of the two-dimensional electron gas in a part between the polarization super junction region and the drain electrode is denoted as n.sub.3,
p.sub.1>p.sub.2 being satisfied if the concentration of a two-dimensional hole gas formed in the second undoped GaN layer in the vicinity part of a hetero-interface between the second undoped GaN layer and the Al.sub.xGa.sub.1-xN layer just below the first gate electrode is denoted as p.sub.1 and the concentration of the two-dimensional hole gas in the polarization super junction region is denoted as p.sub.2.

19. The electrical equipment according to claim 18 wherein the second gate electrode of the normally-off mode polarization super junction GaN-based field effect transistor is provided on the p-type InzGa1-zN layer via a gate insulating film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG. 1 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a first embodiment of the invention.

[0050] FIG. 2 A schematic view showing an energy band diagram of each region of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0051] FIG. 3 A cross-sectional view for explaining operation mechanism of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0052] FIG. 4 A schematic view showing a distribution of electric field when a reverse bias is applied between the drain and the source and 0 V is applied between the gate and the source in the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0053] FIG. 5 A schematic view showing a distribution of potential when a reverse bias is applied between the drain and the source and 0 V is applied between the gate and the source in the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0054] FIG. 6 A cross-sectional view for explaining the manufacturing method of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0055] FIG. 7 A cross-sectional view for explaining the manufacturing method of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0056] FIG. 8 A cross-sectional view for explaining the manufacturing method of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0057] FIG. 9 A cross-sectional view for explaining the manufacturing method of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0058] FIG. 10 A circuit diagram showing a measurement circuit used to measure static characteristics of the normally-off mode polarization super junction GaN-based FET according to the example.

[0059] FIG. 11 A schematic view showing the drain current-drain voltage characteristics of the normally-off mode polarization super junction GaN-based FET according to the example.

[0060] FIG. 12 A schematic view showing the drain current-gate voltage characteristics of the normally-off mode polarization super junction GaN-based FET according to the example.

[0061] FIG. 13 A schematic view showing the logarithmic presentation of the drain current of the drain current-gate voltage characteristics shown in FIG. 12.

[0062] FIG. 14 A schematic view showing the voltage resistance characteristics of the normally-off mode polarization super junction GaN-based FET according to the example.

[0063] FIG. 15A A cross-sectional view showing the Hall element prepared to measure the concentration of the two-dimensional electron gas and the concentration of the two-dimensional hole gas in the particular region of the normally-off mode polarization super junction GaN-based FET according to the example.

[0064] FIG. 15B A cross-sectional view showing the Hall element prepared to measure the concentration of the two-dimensional electron gas and the concentration of the two-dimensional hole gas in the particular region of the normally-off mode polarization super junction GaN-based FET according to the example.

[0065] FIG. 15C A cross-sectional view showing the Hall element prepared to measure the concentration of the two-dimensional electron gas and the concentration of the two-dimensional hole gas in the particular region of the normally-off mode polarization super junction GaN-based FET according to the example.

[0066] FIG. 15D A cross-sectional view showing the Hall element prepared to measure the concentration of the two-dimensional electron gas and the concentration of the two-dimensional hole gas in the particular region of the normally-off mode polarization super junction GaN-based FET according to the example.

[0067] FIG. 16A A plan view showing electrode arrangement of the Hall element shown in FIG. 15A and FIG. 15D.

[0068] FIG. 16B A plan view showing electrode arrangement of the Hall element shown in FIG. 15B and FIG. 15C.

[0069] FIG. 17A A circuit diagram showing a first example of connecting way of terminals of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0070] FIG. 17B A circuit diagram showing a second example of connecting way of terminals of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0071] FIG. 17C A circuit diagram showing a third example of connecting way of terminals of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0072] FIG. 17D A circuit diagram showing a fourth example of connecting way of terminals of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0073] FIG. 18 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a second embodiment of the invention.

[0074] FIG. 19 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a third embodiment of the invention.

[0075] FIG. 20A A schematic view showing an energy band diagram of the region just below the gate electrode 20 of the normally-off mode polarization super junction GaN-based FET according to the third embodiment of the invention.

[0076] FIG. 20BA schematic view showing an energy band diagram of the region just below the gate electrode 20 of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0077] FIG. 21A A schematic view showing an energy band diagram of the region just below the gate electrode 20 of the normally-off mode polarization super junction GaN-based FET according to the third embodiment of the invention when the gate voltage is applied.

[0078] FIG. 21B A schematic view showing an energy band diagram of the region just below the gate electrode 20 of the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention when the gate voltage is applied.

[0079] FIG. 22 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a fourth embodiment of the invention.

[0080] FIG. 23 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a fifth embodiment of the invention.

MODES FOR CARRYING OUT THE INVENTION

[0081] Modes for carrying out the invention (hereinafter referred as embodiments) will now be explained below.

The First Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0082] As shown in FIG. 1, in the normally-off mode polarization super junction GaN-based FET according to the first embodiment, an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13 are stacked in order on a substrate 10 via a buffer layer (not illustrated). The substrate 10 is preferably a substrate on which GaN-based semiconductor grows in C-plane orientation such as, for example, a C-plane sapphire substrate, a Si substrate, a SiC substrate and the like. The buffer layer is made of, for example, polycrystalline or amorphous GaN, AlN, AlGaN, further AlGaN/GaN superlattice and the like. The Al.sub.xGa.sub.1-xN layer 12 is typically undoped, but may be n-type or p-type Al.sub.xGa.sub.1-xN layer doped with donors (n-type impurities) or acceptors (p-type impurities). The undoped GaN layer 13 has an island-like shape. The Al.sub.xGa.sub.1-xN layer 12 is exposed around the undoped GaN layer 13. In FIG. 1, shown is a case where the upper part of the Al.sub.xGa.sub.1-xN layer 12 has the same island-like shape as the undoped GaN layer 13 and the thickness of the Al.sub.xGa.sub.1-xN layer 12 other than this is smaller than the thickness of the island-like part of the Al.sub.xGa.sub.1-xN layer 12. However, there may be a case where the upper part of the Al.sub.xGa.sub.1-xN layer 12 has not an island-like shape and the thickness of the Al.sub.xGa.sub.1-xN layer 12 is uniform. A p-type GaN layer 14 is stacked on the whole surface of the undoped GaN layer 13. The thickness of a part of the p-type GaN layer 14 on the side of a drain electrode 18 which will be described later is smaller than the thickness of a part of the p-type GaN layer 14 on the side of a source electrode 17 which will be described later. The part of the p-type GaN layer 14 having the smaller thickness corresponds to the polarization super junction region (PSJ region). A p-type In.sub.yGa.sub.1-yN layer 15 is stacked on the part of the p-type GaN layer 14 having the larger thickness. Although the p-type In.sub.yGa.sub.1-yN layer 15 may be stacked on the whole surface of the part of the p-type GaN layer 14 having the larger thickness, illustrated here is a case where the p-type In.sub.yGa.sub.1-yN layer 15 is formed on only the part of the p-type GaN layer 14 having the larger thickness except a part on the side of the drain electrode 18. The p-type GaN layer 14 is doped with magnesium (Mg) as p-type impurities. The p-type In.sub.yGa.sub.1-yN layer 15 is also doped with Mg. The In composition y of the p-type In.sub.yGa.sub.1-yN layer 15 is 0<y<1. More specifically, the In composition y and the thickness t of the p-type In.sub.yGa.sub.1-yN layer 15 are selected as necessary and the In composition y is typically selected to be not larger than 0.20. The In composition y and the thickness t are typically selected to satisfy y×t≤0.20×5 [nm] generally. For example, if y=0.10, t is selected to be about t=10 nm or smaller than this.

[0083] A gate electrode 16 is provided on the p-type In.sub.yGa.sub.1-yN layer 15. The gate electrode 16 is made of metals having large work function, for example, typically nickel (Ni) so as to bring it ohmic contact with the p-type In.sub.yGa.sub.1-yN layer 15. The gate electrode 16 may be made of a layered film made of a Ni film and another metal film stacked thereon. The source electrode 17 is provided on the Al.sub.xGa.sub.1-xN layer 12 at a part on the side of the p-type In.sub.yGa.sub.1-yN layer 15 with respect to the island-like layered structure made of the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 and the drain electrode 18 is provided on the Al.sub.xGa.sub.1-xN layer 12 at a part on the opposite side with respect to the island-like layered structure. The source electrode 17 and the drain electrode 17 are made of metals having small work function, typically, for example titanium (Ti) so as to allow ohmic contact with the 2DEG formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12 as described later. The source electrode 17 and the drain electrode 18 may be made of a layered film made of a Ti film and aluminum (Al) film, nickel (Ni) film, gold (Au) film and the like stacked thereon. A p-type In.sub.zGa.sub.1-zN layer 19 and a gate electrode 20 thereon are provided on the Al.sub.xGa.sub.1-xN layer 12 beside one end of the island-like upper part of the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 on the side of the source electrode 17. The In composition z of the p-type In.sub.zGa.sub.1-zN layer 19 may be the same as or different from the In composition y of the p-type In.sub.yGa.sub.1-yN layer 15. The In composition z of the p-type In.sub.zGa.sub.1-zN layer 19 is 0<z<1. More specifically, the In composition z and the thickness t of the p-type In.sub.zGa.sub.1-zN layer 19 are selected as necessary and the In composition z is typically selected to be not larger than 0.20. The In composition z and the thickness t are typically selected to satisfy z×t≤0.20×5 [nm] generally. For example, if z=0.10, t is selected to be about t=10 nm or smaller than this.

[0084] In the normally-off mode polarization super junction GaN-based FET, a part of the p-type GaN layer 14 having the smaller thickness and the undoped GaN layer 13, the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 which are just below the part form the polarization super junction region (intrinsic polarization super junction region). The p-type In.sub.yGa.sub.1-yN layer 15, a part of the p-type GaN layer 14 having the larger thickness and the undoped GaN layer 13, the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 which are just below the p-type GaN layer 14 form a gate electrode contact region.

[0085] In the normally-off mode polarization super junction GaN-based FET, due to piezo polarization and spontaneous polarization, positive fixed charge is induced in the Al.sub.xGa.sub.1-xN layer 12 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12, and negative fixed charge is induced in the Al.sub.xGa.sub.1-xN layer 12 in the vicinity part of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13. As a result, in the normally-off mode polarization super junction GaN-based FET, at a non-operating time (thermal equilibrium state), a 2DHG 21 is formed in the undoped GaN layer 13 in the vicinity part of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 and a 2DEG 22 is formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12.

[0086] In the normally-off mode polarization super junction GaN-based FET, at a non-operating time (thermal equilibrium state), n.sub.0≤n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18. The concentration of the 2DEG 22 in the part between the gate electrode 20 and the source electrode 17 is also n.sub.3. In FIG. 1, the magnitude relation of n.sub.0≤n.sub.1<n.sub.2<n.sub.3 is schematically shown by the size of circle denoting electron and its density. In this case, the concentration n.sub.0 of the 2DEG 22 just below the gate electrode 20 is sufficiently low such that the 2DEG 22 is almost depleted. Therefore, the electron channel made of the 2DEG 22 is interrupted just below the gate electrode 20. Typically, n.sub.0<( 1/1000) x n.sub.3 is satisfied. On the other hand, for the concentration p.sub.1 of the 2DHG 21 just below the gate electrode 16 and the concentration p.sub.2 of the 2DHG 21 in the polarization super junction region, p.sub.1>p.sub.2 is generally satisfied.

[0087] FIG. 2 shows the energy band diagram of each region of the normally-off mode polarization super junction GaN-based FET in the direction vertical to the substrate 10. Shown in FIG. 2 from the left in order are the energy band diagram in the part just below the gate electrode 20, the energy band diagram in the part just below the gate electrode 16, the energy band diagram in the part of the polarization super junction region and the energy band diagram in the part between the polarization super junction region and the drain electrode 18. These energy band diagrams show qualitatively the relative concentration of the 2DEG 22 and the 2DHG 21 in each part. In FIG. 2, the ordinate denotes electron energy, E, denotes energy of the bottom end of the conduction band, E.sub.v denotes energy of the upper end of the valence band and E.sub.f denotes Fermi energy. As shown in FIG. 2, the 2DEG 22 of the concentration n.sub.3 is formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12 in the part between the polarization super junction region and the drain electrode 18. In the polarization super junction region, the conduction band is lifted up due to the polarization effect by the undoped GaN layer 13 and the p-type GaN layer 14. As a result, the concentration n.sub.2 of the 2DEG 22 formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12 is lower than the concentration n.sub.3. In the polarization super junction region, the valence band is lifted up due to the same effect and therefore the 2DHG 21 of the concentration p.sub.2 is formed in the valence band in the vicinity part of the hetero-interface between the undoped GaN layer 13 and the Al.sub.xGa.sub.1-xN layer 12. In the part of the gate electrode 16, the conduction band is further lifted up by the p-type In.sub.yGa.sub.1-yN layer 15 and therefore the concentration n.sub.1 of the 2DEG 22 formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12 is lower than the concentration n.sub.2. In the part of the gate electrode 16, the valence band is further lifted up due to the same effect. As a result, the 2DHG 21 of the concentration p.sub.1 larger than the concentration p.sub.2 is formed in the valence band in the vicinity part of the hetero-interface between the undoped GaN layer 13 and the Al.sub.xGa.sub.1-xN layer 12. In the part of the gate electrode 20, due to the polarization effect by the p-type In.sub.zGa.sub.1-zN layer 19, the concentration n.sub.0 of the 2DEG 22 is extremely small concentration at least less than n.sub.1, which is substantially 0 such that the electron channel made of the 2DEG is interrupted in the part.

[Operation Mechanism of the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0088] As shown in FIG. 3, the source electrode 17, the gate electrode 16 and the gate electrode 20 are connected each other and a positive voltage V.sub.dg is applied to the drain electrode 18 with respect to the source electrode 17, the gate electrode 16 and the gate electrode 20. In this case, the gate electrode 16 and the drain electrode 18 are reverse biased and the gate electrode 20 and the drain electrode 18 are reverse biased. As a result, holes of the 2DHG 21 in the polarization super junction region are extracted from the gate electrode 16 and electrons of the 2DEG 22 in the polarization super junction region are extracted from the drain electrode 18. The concentration n.sub.0 of the 2DEG 22 just below the gate electrode 20 is substantially 0, so that no electric current flow from the source electrode 17 to the drain electrode 18 via the 2DEG 22. That is, the FET is normally-off.

[0089] Electric field distribution and potential distribution of the normally-off mode polarization super junction GaN-based FET in this state are shown in FIG. 4 and FIG. 5, respectively. As shown in FIG. 4, the electric field is almost uniform in the polarization super junction region. Therefore, as shown in FIG. 5, the potential decreases gently toward the drain electrode 18 in the polarization super junction region. As shown in FIG. 4, at the end of the polarization super junction region on the side of the drain electrode 18, the peak electric field results at the connection point between the 2DEG 22 of the concentration n.sub.2 and the 2DEG 22 of the concentration n.sub.3, but the voltage borne by the polarization super junction region itself is much larger than the voltage borne by the peak electric field. That is, the voltage which causes breakdown of the normally-off mode polarization super junction GaN-based FET is borne by the polarization super junction region itself, which raises remarkably the voltage resistance. Therefore, the normally-off mode polarization super junction GaN-based FET can obtain high voltage resistance while keeping normally-off state.

[Method for Manufacturing the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0090] First, as shown in FIG. 6, by the conventionally known MOCVD (metal organic chemical vapor deposition) method using TMG (trimethyl gallium) as Ga source, TMA (trimethyl aluminium) as Al source, NH.sub.3 (ammonia) as nitrogen source, N.sub.2 gas and H.sub.2 gas as carrier gas, a buffer layer (not illustrated), the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 are epitaxially grown in order on the substrate 10. The growth temperature of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 is, for example, about 1100° C. As the substrate 10, a sapphire substrate (for example, a C-plane sapphire substrate), a Si substrate, a SiC substrate and the like can be used. As the buffer layer, a GaN layer, an AlN layer, an AlGaN layer, an AlGaN/GaN superlattice layer and the like can be used. When, for example, the GaN layer is used as the buffer layer, it is grown in low temperature of, for example, about 530° C. As the p-type dopant for growing the p-type GaN layer 14, bis-cyclopentadienyl magnesium (Cp.sub.2 Mg) is used. As the carrier gas for growing the p-type GaN layer 14, hydrogen (H.sub.2) and nitrogen (N.sub.2) are used.

[0091] Then, a mask such as a resist pattern having a shape corresponding to the device forming region is formed on the p-type GaN layer 14. Thereafter, the p-type GaN layer 14, the undoped GaN layer 13, the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 are etched in order to the depth midway in the thickness direction of the undoped GaN layer 11 using the mask to carry out patterning into the predetermined shape. As a result, device isolation is carried out. Thereafter, the mask is removed. The patterning can be carried out by etching using a reactive ion etching (RIE) method and the like.

[0092] Then, a mask such as a resist pattern having a planar shape corresponding to the p-type GaN layer 14 shown in FIG. 1 is formed on the p-type GaN layer 14. Thereafter, the p-type GaN layer 14, the undoped GaN layer 13 and the Al.sub.xGa.sub.1-xN layer 12 are etched in order to the depth midway in the thickness direction of the Al.sub.xGa.sub.1-xN layer 12 using the mask to carry out patterning into the predetermined shape. The patterning can be carried out by etching using the RIE method and the like. Thereafter, the mask is removed.

[0093] Then, a mask such as a resist pattern is formed on the surface of the region except the polarization super junction region. Thereafter, the p-type GaN layer 14 is etched to the depth midway in the thickness direction of the p-type GaN layer 14 using the mask to carry out thinning. The etching can be carried out by the RIE method and the like. Thereafter, the mask is removed. This state is shown in FIG. 7.

[0094] Then, as shown in FIG. 8, the p-type In.sub.yGa.sub.1-yN layer 15 is grown on the whole surface by, for example, the MOCVD method, the sputtering method and the like.

[0095] Then, as shown in FIG. 9, for example, the p-type In.sub.yGa.sub.1-yN layer 15 is patterned to leave the part on the thicker part of the p-type GaN layer 14 and the part beside the end of the island-like undoped GaN layer 13 on the side of the source electrode 17. The patterning can be carried out by, for example, the RIE method, the wet etching method and the like. The p-type In.sub.yGa.sub.1-yN layer 15 left at the part beside the end of the island-like undoped GaN layer 13 on the side of the source electrode 17 forms the p-type In.sub.zGa.sub.1-zN layer 19. That is, in this case, the p-type In.sub.zGa.sub.1-zN layer 19 is formed by the p-type In.sub.yGa.sub.1-yN layer 15 and z=y.

[0096] Then, the source electrode 17 and the drain electrode 18 are formed on the Al.sub.xGa.sub.1-xN layer 12. Thereafter, the gate electrode 16 is formed on the p-type In.sub.yGa.sub.1-yN layer 15 on the p-type GaN layer 14 and the gate electrode 20 is formed on the p-type In.sub.zGa.sub.1-zN layer 19 on the Al.sub.xGa.sub.1-xN layer 12.

[0097] In this way, the target normally-off mode polarization super junction GaN-based FET shown in FIG. 1 is manufactured.

EXAMPLE

[0098] The normally-off mode polarization super junction GaN-based FET was prepared and various evaluations were carried out.

[0099] That is, first, a C-plane sapphire substrate was used as the substrate 10 and a GaN low temperature buffer layer having a thickness of 30 nm, the undoped GaN layer 11 having a thickness of 3000 nm, the Al.sub.xGa.sub.1-xN layer 12 having a thickness of 30 nm and x=0.21, the undoped GaN layer 13 having a thickness of 50 nm and the p-type GaN layer 14 having a thickness of 40 nm and Mg concentration [Mg]=5×10.sup.19 cm.sup.−3 were epitaxially grown in order. The growth temperature of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 was set to 1100° C. As carrier gas during growth, N.sub.2 gas and H.sub.2 gas were used. As the p-type dopant for growing the p-type GaN layer 14, Cp.sub.2 Mg was used.

[0100] Then, the surface of the p-type GaN layer 14 in the device isolation region was masked and etching for device isolation was carried out by ICP (induction coupled plasma)-RIE using chlorine (Cl)-based gas until the upper part of the undoped GaN layer 11 was etched.

[0101] Then, the surface of the parts of the p-type GaN layer 14 corresponding to the gate electrode contact region and the polarization super junction region was masked and the p-type GaN layer 14, the undoped GaN layer 13 and the Al.sub.xGa.sub.1-xN layer 12 were etched in order until the remained thickness of the Al.sub.xGa.sub.1-xN layer 12 reaches 15 nm.

[0102] Then, the surface of the region except the polarization super junction region was masked and etching was carried out to thin the p-type GaN layer 14 in the polarization super junction region.

[0103] Then, the p-type In.sub.yGa.sub.1-yN layer 15 having a thickness of 5 nm, x=0.18 and [Mg]=1×10.sup.20 cm.sup.−3 by the MOCVD method. The growth temperature of the p-type In.sub.yGa.sub.1-yN layer 15 was set to 950° C. As carrier gas during growth 100% N.sub.2 was used.

[0104] Then, the surface of the parts of the p-type In.sub.yGa.sub.1-yN layer 15 on which the gate electrode 16 and the gate electrode 20 are formed was masked and etching of the p-type In.sub.yGa.sub.1-yN layer 15 was carried out by ICP-RIE using Cl-based gas to leave the p-type In.sub.yGa.sub.1-yN layer 15 only in the parts on which the gate electrode 16 and the gate electrode 20 are to be formed.

[0105] Then, the surface of the region except the region on which the source electrode 17 and the drain electrode 18 are to be formed was masked by an SiO.sub.2 film and a Ti/Al/Ni/Au layered film was formed on the source electrode forming part and the drain electrode forming part by the vacuum evaporation method to form the source electrode 17 and the drain electrode 18. Thereafter, ohmic alloy treatment of 800° C. and 60 seconds was carried out in N.sub.2.

[0106] Then, the surface of the region except the region on which the gate electrode 16 and the gate electrode 20 are to be formed was masked by an SiO.sub.2 film and a Ti/Ni/Au layered film was formed on the p-type In.sub.yGa.sub.1-yN layer 15 beside the edge of the undoped GaN layer 13 on the side of the source electrode 17 by the vacuum evaporation method to form the gate electrode 16 and the gate electrode 20. Thereafter, ohmic alloy treatment was carried out by carrying out a rapid thermal annealing (RTA) of 500° C. and 100 seconds in N.sub.2. In this case, the p-type In.sub.zGa.sub.1-zN layer 19 was formed by the p-type In.sub.yGa.sub.1-yN layer 15.

[0107] In this way, the normally-off mode polarization super junction GaN-based FET was prepared. Regarding the normally-off mode polarization super junction GaN-based FET, the PSJ length was 15 μm, the gate length of the gate electrode 16 was 5 μm, the gate width was 100 mm, the gate length of the gate electrode 20 was 5 μm, the gate width was 100 mm, the distance between the end of the polarization super junction region on the side of the drain electrode 18 and the drain electrode 18 was 3 μm and the thickness of the Al.sub.xGa.sub.1-xN layer 12 just below the gate electrode 20 was about 15 nm.

[0108] In order to investigate electric characteristics of the normally-off mode polarization super junction GaN-based FET prepared as described above, a measurement circuit connected as shown in FIG. 10 was formed. And static characteristics of the FET were measured as a three-terminal element in which the gate electrode 16 and the gate electrode 20 were common.

(Drain Current (I.sub.d)−Drain Voltage (V.sub.d) Characteristics)

[0109] FIG. 11 shows the result of measurement of the I.sub.d−V.sub.d characteristics in which the gate voltage V.sub.g is used as parameters. As shown in FIG. 11, I.sub.d was almost 0 [A] at V.sub.g=0.

(Drain Current (I.sub.d)−Gate Voltage (V.sub.g) Characteristics)

[0110] FIG. 12 shows the result of measurement of the I.sub.d−V.sub.g characteristics when V.sub.d=1.0 [V] was set. As shown in FIG. 12, I.sub.d rises over V.sub.g=0 [V]. FIG. 13 shows the I.sub.d−V.sub.g characteristics shown in FIG. 12 in which logarithmic representation of I.sub.d was adopted to obtain high resolution. In FIG. 13, rising of I.sub.d over V.sub.g=0 [V] is clearly shown. If the threshold voltage V.sub.th is defined as V.sub.g when the drain current I.sub.d is about 1/100 (2.5×10.sup.−2 [A]) of the rated drain current of the FET (in this FET, I.sub.d˜2.5 [A] when V.sub.d=1 [V] and V.sub.g=5 [V]), V.sub.th is about 0.7 [V]. That is, it is apparent that normally-off mode was realized. Here, V.sub.th was defined as V.sub.g when the drain current I.sub.d is 1/100 of the maximum rated drain current because the circuit system can be substantially protected by the normally-off mode FET when the gate signal was lost.

(Off Voltage Resistance Characteristic)

[0111] FIG. 14 shows the result of measurement of I.sub.d for V.sub.d when the normally-off mode polarization super junction GaN-based FET was in an off-state by setting V.sub.g=−8 [V]. The ordinate of FIG. 14 is the logarithmic axis. As shown in FIG. 14, in the normally-off mode polarization super junction GaN-based FET, I.sub.d˜30 [μA] when V.sub.d˜1.5 [kV], which means that very high voltage resistance was obtained.

[0112] The concentration of the 2DEG 22 and the concentration of the 2DHG 21 of each region in the normally-off mode polarization super junction GaN-based FET were measured. And it was demonstrated that n.sub.0≤n.sub.1<n.sub.2<n.sub.3 and p.sub.1>p.sub.2 were satisfied. The result is now described. Hall elements were prepared to measure the concentration of the 2DEG 22 and the concentration of the 2DHG 21 of each region. More specifically, a Hall element H.sub.1 shown in FIG. 15A which has the same layer structure as the part of the 2DEG 22 having the concentration n.sub.0 shown in FIG. 1 was prepared to measure n.sub.0. A Hall element H.sub.2 shown in FIG. 15B which has the same layer structure as the part of the 2DEG 22 having the concentration n.sub.1 and the 2DHG 21 having the concentration p.sub.1 shown in FIG. 1 was prepared to measure n.sub.1 and p.sub.1. A Hall element H.sub.3 shown in FIG. 15C which has the same layer structure as the part of the 2DEG 22 having the concentration n.sub.2 and the 2DHG 21 having the concentration p.sub.2 shown in FIG. 1 was prepared to measure n.sub.2 and p.sub.2. A Hall element H.sub.4 shown in FIG. 15D which has the same layer structure as the part of the 2DEG 22 having the concentration n.sub.3 shown in FIG. 1 was prepared to measure n.sub.3. FIG. 16A shows electrode arrangement of the Hall elements H.sub.1, H.sub.4 and FIG. 16B shows electrode arrangement of the Hall elements H.sub.2, H.sub.3. FIG. 15A and FIG. 15D show cross-sectional views along a dashed-and-dotted line of FIG. 16A. FIG. 15B and FIG. 15C show cross-sectional views along a dashed-and-dotted line of FIG. 16B. Sizes of the Hall elements H.sub.1˜H.sub.4 were about 4×4 mm.sup.2. As shown in FIG. 16A, in the Hall elements H.sub.1, H.sub.4, four electrodes E.sub.1˜E.sub.4 were formed on the Al.sub.xGa.sub.1-xN layer 12 to measure the concentration of the 2DEG 22. As shown in FIG. 16B, in the Hall elements H.sub.z, H.sub.3, the electrodes E.sub.1˜E.sub.4 were formed on the Al.sub.xGa.sub.1-xN layer 12 to measure the concentration of the 2DEG 22 and further four electrodes E.sub.11˜E.sub.14 were formed on the p-type In.sub.yGa.sub.1-yN layer 15 to measure the concentration of the 2DHG 21. These Hall elements H.sub.1˜H.sub.4 were prepared by the same process as the one used to prepare the normally-off mode polarization super junction GaN-based FET.

[0113] The result of measurement of the concentration n.sub.0, electron mobility μ.sub.e and the resistance R by the Hall element H.sub.1 is shown in table 1.

TABLE-US-00001 TABLE 1 n.sub.0 [cm.sup.−2] UNMEASURABLE μ.sub.e [cm.sup.2/Vs] UNMEASURABLE R [Ω/□] UNMEASURABLE

[0114] The result of measurement of the concentration n.sub.1, electron mobility μ.sub.e and the resistance R by the Hall element H.sub.2 is shown in table 2.

TABLE-US-00002 TABLE 2 n.sub.1 [cm.sup.−2] 4.5 × 10.sup.12 μ.sub.e [cm.sup.2/Vs] 990 R [Ω/□] 1403

[0115] The result of measurement of the concentration p.sub.1, hole mobility μ.sub.p and the resistance R by the Hall element H.sub.2 is shown in table 3.

TABLE-US-00003 TABLE 3 p.sub.1 [cm.sup.−2] 5.1 × 10.sup.12 μ.sub.p [cm.sup.2/Vs] 14 R [kΩ/□] 87.5

[0116] The result of measurement of the concentration n.sub.2, electron mobility μ.sub.e and the resistance R by the Hall element H.sub.3 is shown in table 4.

TABLE-US-00004 TABLE 4 n.sub.2 [cm.sup.−2] 6.5 × 10.sup.12 μ.sub.e [cm.sup.2/Vs] 990 R [Ω/□] 971

[0117] The result of measurement of the concentration p.sub.2, hole mobility μ.sub.p and the resistance R by the Hall element H.sub.3 is shown in table 5.

TABLE-US-00005 TABLE 5 p.sub.2 [cm.sup.−2] 3.1 × 10.sup.12 μ.sub.p [cm.sup.2/Vs] 8.6 R [kΩ/□] 234

[0118] The result of measurement of the concentration n.sub.3, electron mobility μ.sub.e and the resistance R by the Hall element H.sub.4 is shown in table 6.

TABLE-US-00006 TABLE 6 n.sub.3 [cm.sup.−2] 9.1 × 10.sup.12 μ.sub.e [cm.sup.2/Vs] 980 R [Ω/□] 700

[0119] From tables 1˜6, it is understood that n.sub.0≤n.sub.1<n.sub.2<n.sub.3 and p.sub.1>p.sub.2 are certainly satisfied.

[Modes of Usage of the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0120] The normally-off mode polarization super junction GaN-based FET is a 2-gate transistor which operates according to AND. When both of the gate electrode 16 and the gate electrode 20 are on, the drain current flows. When either of the gate electrode 16 and the gate electrode 20 is off, the drain current does not flow. However, since the gate electrode 16 is normally-on, the FET can be operated as a normally-off mode transistor by the gate electrode 20. In this case, three kinds of connecting ways are considered.

[0121] FIG. 17A shows a case where the FET operates as a 3-terminal transistor by connecting the gate electrode 16 and the gate electrode 20. In FIG. 17A, the gate electrode 16 is denoted as G1, the gate electrode 20 is denoted as G0, the source electrode 17 is denoted as S and the drain electrode 18 is denoted as D (hereinafter the same).

[0122] FIG. 17B shows a case where the FET operates like an internal cascode by connecting the gate electrode 16 and the source electrode 17.

[0123] FIG. 17C shows a case where the FET operates as modified cascode by applying a positive voltage to the gate electrode 16 with respect to the source electrode 17.

[0124] The connecting ways shown in FIG. 17A, FIG. 17B and FIG. 17C are logically identical, although transient characteristics upon switching may be different. Therefore, it is possible to change connecting way depending on circuits to which the normally-off mode polarization super junction GaN-based FET is applied.

[0125] FIG. 17D shows a case where the source electrode 17 and the gate electrode 16 and the gate electrode 20 are connected and the FET operates as a diode.

[0126] As described above, according to the first embodiment, it is possible to easily realize a normally-off mode polarization super junction GaN-based FET in which the 2DEG 22 does not exist substantially in the part just below the gate electrode 20 at a non-operating time (thermal equilibrium state) without using complicated circuits such as a cascode circuit or modified cascode circuit using low voltage resistance normally-off mode Si MOS transistors because the FET has the layer structure of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 and further the gate electrode 16 on the p-type In.sub.yGa.sub.1-yN layer 15 and the gate electrode 20 on the p-type In.sub.zGa.sub.1-zN layer 19 on the Al.sub.xGa.sub.1-xN layer 12 and n.sub.0≤n.sub.1<n.sub.2<n.sub.3 and p.sub.1>p.sub.2 are satisfied with respect to the concentration of the 2DEG 22 and the concentration of the 2DHG 21. Furthermore, the normally-off mode polarization super junction GaN-based FET can be used as transistors having various characteristics by choosing connecting way of each terminal or as diodes.

The Second Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0127] As shown in FIG. 18, the normally-off mode polarization super junction GaN-based FET according to the second embodiment is different from the normally-off mode polarization super junction GaN-based FET according to the first embodiment in that the p-type GaN layer 14 does not exist in the polarization super junction region similarly to patent literature 1. Other than the above is the same as the normally-off mode polarization super junction GaN-based FET according to the first embodiment.

[Method for Manufacturing the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0128] The method for manufacturing the normally-off mode polarization super junction GaN-based FET is the same as the method for manufacturing the normally-off mode polarization super junction GaN-based FET according to the first embodiment except that the p-type GaN layer 14 is not finally formed on the undoped GaN layer 13 in the polarization super junction region.

[0129] According to the second embodiment, the same advantage as the first embodiment can be obtained.

The Third Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0130] As shown in FIG. 19, in the normally-off mode polarization super junction GaN-based FET, the gate electrode 20 is provided on the p-type In.sub.zGa.sub.1-zN layer 19 via a gate insulating film 23. That is, a MIS structure is formed by the gate electrode 20, the gate insulating film 23 and the p-type In.sub.zGa.sub.1-zN layer 19. That is, the part of the FET corresponding to the gate electrode 20 forms the MIS structure. Therefore, when a gate voltage not less than +3 V, for example, is applied to the gate electrode 20 to turn on the normally-off mode polarization super junction GaN-based FET from the off-state, even if a part of electron of the 2DEG 22 reaches the p-type In.sub.zGa.sub.1-zN layer 19 through the Al.sub.xGa.sub.1-xN layer 12, it does not reach the gate electrode 20 due to protection by the gate insulating film 23. As a result, it is possible to greatly reduce the gate current flowing through the channel. The gate insulating film 23 may be, for example, inorganic oxides, inorganic nitrides, inorganic oxynitrides and the like. More specifically, the gate insulating film 23 may be, for example, Al.sub.2O.sub.3, SiO.sub.2, AlN, SiN.sub.x, SiON and the like, but not limited to these. The thickness of the gate insulating film 23 is selected as necessary and for example, not smaller than 3 nm and not larger than 100 nm and is typically not smaller than 3 nm and not larger than 30 nm. Other than the above of the normally-off mode polarization super junction GaN-based FET is the same as the normally-off mode polarization super junction GaN-based FET according to the first embodiment.

[0131] FIG. 20A shows an enlarged view of the energy band diagram of the part just below the gate electrode 20 of the normally-off mode polarization super junction GaN-based FET. In FIG. 20A, the gate insulating film 23 is assumed to be SiN.sub.x as an example. In FIG. 20A, E.sub.c denotes the difference (the value of discontinuity of the conduction band) between E.sub.c of the undoped GaN layer 11 and E.sub.c of the Al.sub.xGa.sub.1-xN layer 12 in the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12. FIG. 20B shows the energy band diagram of the part just below the gate electrode 20 of the normally-off mode polarization super junction GaN-based FET according to the first embodiment in which the gate electrode 20 is not provided on the p-type In.sub.zGa.sub.1-zN layer 19 via the gate insulating film 23 and the gate electrode 20 is directly provided on the p-type In.sub.zGa.sub.1-zN layer 19 for comparison with the normally-off mode polarization super junction GaN-based FET. The gate electrode 20 directly provided on the p-type In.sub.zGa.sub.1-zN layer 19 is in Schottky contact with the p-type In.sub.zGa.sub.1-zN layer 19. Comparing FIG. 20A and FIG. 20B, it is understood that the both energy band diagrams are substantially the same. FIG. 21A shows the energy band diagram of the normally-off mode polarization super junction GaN-based FET shown in FIG. 20A when a positive gate voltage V.sub.g is applied to the gate electrode 20. FIG. 21B shows the energy band diagram of the normally-off mode polarization super junction GaN-based FET according to the first embodiment shown in FIG. 20B when a positive gate voltage V.sub.g is applied to the gate electrode 20. The difference between the normally-off mode polarization super junction GaN-based FET shown in FIG. 20A and the normally-off mode polarization super junction GaN-based FET shown in FIG. 20B is only that in the former, the band of the gate insulating film 23 is bent as shown in FIG. 21A when the positive gate voltage V.sub.g is applied and therefore the positive gate voltage V.sub.g larger than that of the normally-off mode polarization super junction GaN-based FET according to the first embodiment shown in FIG. 20B is applied and similarly a larger negative gate voltage V.sub.g is applied when a negative gate voltage V.sub.g is applied.

[Operation Mechanism of the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0132] Operation mechanism of the normally-off mode polarization super junction GaN-based FET is basically the same as operation mechanism of the normally-off mode polarization super junction GaN-based FET according to the first embodiment. [Method for manufacturing the normally-off mode polarization super junction GaN-based FET]

[0133] After the step for forming the source electrode 17 and the drain electrode 18 on the Al.sub.xGa.sub.1-xN layer 12 is implemented as the same as the first embodiment, the gate insulating film 23 is formed on the whole surface. Then, the gate insulating film 23 is etched off except the part on the p-type In.sub.zGa.sub.1-zN layer 19. Then, the gate electrode 16 is formed on the p-type In.sub.yGa.sub.1-yN layer 15 on the p-type GaN layer 14. And the gate electrode 20 is formed on the gate insulating film 23 formed on the p-type In.sub.zGa.sub.1-zN layer 19 on the Al.sub.xGa.sub.1-xN layer 12.

[0134] In this way, the target normally-off mode polarization super junction GaN-based FET shown in FIG. 19 is manufactured.

EXAMPLE

[0135] First, a C-plane sapphire substrate was used as the substrate 10 and a GaN low temperature buffer layer having a thickness of 30 nm, the undoped GaN layer 11 having a thickness of 3000 nm, the Al.sub.xGa.sub.1-xN layer 12 having a thickness of 30 nm and x=0.21, the undoped GaN layer 13 having a thickness of 50 nm and the p-type GaN layer 14 having a thickness of 40 nm and Mg concentration [Mg]=5×10.sup.19 cm.sup.−3 were epitaxially grown in order. The growth temperature of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 was set to 1100° C. As carrier gas during growth, N.sub.2 gas and H.sub.2 gas were used. As the p-type dopant for growing the p-type GaN layer 14, Cp.sub.2 Mg was used.

[0136] Then, the surface of the p-type GaN layer 14 in the device isolation region was masked and etching for device isolation was carried out by ICP-RIE using Cl-based gas until the upper part of the undoped GaN layer 11 was etched.

[0137] Then, the surface of the parts of the p-type GaN layer 14 in the gate electrode contact region and the polarization super junction region was masked and the p-type GaN layer 14, the undoped GaN layer 13 and the Al.sub.xGa.sub.1-xN layer 12 were etched in order until the remained thickness of the Al.sub.xGa.sub.1-xN layer 12 reaches 15 nm.

[0138] Then, the surface of the region except the polarization super junction region was masked and etching was carried out to thin the p-type GaN layer 14 in the polarization super junction region.

[0139] Then, the p-type In.sub.yGa.sub.1-yN layer 15 having a thickness of 5 nm, x=0.18 and [Mg]=1×10.sup.20 cm.sup.−3 by the MOCVD method. The growth temperature of the p-type In.sub.yGa.sub.1-yN layer 15 was set to 950° C. As carrier gas during growth 100% N.sub.2 was used.

[0140] Then, the surface of the parts of the p-type In.sub.yGa.sub.1-yN layer 15 on which the gate electrode 16 and the gate electrode 20 are to be formed was masked and etching was carried out by ICP-RIE using Cl-based gas to leave the p-type In.sub.yGa.sub.1-yN layer 15 only in the region on which the gate electrode 16 and the gate electrode 20 are to be formed.

[0141] Then, the surface of the region except the region on which the source electrode 17 and the drain electrode 18 are to be formed was masked by an SiO.sub.2 film and a Ti/Al/Ni/Au layered film was formed on the source electrode forming part and the drain electrode forming part by the vacuum evaporation method to form the source electrode 17 and the drain electrode 18. Thereafter, ohmic alloy treatment of 800° C. and 60 seconds was carried out in N.sub.2.

[0142] Then, a SiN.sub.x film was formed on the whole surface as the gate insulating film 23. Thereafter, the SiN.sub.x film was etched off except the part on the p-type In.sub.yGa.sub.1-yN layer 15 remained in the part on which the gate electrode 20 is to be formed. Then, the surface of the region except the region on which the gate electrode 16 and the gate electrode 20 are to be formed was masked by an SiO.sub.2 film and a Ti/Ni/Au layered film was formed on the p-type In.sub.yGa.sub.1-yN layer 15 on the p-type GaN layer 14 and on the SiN.sub.x film on the p-type In.sub.yGa.sub.1-yN layer 15 beside the end of the undoped GaN layer 13 on the side of the source electrode 17 on the Al.sub.xGa.sub.1-xN layer 12 by the vacuum evaporation method to form the gate electrode 16 and the gate electrode 20. Thereafter, ohmic alloy treatment of the gate electrode 16 was carried out by carrying out RTA of 500° C. and 100 seconds in N.sub.2. In this case, the p-type In.sub.zGa.sub.1-zN layer 19 was formed by the p-type In.sub.yGa.sub.1-yN layer 15.

[0143] In this way, the normally-off mode polarization super junction GaN-based FET was prepared.

[0144] As described above, according to the third embodiment, it is possible to easily realize a normally-off mode polarization super junction GaN-based FET in which the 2DEG 22 does not exist substantially in the part just below the gate electrode 20 at a non-operating time (thermal equilibrium state) without using complicated circuits such as a cascode circuit or modified cascode circuit using low voltage resistance normally-off mode Si MOS transistors because the FET has the layer structure of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 and further the gate electrode 16 on the p-type In.sub.yGa.sub.1-yN layer 15 and the gate electrode 20 provided on the p-type In.sub.zGa.sub.1-zN layer 19 on the Al.sub.xGa.sub.1-xN layer 12 via the gate insulating film 23 and n.sub.0≤n.sub.1<n.sub.2<n.sub.3 and p.sub.1>p.sub.2 are satisfied with respect to the concentration of the 2DEG 22 and the concentration of the 2DHG 21. In addition, in the normally-off mode polarization super junction GaN-based FET, the MIS structure is formed by the gate electrode 20, the gate insulating film 23 and the p-type In.sub.zGa.sub.1-zN layer 19. Therefore, when a gate voltage not less than +3 V, for example, is applied to the gate electrode 20 to turn on the normally-off mode polarization super junction GaN-based FET from the off-state, it is possible to greatly reduce the gate current flowing through the channel. As a result, it is possible to save energy. Furthermore, the normally-off mode polarization super junction GaN-based FET can be used as transistors having various characteristics by choosing connecting way of each terminal or as diodes.

The Fourth Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0145] As shown in FIG. 22, the normally-off mode polarization super junction GaN-based FET according to the fourth embodiment is different from the normally-off mode polarization super junction GaN-based FET according to the third embodiment in that the p-type GaN layer 14 does not exist in the polarization super junction region as the same as patent literature 1. Other than the above is the same as the normally-off mode polarization super junction GaN-based FET according to the third embodiment.

[Method for Manufacturing the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0146] The method for manufacturing the normally-off mode polarization super junction GaN-based FET is the same as the method for manufacturing the normally-off mode polarization super junction GaN-based FET according to the third embodiment except that the p-type GaN layer 14 is not finally formed on the undoped GaN layer 13 in the polarization super junction region.

[0147] According to the fourth embodiment, the same advantage as the third embodiment can be obtained.

The Fifth Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0148] As shown in FIG. 23, the normally-off mode polarization super junction GaN-based FET according to the fifth embodiment is different from the normally-off mode polarization super junction GaN-based FET according to the third embodiment in that the thickness of the parts of the Al.sub.xGa.sub.1-xN layer 12 on which the source electrode 17 and the drain electrode 18 are provided is the same as or almost the same as the thickness of the part of the Al.sub.xGa.sub.1-xN layer 12 on which the undoped GaN layer 13 is provided. Other than the above is the same as the normally-off mode polarization super junction GaN-based FET according to the third embodiment.

[Method for Manufacturing the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0149] According to the method for manufacturing the normally-off mode polarization super junction GaN-based FET, the p-type GaN layer 14 is etched to the depth midway in its thickness direction to thin it and an Al.sub.xGa.sub.1-xN layer having the predetermined thickness is epitaxially grown by using the MOCVD method and the like before the p-type In.sub.yGa.sub.1-yN layer 15 is epitaxially grown. Thereafter, the Al.sub.xGa.sub.1-xN layer is patterned to remain it only on the parts of the Al.sub.xGa.sub.1-xN layer 12 on which the source electrode 17 and the drain electrode 18 are to be formed. Other than the above is the same as the method for manufacturing the normally-off mode polarization super junction GaN-based FET according to the third embodiment. This patterning can be carried out by etching by, for example, the RIE method and the like. The thickness of the Al.sub.xGa.sub.1-xN layer is the same as or almost the same as the value which is obtained by subtracting the thickness of the parts of the Al.sub.xGa.sub.1-xN layer 12 on which the source electrode 17 and the drain electrode 18 are to be formed from the thickness of the part of the Al.sub.xGa.sub.1-xN layer 12 below the undoped GaN layer 13. With this, the source electrode 17 and the drain electrode 18 can be formed on the Al.sub.xGa.sub.1-xN layer 12 having the same thickness as the thickness of the part of the Al.sub.xGa.sub.1-xN layer 12 below the undoped GaN layer 13.

[0150] According to the fifth embodiment, the same advantage as the third embodiment can be obtained.

[0151] Heretofore, embodiments and examples of the present invention have been explained specifically. However, the present invention is not limited to these embodiments and examples, but contemplates various changes and modifications based on the technical idea of the present invention.

[0152] For example, numerical numbers, structures, shapes, materials and the like presented in the aforementioned embodiments and examples are only examples, and the different numerical numbers, structures, shapes, materials and the like may be used as needed.

EXPLANATION OF REFERENCE NUMERALS

[0153] 10 Substrate [0154] 11 Undoped GaN layer [0155] 12 Al.sub.xGa.sub.1-xN layer [0156] 13 Undoped GaN layer [0157] 14 p-type GaN layer [0158] 15 p-type In.sub.yGa.sub.1-yN layer [0159] 16 Gate electrode [0160] 17 Source electrode [0161] 18 Drain electrode [0162] 19 p-type In.sub.zGa.sub.1-zN layer [0163] 20 Gate electrode [0164] 21 2DHG [0165] 22 2DEG [0166] 23 Gate insulating film