Method of Manufacturing a Component Carrier and a Component Carrier

Abstract

A method for manufacturing a component carrier includes covering a dielectric layer structure by a metal foil, forming an electroless metal layer on the metal foil, and forming a multi-stage electroplating structure on the electroless metal layer. A component carrier made by the method is further described.

Claims

1. A method of manufacturing a component carrier, comprising: covering a dielectric layer structure by a metal foil; forming an electroless metal layer on the metal foil; and forming a multi-stage electroplating structure on the electroless metal layer.

2. The method according to claim 1, further comprising: attaching the dielectric layer structure covered by the metal foil as a preformed double layer structure to a base.

3. The method according to claim 1, further comprising: forming the electroless metal layer by a chemical process.

4. The method according to claim 1, further comprising: forming the multi-stage electroplating structure by flash plating followed by pattern plating.

5. The method according to claim 1, further comprising: patterning the dielectric layer structure covered by the metal foil, in particular to expose a base on which the dielectric layer structure is formed by forming a laser via in the patterned dielectric layer structure covered by the metal foil.

6. The method according to claim 1, further comprising: forming at least one of the electroless metal layer and at least part of the multi-stage electroplating structure in a horizontal plating line.

7. The method according to claim 1, further comprising: structuring the metal foil, the electroless metal layer, and the multi-stage electroplating structure together, in particular using a lithographic dry film process.

8. The method according to claim 1, further comprising: forming a dielectric pattern on a bottom-sided flash plating structure of the multi-stage electroplating structure, and forming the dielectric pattern to extend through a top-sided pattern plating structure of the multi-stage electroplating structure.

9. A component carrier, comprising: a dielectric layer structure, covered by a metal foil; an electroless metal layer on the metal foil; and a multi-stage electroplating structure on the electroless metal layer.

10. The component carrier according to claim 9, wherein the dielectric layer structure, covered by the metal foil, is formed on only part of a base; and wherein the electroless metal layer is formed partially on the metal foil and partially on the base.

11. The component carrier according to claim 9, wherein the dielectric layer structure and the metal foil are patterned, in particular to expose a base by a via extending through the patterned dielectric layer structure and the patterned metal foil.

12. The component carrier according to claim 11, wherein the via is at least partially filled by part of the electroless metal layer and by part of the multi-stage electroplating structure.

13. The component carrier according to claim 11, wherein the multi-stage electroplating structure has a larger thickness in the via compared to a smaller thickness above the dielectric layer structure.

14. The component carrier according to claim 10, wherein the base comprises a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure.

15. The component carrier according to claim 9, wherein the metal foil has a thickness of less than 5 μm, in particular of not more than 3 μm.

16. The component carrier according to claim 9, wherein the electroless metal layer has a thickness of not more than 2 μm, in particular a thickness in a range from 1 μm to 1.5 μm.

17. The component carrier according to claim 9, wherein the multi-stage electroplating structure has a maximum thickness of at least 10 μm, in particular of at least 20 μm.

18. The component carrier according to claim 9, wherein a pattern plating structure of the multi-stage electroplating structure has a thickness of at least 5 times of a thickness of a flash plating structure of the multi-stage electroplating structure.

19. The component carrier according to claim 9, wherein the metal foil, the electroless metal layer and the multi-stage electroplating structure form an electrically conductive structure with a line/space ratio of not more than 20 μm/20 μm, in particular of not more than 15 μm/15 μm.

20. The component carrier according to claim 19, comprising at least one of the following features: wherein the electrically conductive structure is a trace; wherein the electrically conductive structure is free of an undercut.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG. 1 illustrates a cross-sectional view of a component carrier according to an exemplary embodiment of the invention.

[0050] FIG. 2 illustrates a flowchart of a method of manufacturing a component carrier according to an exemplary embodiment of the invention.

[0051] FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 show structures obtained during carrying out a method of manufacturing a component carrier, illustrated in FIG. 8, according to an exemplary embodiment of the invention.

[0052] FIG. 9, FIG. 10, FIG. 11, FIG. 12, and FIG. 13 show images with cross-sectional views of portions of component carriers according to exemplary embodiments of the invention.

[0053] FIG. 14 illustrates a cross-sectional view of a component carrier having traces with small line/space ratio according to an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

[0054] The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.

[0055] Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.

[0056] Conventionally, a trace of a component carrier may be produced by an SAP (semi additive processing) process flow to obtain a relatively small line/space ratio. During a corresponding manufacturing process, it may be possible to apply a vertical electroless plating process to induce an electroless plating layer on a resin sheet laminate. Such a conventional manufacturing process may involve a risk of skip plating in an electroless plating layer and may cause layer separation or voids in an interior of an electrically conductive structure. Furthermore, such an SAP manufacturing process may be limited to thick cores to prevent panel warpage in a vertical electroless plating tank. Such a conventional approach may also require fixing of a plate or another preform of component carriers in a dedicated frame holder.

[0057] According to an exemplary embodiment of the invention, a component carrier (such as a PCB) is provided which comprises a double layer of a dielectric layer structure and a thin metal foil. An electroless metal layer and a multi-stage electroplating structure on the electroless metal layer may be formed subsequently on the double layer (and preferably in a via neighbored to the double layer). This may allow to create a trace of a component carrier with extremely small line/space ratio, with excellent spatial and geometric accuracy and with very small or even no undercut. Advantageously, such a manufacturing architecture may in particular allow to obtain a line/space ratio of 20 μm/20 μm or less thanks to the use of high build electroless plating in combination with an ultra-thin copper foil and due to the use of a horizontal flash copper plating line.

[0058] In particular, an exemplary embodiment of the invention provides an mSAP (modified semi additive processing) process flow to produce traces with a line/space ratio of 20 μm/20 μm or less. Advantageously, exemplary embodiments of the invention may utilize high build electroless plating with medium deposition rate on a thin copper foil which can be produced in a horizontal electroless plating line with no capacity impact. In particular, it may be advantageous to utilize an ultra-thin copper foil with a prepreg in a stack-up in order not to remove strike plating for better reliability and to improve a trace width undercut behavior. Beyond this, exemplary embodiments may make it possible to carry out a micro etch process on a flash copper plating layer before dry film lamination and pattern plating to enhance reliability performance. Preferably, a combination of medium deposition of high build electroless with an ultra-thin copper foil and strike plating may lead to an optimum base copper thickness which will not impact a 20 μm line shape after etching. Further advantageously, exemplary embodiments of the invention involve only a low risk of skip plating with an additional layer of flash copper plating as bonding enhancement layer for inter-layer connection. Furthermore, there is substantially no restriction of panel thickness when producing component carriers in a horizontal electroless plating line, since there may be no warpage caused by a frame holder. An exemplary embodiment of the invention may make it possible to produce a 20 μm/20 μm line and space with an mSAP process stack-up with a layer of flash copper plating as secure bonding between an electroless plating layer and an electroplating layer.

[0059] Conventional SAP processes capable of producing component carriers with low line/space ratio may require a substantial extra effort for a vertical high build electroless plating line and also the development and execution of complex processes. Apart from the high effort, the capacity of such a conventional manufacturing method may be low and the reliability risk may be high.

[0060] By implementing a high build electroless process to a horizontal plating line and by utilizing an ultra-thin copper foil, it may be possible to efficiently utilize mSAP processes for obtaining a low line/space ratio. This may be done with reasonable effort, high capacity and a low reliability risk. Consequently, component carriers with extreme demanding line and space patterning requirements may be produced. Exemplary applications of exemplary embodiments of the invention are component carriers for mobile phones and for modules (in particular comprising a plurality of embedded and/or surface mounted interacting components). Component carriers according to exemplary embodiments of the invention may be manufactured in a compact way.

[0061] Exemplary embodiments of the invention may be implemented with a horizontal high build electroless plating process rather than with a vertical high build electroless plating process for reducing the effort in terms of manufacturing component carriers with low line/space ratio. This may allow to manufacture printed circuit boards in mSAP design. In particular, a layer of flash copper may be plated on a component carrier with small line/space ratio around a laser via hole surface area. Hence, a fine line or space capability improvement may be achieved by horizontal high build electroless plating.

[0062] A conventional way to produce component carriers with small line/space ratio needs high deposition electroless plating that can only be done in a technically and economically feasible way in a vertical plating line. Assuming theoretically a high build electroless plating stage for an SAP process with horizontal line, due to the high required thickness the speed will be super slow and the process line will be super long. Hence, the involved effort is not effective and not feasible for mass production. In such conventional approaches, no copper foil and strike plating processes are carried out to keep the base copper low in order to achieve a good shape after etching.

[0063] In contrast to this, there may be no need for a vertical high build electroless equipment according to exemplary embodiments of the invention. Exemplary embodiments may allow to execute horizontal electroless plating with no capacity impact. Horizontal electroless plating may be preferred, because this may allow to utilize a simple line setup for an mSAP process without sophisticated changes. Furthermore, there may be less space demand, and productivity may be higher. Apart from this, a horizontal line process may be a continuous process with a flood bar closer to the panel surface. Via holes bottom properties may be better. It may also be possible to connect an electroless module directly to an electrolytic plater and perform strike plating in line. A vertical line may normally produce in bulk or—if applied as continuous plating line—may need a large space. In conventional approaches, via bottom behaviour may be poor in a batch process, and such a line cannot be arranged in-line with an electrolytic plater in conventional systems. Furthermore, exemplary embodiments of the invention may keep the copper foil and the strike copper in the stack-up, which may lead to a high reliability.

[0064] In contrast to conventional mSAP processes for manufacturing traces of component carriers, exemplary embodiments of the invention may simply require a chemistry change without a fundamental hardware change so that a fine line trace may be manufactured with low effort. In particular the use of a resin-copper-double sheet connected to a layer stack on which a fine line trace is to be formed as well as the execution of an additional flash etching process in terms of electroplating may lead to advantageous properties of a manufactured component carrier. Advantageously, very straight traces without undercut may be obtained.

[0065] FIG. 1 illustrates a cross-sectional view of a component carrier 100 according to an exemplary embodiment of the invention.

[0066] The component carrier 100 according to FIG. 1 may be configured as a substantially plate-shaped printed circuit board (PCB). Thus, the component carrier 100 shown in FIG. 1 may be highly compact in a vertical direction. More specifically, the component carrier 100 may comprise a base 106 comprising one or more electrically conductive layer structures 118 and/or one or more electrically insulating layer structures 120. Each of the electrically conductive layer structures 118 may comprise a layer section and vertical through connections, for example copper filled vias which may be created by drilling and plating. The electrically insulating layer structure(s) 120 may comprise a respective resin (such as a respective epoxy resin), preferably comprising reinforcing particles therein (for instance glass fibers or glass spheres). For instance, the electrically insulating layer structures 120 may be made of FR4. Thus, the base 106 comprises a laminated layer stack comprising one or more electrically conductive layer structures 118 and one or more electrically insulating layer structures 120.

[0067] Again referring to FIG. 1, the component carrier 100 comprises a dielectric layer structure 102, covered by a metal foil 104, on at least of part of the base 106. For instance, the dielectric layer structure 102 may be a resin layer (for example may be formed of epoxy resin) or may comprise resin and reinforcing particles (for instance may be formed as prepreg). The metal foil 104 on the dielectric layer structure 102 may be an ultra-thin copper foil having a thickness of for instance 3 μm. The dielectric layer structure 102 and the metal foil 104 may be provided as a common semifinished product, i.e., as a prefabricated double layer, such as copper cladded resin. As shown, the mentioned double layer is structured, which is accomplished in the shown embodiment by the formation of a laser via 114 extending through both the dielectric layer structure 102 and the metal foil 104 for exposing a central portion of base 106. Hence, the dielectric layer structure 102 and the metal foil 104 are patterned to thereby expose a portion of the base 106. This is accomplished by creating laser via 114 in the patterned dielectric layer structure 102 covered by the metal foil 104.

[0068] Furthermore, an electroless metal layer 108 is formed partially on the metal foil 104 (where present) and partially on the base 106 (where exposed).

[0069] Apart from this, a multi-stage electroplating structure 110 is formed on the electroless metal layer 108. The multi-stage electroplating structure 110 is composed of a flash plating structure 124 formed directly on the electroless metal layer 108, and a pattern plating structure 122 formed directly on the flash plating structure 124.

[0070] Apart from the laser via 114, the metal foil 104, the electroless metal layer 108, the flash plating structure 124 and the pattern plating structure 122 form a stack of parallel layers. In contrast to this, in the laser via 114 and consequently directly on base 106, the metal layer 104 is absent, electroless metal layer 108 and flash plating structure 124 constitute a substantially U-shaped double layer, and pattern plating structure 122 fills up the rest of the laser via 114. Consequently, the laser via 114 is completely filled by the electroless metal layer 108 and the multi-stage electroplating structure 110.

[0071] Next, the thicknesses of the various layer structures shown in FIG. 1 will be explained. Inside of the laser via 114, the multi-stage electroplating structure 110 may have a maximum thickness d1 of at least 20 μm, for example 25 μm. Moreover, the multi-stage electroplating structure 110 may have a larger thickness d1 in the laser via 114 compared to a smaller thickness d2 above the dielectric layer structure 102. For example, d2 may be at least 15 μm, for example 20 μm. Advantageously, the metal foil 104 has a thickness d3 of not more than 4 μm, preferably 3 μm. Still referring to FIG. 1, the electroless metal layer 108 may have a thickness d4 in a range from 1 μm to 1.5 μm, for example 1.2 μm. What concerns the pattern plating structure 122 of the multi-stage electroplating structure 110, it may have a thickness d5 of more than 5 times of a thickness d6 of a flash plating structure 124 of the multi-stage electroplating structure 110.

[0072] Advantageously, the metal foil 104, the electroless metal layer 108 and the multi-stage electroplating structure 110 form an electrically conductive structure 126 with a line/space ratio of not more than 20 μm/20 μm. The created electrically conductive structure 126 may be a trace. Due to the arrangement shown in FIG. 1 and as a result of the executed manufacturing methods, the electrically conductive structure 126 is free of an undercut at its bottom side.

[0073] FIG. 1 shows as well that component carrier 100 comprises a dielectric pattern 128 on top of the flash plating structure 124 and extending through the top-sided pattern plating structure 122 of the multi-stage electroplating structure 110. For instance, dielectric pattern 128 may be a structured dry film.

[0074] As shown as well, an opening 130 extends vertically through the multi-stage electroplating structure 110, the electroless metal layer 108 and the metal foil 104 for exposing the dielectric layer structure 102. A corresponding etching process may define a lateral limit of an electrically conductive structure 126 to be created.

[0075] Electrically conductive structure 126 embodied as horizontal trace may have an advantageously low line/space ratio of not more than 20 μm/20 μm, preferably of not more than 15 μm/15 μm. An undesired undercut on the bottom side of the metal foil 104 may be reliably prevented. The trace may be created with high spatial accuracy and with a simple manufacturing process. Manufacturability of the component carrier 100 according to FIG. 1 using a horizontal electroless plating line may be simple and without capacity impact. The low thickness of the metal foil 104 may lead to a proper reliability. The synergetic combination of the high-thickness electroless metal layer 108 with the formation of the flash plating structure 124 by flash or strike plating may lead to an optimal base copper thickness below pattern plating structure 122, which may promote, in turn, a low line/space ratio. Undesired phenomena such as delamination of the individual layers and warpage of the component carrier 100 as a whole may be reliably prevented. Consequently, there is also substantially no restriction in terms of panel thickness.

[0076] A person skilled in the art will understand that the different metal structures of component carrier 100 according to FIG. 1 may be distinguished visually when inspecting a cross-sectional image thereof (in particular based on grain boundaries between the various layers).

[0077] The component carrier 100 shown in FIG. 1 may be manufactured as will be described in the following referring to FIG. 2.

[0078] FIG. 2 illustrates a flowchart 200 of a method of manufacturing a component carrier 100 according to an exemplary embodiment of the invention.

[0079] Referring to a block 202, the method may comprise forming a thin foil layup and executing lamination.

[0080] Referring to a block 204, the method may comprise provision of a bond film.

[0081] Referring to a block 206, the method may comprise forming a laser via.

[0082] Referring to a block 208, the method may comprise removing the bond film.

[0083] Referring to a block 210, the method may comprise carrying out a desmear process.

[0084] Referring to a block 212, the method may comprise executing high build electroless plating (for instance for forming an electroless plating layer having a thickness of 0.9 μm).

[0085] Referring to a block 214, the method may comprise execution of a pre-clean process and of a dry-film lamination process.

[0086] Referring to a block 216, the method may comprise a process of exposing a trace pattern.

[0087] Referring to a block 218, the method may comprise a developing process.

[0088] Referring to a block 220, the method may comprise pattern plating (for instance at a thickness of 20 μm).

[0089] Referring to a block 222, the method may comprise dry-film stripping.

[0090] Referring to a block 224, the method may comprise flash etching.

[0091] Thus, an exemplary embodiment of the invention may relate to an mSAP process for forming an electrically conductive structure 126 with a line/space ratio of for example 20 μm/20 μm. Such an mSAP process may use a copper foil and a prepreg sheet for providing a buildup layer. Furthermore, such an mSAP process may be based on the provision of a copper foil, a high build electroless structure on top, followed by strike plating. Advantageously, it may be possible to carry out a horizontal electroless plating process for creating a high build electroless plating layer on a copper foil layer. Moreover, a micro etch may be applied on the electroless plating layer before dry film lamination and pattern plating.

[0092] It may be preferred to execute a pre-curing process after build up film lamination. Furthermore, bond film provision and bond film removal may be applied before and after laser processing. Furthermore, it may be possible to apply a horizontal high build electroless plating process on each copper foil build layer. Beyond this, a micro etch may be applied on the electroless plating layer before dry film lamination and pattern plating.

[0093] FIG. 3 to FIG. 8 show structures obtained during carrying out a method of manufacturing a component carrier 100, illustrated in FIG. 8, according to an exemplary embodiment of the invention.

[0094] Referring to FIG. 3, a dielectric layer structure 102 (for example a prepreg sheet having a thickness of 25 μm), covered by metal foil 104 (for example a copper foil), is formed on a base 106. Preferably, the dielectric layer structure 102 covered by the metal foil 104 is attached as a preformed double layer structure to the base 106. Further preferably, the metal foil 104 is very thin, for instance has a vertical thickness of 2 μm.

[0095] Referring to FIG. 4, the dielectric layer structure 102, covered by the metal foil 104, is patterned by laser drilling. Consequently, a central portion of the base 106 is exposed by forming a laser via 114 extending entirely through the patterned dielectric layer structure 102 and extending entirely through the metal foil 104.

[0096] Referring to FIG. 5, an electroless metal layer 108 (for example a copper layer) is formed on the metal foil 104 and on an exposed portion of base 106 by electroless plating. Preferably, the electroless metal layer 108 is formed by a chemical process, for instance as chemical copper. The electroless metal layer 108 may be quite thick, for instance may have a thickness of 1.5 μm. Advantageously, the electroless metal layer 108 may be created in a horizontal plating line, i.e., with a corresponding panel being oriented horizontally during the electroless deposition process in an appropriate chemical bath for forming the electroless metal layer 108. Descriptively speaking, the electroless metal layer 108 may cover a region on and around the laser via 114 in order to prepare the shown structure for subsequent flash plating.

[0097] Referring to FIG. 6, a flash plating structure 124 is deposited by flash plating, for example with a thickness of less than 2 μm, on the exposed surface of the structure shown in FIG. 5. For forming the flash plating layer 124, the structure of FIG. 5 may be put in a chemical bath for depositing flash plating layer 124 by galvanic plating (including applying electric current). During flash plating, a current density may be set to a very low value or may even be minimized. This may promote a low line/space ratio of a trace of the readily manufactured component carrier 100 shown in FIG. 8. The formation of the flash plating structure 124 prior to and in addition to a pattern plating structure 122 of multi-stage electroplating structure 110 (see FIG. 7) simplifies handling, reduces the risk of delamination and thereby improves reliability.

[0098] Referring to FIG. 7, a dielectric pattern 128, for instance made of a dry film or another electrically insulating material, is formed on a part of the electroless metal layer 108. This may involve a pattern expose and develop process.

[0099] Thereafter, formation of multi-stage electroplating structure 110 on the electroless metal layer 108 is completed by forming pattern plating structure 122 by galvanic plating on the exposed surface of the flash plating structure 124 which is not covered by dielectric pattern 128. Formation of pattern plating structure 122 may be accomplished by galvanic plating and fills up the laser via 114 entirely (as shown) or partially (not shown). The process of forming pattern plating structure 122 takes longer than the process of forming flash plating structure 124. The galvanic plating process of forming pattern plating structure 122 is executed with a larger current density than the process of forming flash plating structure 124. When formation of the multi-stage electroplating structure 110 is completed, the dielectric pattern 128 extends through a top part of the multi-stage electroplating structure 110, i.e., is arranged on top of flash plating structure 124 and is surrounded by pattern plating structure 122. Hence, the multi-stage electroplating structure 110 may be formed by flash plating followed by selective pattern plating. Advantageously, the multi-stage electroplating structure 110 may be created in a horizontal plating line.

[0100] Referring to FIG. 8, the metal foil 104, the electroless metal layer 108 and the multi-stage electroplating structure 110 may then be patterned together for forming opening 130 using a lithographic dry film process. As a result, opening 130 is formed which extends through the multi-stage electroplating structure 110, the electroless metal layer 108 and the metal foil 104 for exposing a portion the base 106. This may involve a dry film strip and flash etch process. Consequently, in electrically conductive structure 126 may be formed in and/or around the laser via 114 and may be laterally delimited.

[0101] FIG. 9 to FIG. 13 show images with cross-sectional views of portions of component carriers 100 according to exemplary embodiments of the invention.

[0102] Referring to FIG. 9 and referring to FIG. 10, cross-sections of traces manufactured as electrically conductive structures 126 forming part of a component carrier 100 according to exemplary embodiments of the invention are shown.

[0103] FIG. 9 shows two adjacent trace-type electrically conductive structures 126 being formed with a line/space ratio of about 20 μm/20 μm.

[0104] FIG. 10 shows, with reference sign 136, a flash copper layer in the trace.

[0105] Referring to FIG. 11, a cross-sectional view of an electrically conductive structure 126 of a component carrier 100 according to an exemplary embodiment of the invention is illustrated, which has been manufactured with an mSAP process. As shown with reference sign 138, a target pad is visible. As shown with reference sign 140, an electroless copper layer can be distinguished. As shown with reference sign 142, a copper flash layer is present. As shown with reference sign 144, electroplating copper is provided.

[0106] Referring to FIG. 12, cross-sections of traces manufactured as electrically conductive structure 126 forming part of a component carrier 100 according to an exemplary embodiment of the invention are shown. The line/space ratio is about 20 μm/20 μm.

[0107] Referring to FIG. 13, a cross-section of a trace manufactured as electrically conductive structure 126 forming part of a component carrier 100 according to an exemplary embodiment of the invention is shown. A flash copper line in the copper layer is shown with reference sign 136.

[0108] FIG. 14 illustrates a cross-sectional view of a component carrier 100 having traces as electrically conductive structures 126 with a small line/space ratio of 20 μm/20 μm according to an exemplary embodiment of the invention. The illustrated layer stack can be manufactured as described above.

[0109] As shown, electroless metal layer 108 may be utilized as high build electroless structure with medium deposition which can be produced at a horizontal plating line with no capacity impact.

[0110] Furthermore, it may be advantageously possible to utilize a metal foil 104 (preferably a copper foil) in the stack-up in order not to remove material formed by strike plating (i.e., flash plating structure 124, such as a flash copper plating structure) for better reliability. The copper foil in the stack-up may be used to avoid removing the strike plating structure: Strike plating or flash plating may require filling the via holes and plating the panel surface at the same time. In order to balance the plating thickness, the plating chemistry may contain ions for etching the copper plated on the surface at the same time when filling the vias. Without copper foil, this may be difficult or even impossible because the electroless layer may be too thin.

[0111] Advantageously, the illustrated traces may be formed by a combination of medium deposition of high build electroless with an ultra-thin copper foil and strike plating, which may lead to an optimum base copper thickness. Advantageously, this may not impact the 20 μm line shape after etching.

[0112] It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

[0113] Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants are possible which variants use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.