FAULT CURRENT BYPASS BASED SOLID STATE CIRCUIT BREAKERS AND ACTIVE CLAMPING SNUBBERS FOR DC CIRCUIT BREAKERS

Abstract

A thyristor-based dc solid state circuit breaker (SSCB) named Y-type includes a new complementary commutation circuit including a capacitor-capacitor pair, which features three advantages. First, a fast commutation is achieved using a countercurrent pulse injection by the capacitor-capacitor pair structure. Second, metal-oxide varistors (MOVs) are disconnected from the power line when SSCB is OFF, which solves the reliability issue due to the MOV degradation and enhances the voltage utilization rate of the main switch. Third, benefiting from the capacitor-capacitor pair structure, reliable reclosing and rebreaking are obtained for practical applications.

Claims

1. AY-Type Thyristor-Based DC solid state circuit breaker (Y-SSCB) comprising: a first capacitor; a first resistor; and a metal oxide varistor; wherein the first capacitor, first resistor, and metal oxide varistor are in parallel; a main thyristor and an auxiliary thyristor, wherein the metal oxide varistor is connected to an anode of the main thyristor and auxiliary thyristor; a first diode and second capacitor in parallel with one another and connected to a cathode of the main thyristor and auxiliary thyristor; and a second diode connected to a cathode of the auxiliary thyristor.

2. The Y-SSCB of claim 1, wherein a DC voltage is connected to the first capacitor, first resistor, and metal oxide varistor.

3. The Y-SSCB of claim 2, wherein a line conductor and line resistor in series are connected in series to the first diode and second capacitor.

4. The Y-SSCB of claim 1, wherein the second capacitor is charged by a DC voltage and obtains complementary commutation in the main thyristor during DC current interruption.

5. The Y-SSCB of claim 4, wherein the first capacitor achieves a turn-OFF in the auxiliary thyristor.

6. The Y-SSCB of claim 1, further comprising a second resistor in series with the second diode and connected to the auxiliary thyristor, wherein the first capacitor turns off the auxiliary thyristor and the second does not contribute to the turning off.

7. The Y-SSCB of claim 6, wherein the second capacitor charges through the second diode and second resistor.

8. The Y-SSCB of claim 7, wherein the second resistor limits oscillation within the Y-SSCB when the main thyristor turns on.

9. The Y-SSCB of claim 8, wherein second resistor reduces current peak imposed on a DC source during current interruption.

10. The Y-SSCB of claim 9, wherein the second resistor has a resistance in the tens of ohms.

11. The Y-SSCB of claim 1, wherein the Y-SSCB is ready for re-breaking after a fault in a maximum range of hundreds of milliseconds.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIGS. 1(a) to 1(d) show active thyristor-based SSCBs: active resonance (AR) presented in FIGS. 1(a) and 1(b), load-commutation switch (LCS) indicated in FIG. 1(c), and complementary commutation (CC) shown in FIG. 1(d).

[0015] FIG. 2 shows the Y-SSCB in a typical dc system.

[0016] FIG. 3 shows the proposed Y-SSCB and the SSCB during the current commutation.

[0017] FIG. 4 shows Sa turn-OFF process in the proposed Y-SSCB and the breaker in the prior art

[0018] FIG. 5 shows the reclosing process in the proposed Y-SSCB and breaker in Shu.

[0019] FIG. 6 shows 8 operating modes of the proposed Y-SSCB during a short-circuit fault current interruption.

[0020] FIG. 7 shows critical current and voltage waveforms of the proposed Y-SSCB during a fault isolation.

[0021] FIG. 8 shows a proposed Y-SSCB during reverse recovery process.

[0022] FIG. 9 shows bidirectional topologies: proposed Y-SSCB (left) and SSCB in Shu (right).

[0023] FIG. 10 shows a 400 V/120 A Y-SSCB prototype and the dc test circuits diagram.

[0024] FIG. 11 shows experimental results: line current (idc) and voltage across Sm (vSm). SSCB conducts 8 A load current in a steady state; a short circuit is created at t=0.175 ms; fault current interruption begins at t=1.57 ms; dc current begins to decay at t=1.65 ms and reaches zero at t=2.6 ms.

[0025] FIG. 12 shows experimental results: Sm current iSm and voltage vSm during dc current interruption. Results are consistent with the analysis in Section II-B and FIG. 3.

[0026] FIG. 13 shows experimental results: the voltages across Sm, C1, and C2 are shown. Sm voltage follows vSm=vC1+(Rs×If)−vC2. The circuit turn-OFF time tcc for Sm shows 57.7 μs, which is sufficient for the selected thyristor. Voltage on C1 is clamped to 740 V and C2 is prevented to be reversely charged.

[0027] FIG. 14 shows experimental results: Sa current iSa during dc current interruption.

[0028] FIG. 15 shows experimental results: Sa voltage vSa during dc current interruption.

[0029] FIG. 16 shows experimental results: the operating duty of reclosing and rebreaking.

[0030] FIG. 17 shows Table 1.

[0031] FIG. 18 shows Table 2.

[0032] FIG. 19 shows Table 3.

[0033] FIG. 20 shows Table 4.

[0034] FIG. 21 shows Table 5.

DETAILED DESCRIPTION OF THE EMBODIMENTS

II. Capacitor-Capacitor Pair Concept in Y-SSCB: Achieving Reliability During Reclosing

[0035] A. Proposed Y-SSCB

[0036] FIG. 2 shows the Y-SSCB in a typical dc system. The proposed Y-SSCB benefits from a capacitor-capacitor (C1-C2) pair, which may have two functions. First, C2 is charged by the dc system, and its energy obtains a CC in Sm during dc current interruption. Second, C1 helps to achieve a natural turn-OFF in Sa. In addition to performing a fast fault current isolation, the Y-SSCB can operate under the operating duty of reclosing and rebreaking. In this case, C1-C2 pair presents higher reliability compared with the single capacitor used in Shu and justifies the effectiveness of the SSCB in practice. This is further elaborated in Section II-C.

[0037] B. Main Thyristor Turn-Off Dynamic in CC-Based SSCBs

[0038] Thyristor turn-OFF dynamic in CC-based SSCBs is analyzed in this section for two reasons. First, the parameters impacting the forward blocking in the main thyristor Sm are reviewed. Second, transient voltage and current values imposed on the main thyristor Sm and auxiliary thyristor Sa are studied.

[0039] FIG. 3 shows the proposed Y-SSCB and the SSCB in Shu during the current commutation; also, critical waveforms are shown. The commutation process is almost the same for both SSCBs, but Sa turn-OFF and reclosing scenarios are different and explained in Section II-C.

[0040] Before t=ta, Sm is ON and conducts Idc; Sa is OFF (vSa=Vdc).

[0041] Interval ta≤t<tb: Sa turns ON at t=ta to obtain commutation in Sm. iSa starts rising, and iSm begins decaying at the same time.

[0042] Interval tb≤t<tc: At t=tb, iSm=0. Then, iSm continues to be negative due to carriers stored in semiconductor layers of Sm.

[0043] Interval tc≤t<td: iSm=IRM at t=tc, where about 60% of stored charges are swept away from outer junctions of Sm; iSa reaches the peak value of |Ip|=|IRM|+|Idc|. IRM is device dependent and circuit-dependent, and it can be described as follows:

IRM=f(Vdc,Idc,Ls,Rs,QRR,Δtbd)  (EQ. 1)

[0044] where Ls and Rs are parasitic inductance and resistance in the current commutation loop, respectively; QRR is the recovered charge in Sm layers; and Δtbd=td−tb. As the density of carriers around outer layers of Sm decreases, iSm begins to return to zero.

[0045] Also, as shown in FIG. 3, vSm undergoes an undershoot to Vp. of Sm are removed, and these junctions start to block the negative voltage; in this case, iSm is close to zero. Time interval trr=td−tb is defined as reverse recovery time. However, carriers in the inner junction have no way to external circuits. These trapped carriers are decaying only by recombination, which needs a negative voltage across Sm. The time period tgr=te−td stands for the gate recovery time in which recombination completes.

[0046] Sm regains its forward blocking capability if reverse recovery and recombination are complete in order. So, thyristor turn-OFF time is tq=trr+tgr. In practice, vSm is designed to be negative for t tcc, where tcc=tf−tb; tcc and tq are labeled in FIG. 3.

[0047] C. Sa Turn-Off Process, Reclosing Under Reliability

[0048] Both capacitor-capacitor pair structure and single capacitor can achieve a complete commutation in Sm; however, SSCB in Shu suffers from low reliability during reclosing and leaves the system without any protection for a considerable period.

[0049] FIG. 4 shows Sa turn-OFF process in the proposed Y-SSCB and the breaker in Shu. In the proposed Y-SSCB, C1 primarily helps to turn Sa OFF, and resistor R2 does not need to contribute to this process. In contrast, for the SSCB in Shu, R1 needs to reduce Sa current below its holding current (IH), meaning iSa=Vdc/R1<IH. In this case, R1 is in the range of hundreds of kΩ.

[0050] FIG. 5 indicates the reclosing process in both SSCBs. For YSSCB, capacitorC2 charges throughD2 and resistor R2. R2 helps to limit current oscillation in the system when Sm turns ON. Also, it reduces the current peak imposed on dc source during current interruption. R2 depends on Vdc and maximum fault current, but its value remains in the range of tens of Ω. Therefore, Y-SSCB is ready (C2 is charged) for rebreaking after a few milliseconds.

[0051] However, for SSCB in Shu, C1 charges through R1, where R1 has been predetermined by Sa turn-OFF process. In this case, the charging time of C1 is in the range of hundreds of milliseconds to a few seconds. In other words, after turning ON Sm (reclosing), SSCB in Shu cannot rebreak faults (as C1 is not charged) for a substantial interval and does not fulfill IEC-62271-100.

III. Proposed Y-SSCB: Working Principle and Design Procedure

[0052] A. Working Principle

[0053] FIG. 6 shows operating modes and FIG. 7 indicates the critical waveforms of the Y-SSCB during a short-circuit fault current interruption. A detailed explanation is given in the following.

[0054] Mode I (t<t0): SSCB is OFF, meaning both Sm and Sa are OFF and hold dc bus voltage Vdc individually (vSa=vSm=Vdc).

[0055] Voltage on passive components is zero, that is, vMOV1=vC1=vC2=0. Also, system and SSCB currents are zero, idc=iSm=iSa=iC2=iD2=0.

[0056] Mode II (t0≤t<t1): SSCB recloses the circuit by turning Sm ON. Load RL is energized. At the same time, C2 is charged through D2 and R2. Rebreaking is possible when C2 is charged.

[0057] So, the preparation time interval between a reclosing and the following rebreaking is determined by R2×C2 time constant.

[0058] Mode III (t1≤t<t2): C2 is fully charged, meaning vC2=Vdc. SSCB continues in normal operation mode. Sa remains OFF (vSa=Vdc and vC1=0). Current in Sa is zero (iSa=0), but the dc bus compensates C2 steady-state discharge, so vC2 remains at Vdc.

[0059] Mode IV (t2≤t<t3): Fault occurs at t=t2; dc current rises fast.

[0060] Mode V (t=t3): Fault current increases to If (iSm=idc=If). SSCB begins current interruption by turning Sa ON, which transfers the stored energy in C2 to C1 through Sm resulting in CC. The dynamic turn-OFF in Sm follows the same procedure elaborated in Section II-B.

[0061] Mode VI (t3<t<t5): Sm turns OFF; fault current commutates to Sa and charges C1; C2 discharges and its voltage decays to zero.

[0062] Mode VII (t5≤t<t6): MOV1 clamps the voltage across C1 and dissipates the remaining inductive energy. C2 is prevented to be reversely charged using an antiparalleled D1.

[0063] MOV1 absorbs the inductive energy of the line inductance, and the line current idc reduces to Vdc/R1 at t=t6. The voltage on MOV1 returns to the dc bus voltage, meaning that VMOV1=Vdc. As Sa is ON, there is a leakage current in the system as C1 discharges on R1, which is idc=iR1=iSa=Vdc/R1. As illustrated in Section III-B2, R1 is selected to satisfy (Vdc/R1)<IH, where IH is the holding current in Sa. As iSa<IH, Sa enters its turn-OFF mode.

[0064] Mode VIII (t6≤t≤t7): Sa turns OFF naturally at t=t6; C1 continues discharging on R1, and vSa increases simultaneously since vSa=vSm-vC1. At t=t7, vC1=0 and vSa=Vdc; interruption completes and the SSCB goes back to mode I. In this case, the breaker is ready for reclosing the circuit and energizing the load RL.

[0065] B. Design Procedure

[0066] With respect to FIGS. 3, 6, and 7, key parameters in Y-SSCB are capacitors C1 and C2, resistors R1 and R2, thyristors Sm and Sa, and diodes D1 and D2.

[0067] 1) C1 and C2 Selection: C1 and C2 are selected so that Sm undergoes its complete forward blocking. To achieve this, two conditions need to be satisfied: 1) ism reduces to zero, and 2) vSm must be negative for t tcc. The former is easily obtained through the Sm-C1-Sa-C2 path. In practice, to limit the generated pulse current at the instance of turning ON Sa, a small resistor RS can be connected in series with C2. Regarding a maximum fault current If, RS should be lower than Vdc/If. The latter (vSm<0 during tcc) is achieved when

vSm(t)=(vC1(t)+vSa+RS.Math.If−vC2(t))<0 for t≥tcc  (EQ. 2)

[0068] The easy way to find an approximation of C1 and C2 to satisfy (EQ. 2) is assuming dc current as a constant (idc=If) during current interruption. However, as the fault current is fed from the source during current interruption (refer to Mode VI in FIG. 6) and to satisfy tcc>tq in the main thyristor Sm, a redundancy factor 2<α<4 is included to ensure a safe commutation in Sm. Assuming C1=C2, we have

C1=C2=C>(2.Math.α.Math.If.Math.tq/Vdc)  (EQ. 3)

[0069] 2) R1 and R2 Selection: R1 is used to discharge C1 during mode VIII. A small value of R1 helps to accelerate the reclosing time interval treclosing, which is about 3×C1×R1. However, R1 needs to satisfy iSa<IH during mode VII. Equation (4) gathers these criteria as follows:

(Vdc/IH)<R1<(treclosing/(5.Math.C))  (EQ. 4)

[0070] R2 determines C2 charging interval in mode II, which is the SSCB's preparation time trebreaking (≈3×C2×R2) for the next interruption. Also, it helps to reduce the peak current imposed on dc source during mode V. To limit the source current flowing through R2 at the time of turning ON Sa, R2 needs to satisfy the following equation:

R2>Vdc/(ρ.Math.If))  (EQ. 5)

[0071] where ρ is particularly defined as 10% in this article. By combining Equations (3) and (5), R2 is defined as follows:

(2.Math.α.Math.tq/(ρ.Math.C))<R2<(trebreaking/(5.Math.C))  (EQ. 6)

[0072] 3) Semiconductors Sm, Sa,D1, and D2 Selection: Regarding the working principle in Section III-A, voltage and current stresses on the active and passive components are listed in FIG. 17, Table I. In this case, solid-state switches Sm and Sa and diodes D1 and D2 are selected by satisfying the following equation:

{VSm,break>VClmp & VSa,break>Vdc

{VD1,break>Vdc & VD2,break>Vdc  (EQ. 7)

[0073] where VSm,break, VSa,break, VD1,break, and VD2,break stand for the break-down voltage of Sm, Sa, D1, and D2, respectively; and VClmp is the maximum clamping voltage of MOV1.

[0074] As shown in FIG. 7, from t=t3 to t=t6, Sa handles the commutated fault current Time interval t6−t3 depends on the maximum fault current If, the dc bus voltage Vdc, the maximum clamping voltage of MOV1 labeled as VClmp, and the line inductor LLine. Sa needs to be selected in a way that it can safely conduct the fault current in this period. The same criteria are valid for D1 as it bypasses C2 when it completely discharges.

[0075] 4) Current Derivative in Sm and Sa: Regarding FIG. 6 and mode V, FIG. 8 shows the reverse recovery process in Sm, where Ls and Rs are the loop inductance and resistance in C2-Sm-C1-Sa-Ls-Rs path. With respect to Eq. (2), by including the loop inductance Ls, the following equation is derived:

vSm=vC1+vSa+(Ls.Math.(diSa/dt))+(Rs.Math.iSa)−vC2  (EQ. 8)

[0076] By assuming vSa≈0 during the reverse recovery process, one can conclude Equation (9) as follows:

vSm≈vC1+(Ls.Math.(diSa/dt))+(Rs.Math.iSa)−vC2  (EQ. 9)

[0077] which shows the impact of Ls and Rs on vSm. As vSm needs to be negative during tcc (referring to Section III-B1), higher values of Ls and Rs may lead to a failed forward blocking process in Sm. According to EQ. (9), Ls and Rs should be minimized.

[0078] On the other hand, a high current derivative in the commutation path (higher values of diSa/dt) results in a prompt temperature rise inside the device, creating internal hot spots, and finally permeant damage in the auxiliary thyristors. If the transient energy exceeds the devices' capability, an external inductance can be easily inserted into the commutation path.

[0079] In this case, EQ. (10) formulates the required Ls as follows:

Ls≥(vSm+vC2−Rs.Math.iSa)/(diSa/dt)max  (EQ. 10)

[0080] where (diSa/dt)max is the maximum allowable current derivative in Sa. Overdriving the gate (increasing the amplitude of the gate triggering pulse current with a fast-rising time, selecting thyristors with higher voltage/current ratings, and putting thyristors in parallel to handle higher pulse currents can significantly push up the current derivative limits in C2-Sm-C1-Sa-Ls-Rs commutation loop.

IV. Comparing the Proposed Y-SSCB to Shu's SSCB

[0081] To highlight the significance of the proposed Y-SSCB, it is compared with SSCB in Shu in terms of three practical factors.

[0082] A. Quantitative Comparison

[0083] Bidirectional topologies are shown in FIG. 9. In this case, FIG. 18, Table II presents a comparison with the breaker in Shu in terms of the number of active and passive components. Considering the unidirectional topologies, the proposed Y-SSCB needs one more capacitor, one more resistor, and two more diodes. Also, regarding the bidirectional topologies, the proposed Y-SSCB needs one more resistor, one more MOV, and five more diodes.

[0084] However, the number of thyristors is the same for both SSCBs, which dominates the cost. Also, the capacitor used in Shu needs to be bipolar since its polarity is reversed during the dc current interruption.

[0085] B. Reclosing and Rebreaking Process

[0086] The proposed Y-SSCB presents a reliable reclosing process. As elaborated in Section II-C, the preparation time interval between the reclosing and the subsequent rebreaking in the SSCB in Shu is unsatisfactorily elongated.

[0087] For the proposed Y-SSCB, the preparation time between a reclosing and the subsequent rebreaking is defined as follows:

trebreaking=6.Math.α.Math.tq/ρ for Y−SSCB  (EQ. 11)

[0088] where trebreaking ensures 95% charge in C2 after reclosing. Also, the preparation time interval for SSCB in Shu is given in EQ. (9)

trebreaking=3.Math.α.Math.tq If/IH for SSCB in Shu  (EQ. 12)

[0089] Regarding Equations (11) and (12), Equation (13) shows the preparation time ratio where thyristors turn-OFF time tq and redundancy factor α are the same for both breakers, and ρ=0.1

[00001]$\begin{array}{cc}k-\frac{\left(\mathrm{preparation}\mathrm{time}\mathrm{in}\mathrm{Shu}\right)}{\left(\mathrm{preparation}\mathrm{time}\mathrm{in}Y-\mathrm{SSCB}\right)}=\frac{\left(\mathrm{EQ}.12\right)}{\mathrm{EQ}.11}=\mathrm{If}/\left(20\times \mathrm{IH}\right)& \left(\mathrm{Eq}.13\right)\end{array}$

[0090] Regarding Equation (13), k increases when IH decreases or If rises. For example, given IH=200 mA and If=120 A, k is 30. That is, after reclosing, the proposed Y-SSCB is ready for rebreaking and isolating short-circuit faults 30 times faster than SSCB in Shu.

[0091] C. MOV Degradation Issue and Main Switch Voltage Utilizations Rate

[0092] The proposed Y-SSCB offers higher reliability and an enhanced voltage utilization rate in the main switch. With respect to FIG. 3, the SSCB in Shu imposes Vdc on the MOV when the breaker is OFF. This brings reliability issues due to the MOV degradation explained below.

[0093] As the number and duration of surge currents in MOVs rise, the MOVs fall into degradation. As MOVs degrade, the leakage current increases and the time to failure decreases. In addition, the MOVs leakage current value is directly proportional to the temperature, meaning that higher temperatures increase the leakage current in MOVs. A thermal runaway happens in an MOV when its temperature goes beyond its capability, resulting in a short-circuit failure.

[0094] To solve MOV degradation in SSCBs, a 20% margin in selecting the MOV dc rating VMOV,rating (the maximum allowable dc voltage on MOV in steady-state) has been suggested by Rodrigues et al., meaning Vdc≤0.8×VMOV, rating. However, it brings dimensioning issues and most importantly reduces the voltage utilization rate of the main thyristor. Regarding the research reported by others, the voltage utilization rate ηv in a solid-state switch is defined as follows:

ηv=(Vdc/main switch voltge rating)×100%.  (EQ. 14)

[0095] Considering Equation (14), to avoid MOV degradation, Vdc is limited to 0.8×VMOV,rating, which consequently reduces ηv. As ηv decreases, more solid-state switches need to be connected in series, leading to a more complicated and expensive design.

[0096] The proposed Y-SSCB solves the MOV degradation safety issue by disconnecting the MOV from the power line when SSCB is OFF. This fact is clear in FIG. 7, where vMOV1=vC1. The presented advantage extends the maximum allowable dc bus voltage on SSCB, which is highly attractive for industrial applications. Compared with the SSCB in Shu, the proposedY-SSCB presents at least 20% increase in ηv, which is significant.

[0097] It can be concluded that both Y-SSCB and the SSCB in Shu have almost similar design costs, but the proposed Y-SSCB presents better performance and higher practicality.

V. Experimental Validation

[0098] To verify the proposed Y-SSCB, experiments are conducted. FIG. 10 shows the implemented 400 V/120 A SSCB prototype and the dc test circuit diagram. The corresponding parameters are listed in FIG. 19, Table III. A 3 mF dc-link capacitor Cin is used to obtain a pulse current capability. Also, to limit the fault current's rising rate during experiments and obtain a fair comparison with the breakers in Shu and others, a 3.2 mH line inductor has been used in the dc test circuits. To emulate a short-circuit fault, a solid-state switch QSC is connected in series with a 1Ω fault resistor. At the load side, a 50Ω resistor is used to achieve 8 A steady-state load current, whereas the SSCB can conduct 12 A continuous load current under the current interruption capability of If=120 A.

[0099] For thyristors Sm and Sa, SK655KD is selected, which presents a holding current of IH=200 mA with the thyristor turn-OFF time of tq=20 μs. Takenα=3.75 and ρ=10%,C1 and C2 are chosen as 45 μF using EQ. (3). The redundancy factor of 3.75 obtains safety during tests and satisfies the criteria mentioned in Section III-B1. Besides, R1 is selected as 2.5 kΩ considering EQ. (4), and R2 is chosen as 50Ω using EQ. (6). For Rs, three 1Ω resistors are connected in parallel to achieve 0.33Ω. To highlight the effectiveness of the proposed Y-SSCB, experimental results of fault current interruption, operation of the main switch Sm, operation of the auxiliary switch Sa, and operation of Y-SSCB under reclosing and rebreaking are separately illustrated in the following sections.

[0100] A. Short-Circuit Fault Current Interruption

[0101] Short-circuit current interruption is shown in FIG. 11. The status of the solid-state switches Sm, Sa and the fault switch QSC is also represented in FIG. 11 to clarify the controlled time sequence used in conducting the experiments.

[0102] The SSCB conducts 8 A load current in a steady state. A short circuit is emulated in the system by turning QSC on at t=0.175 ms; then, the fault current begins to increase in the system. At t=1.57 ms, the fault current reaches 115.2 A, where the resistance of the line inductor also contributes to limiting the fault current. Then, SSCB starts breaking the dc current by turning ON Sa. After tcc=57.7 μs, the voltage across Sm returns to zero and begins blocking the forward voltage. The Sm turn-OFF process is elaborated in SectionV-B.At t=1.65 ms, vSm exceeds Vdc and forces the line current in the system to zero, where the line current peak reaches 120 A. Therefore, the reaction time interval is 80 μs (=1.65-1.57 ms). The line current reduces to zero at t=2.6 ms; current interruption process completes when Sa turns OFF naturally and holds vSa=vSm−VC1. As FIG. 11 indicates, Sm experiences the undershoot voltage of negative 330 V and peak voltage of 773 V.

[0103] B. Operation of Main Thyristor Sm

[0104] The operation of thyristor Sm during current interruption is explained in this section. FIG. 12 shows the voltage and current in Sm and FIG. 13 indicates voltage across Sm, C1, and C2.

[0105] As shown in FIG. 12, current commutation in Sm is achieved at t=1.57 ms, where its current reduces from 120 A to negative 239 A within 1 μs. The shape of the Sm current and voltage during the turn-OFF dynamic follows the analysis of Section II-B, where the thyristor reverse recovery interval trr is estimated as 2.7 μs. The conducted pulse current in Sm is totally safe as the selected thyristor SK655KD is able to handle 550 A for 20 ms. Besides, with respect to FIG. 13, the voltage across Sm is negative for tcc=57.7 is, which is sufficient for Sm to undergo its forward blocking process successfully.

[0106] Furthermore, FIG. 13 indicates the operation of C1 and C2 during current interruption, where the following points can be concluded.

[0107] 1) Voltage on C1 is zero before the short circuit occurs in the system. As MOV1 and R1 are connected in parallel to C1, the voltage on MOV1 and R1 is also zero. By turning Sa on at t=1.57 ms, the voltage on C1 begins to increase, and it is clamped to 740 V under the operation of MOV1.

[0108] 2) Voltage on C2 has been charged to 400 V during steadystate operation, which again confirms the analysis of Section III. As Sa turns ON, the voltage on C2 begins decaying by the fault current and it reaches zero at t=1.71 ms. Due to the operation of diode D1 in parallel to C2, the voltage on C2 remains zero, and it is not allowed to be charged reversely. This feature obtains the possibility to use unipolar capacitors in Y-SSCB.

[0109] 3) Regarding the Sm voltage in FIGS. 13 and (2), vSm≈vC1+(Rs×If)−vC2. In this case, when vSm=0, Rs×If=vC2−vC1. This voltage has been recorded as 44 V in FIG. 13, which results in Rs=0.36Ω for If=120 A.

[0110] The calculated Rs is close to the expected value of 0.33Ω according to Table III, where the drop voltage across Sa and the parasitic resistance in the loop of Sm-C1-Sa-Rs-C2 stand for the difference.

[0111] C. Operation of Auxiliary Thyristor Sa

[0112] The current and voltage waveforms of the auxiliary thyristor Sa are shown in FIGS. 14 and 15, respectively. During the steady-state and before the current interruption process, Sa is OFF, meaning vSa=400 V and iSa=iC1=0.

[0113] Sa turns ON at t=1.57 ms to achieve commutation in Sm. Voltage on Sa reduces to zero, and its current undergoes an overshoot as shown in FIG. 14. The peak of Sa current reaches 365 A within 1 μs, and it goes back to iSa=If=120 A within 3 μs. The current peak and its duration have safe margins with limitations of the selected thyristor SK655KD. The current peak in Sa during current commutation depends on the circuit (parasitic elements), electrical ratings of the dc system, and features of selected thyristors as described in (1). As the current in Sa reduces below its holding current at t=2.6 ms, Sa turns OFF naturally and holds vSa=vSm−vC1.

[0114] As shown in FIG. 15, vSa experiences a negative peak voltage of 298 V, and it begins to return back to Vdc=400 V as vC1 discharges on R1.

[0115] D. Operation of the Proposed Y-SSCB Under Reclosing and Rebreaking

[0116] Regarding the analysis presented in Section III, the proposed Y-SSCB can reclose the circuit and energize the load when C1 is almost discharged by paralleled resistor R1. With respect to FIG. 19, Table III, R1=2.5 kΩ and C1=45 μF. Regarding the reclosing time interval,C1 discharges by 95% in 337.5 ms(3×R1×C1) and by 98% in 450 ms (=4×R1×C1). The preparation time interval in the proposed Y-SSCB relies on resistor R2 and capacitor C2.

[0117] Given the value of R2=50Ω and C2=45 μF, after turning Sm ON, C2 charges to 0.95×Vdc in 6.75 ms (=3×R2×C2) and 0.98×Vdc in 9 ms (=4×R2×C2).

[0118] The lower limits of reclosing and the preparation time intervals are determined by parameters C1, C2, R1, and R2. The C1 and C2 selections depend on the maximum fault current. If aimed to be interrupted in the system, the dc bus voltage Vdc, and the thyristor specifications. The reclosing and the preparation time intervals are shorter for smaller If, faster thyristor (smaller tq), and larger IH. It is noted that, according to the maximum fault current If=120 A, the dc bus voltage Vdc=400 V, the thyristor turn-OFF time tq=20 μs, and IH=200 mA, parameters C1, C2, R1, and R2 have been selected to minimize the reclosing and preparation time intervals.

[0119] FIG. 16 indicates the experimental results under reclosing and rebreaking process, where the test has been repeated 10 times in the periods of 500 ms. As FIG. 16 shows, the proposed Y-SSCB is able to perform the operating duty of reclosing and rebreaking successfully and satisfies IEC-62271-100.

[0120] FIG. 20, Table IV presents a comparison between the proposed YSSCB and the active commutation-based breakers in the literature. To have a fair comparison, the maximum fault current is considered as 120 A, the dc bus voltage is Vdc=400 V, the thyristors' turn-OFF time and the holding current are assumed as tq=20 μs and IH=200 mA, respectively, and the redundancy factor is α=3.75. The proposed Y-SSCB has a longer reclosing time compared with the topologies listed in FIG. 20, Table IV. This issue elongates the re-energizing stage and puts limitations on the protective functions in dc systems. Solutions to this problem can be investigated in future research works. The proposed Y-SSCB presents a faster preparation time compared with the SSCBs Shu and others. S

[0121] E. Efficiency of the Proposed Y-SSCB

[0122] The short-circuit capability of an SSCB is given as 10 times the nominal load current. As the effectiveness of the proposed Y-SSCB under If=120 A has been verified, the proposed Y-SSCB is designed to conduct 12 A load current in steady-state. According to the manufacturer information for the main thyristor Sm, the conduction power loss of SK655KD is below 10 W under Idc=12 A. In this case, the proposedY-SSCB presents the efficiency in (15) during steady-state operation

ηY-SSCB≥(1−(PY-SSCB)/(Vdc×Idc))×100%=99.79%.  (EQ. 15)

[0123] It is noted that the line inductor is not included in calculating efficiency as it is a part of the dc system under operation.

VI. Comparative Study

[0124] Experimental results verify the analysis presented in Sections II-IV and prove the effectiveness of the proposed YSSCB. To highlight the significance of the presented Y-SSCB in practice, a comparative study with the reported topologies in literature has been conducted, and the results are summarized in FIG. 21, Table V. The presented comparison is based on the unidirectional topologies.

[0125] Compared with the CC-based breakers in Shu, the proposed Y-SSCB presents a safe reclosing. It also solves the MOV degradation reliability issue when SSCB is OFF. Also, the voltage utilization rate in the proposed Y-SSCB is higher, which reduces the cost when multiple solid-state switches need to be connected in series. However, that the source feeds the fault after turning OFF the main switch is one of the practical issues of CC-based SSCBs. This problem also exists in LCS-based structures and imposes a burden on the source during dc current interruption.

[0126] Future works can focus on solving this issue in CC-based and LCS-based SSCBs.

[0127] Compared with the AR-based SSCBs, the proposed Y-SSCB presents a relatively lower number of thyristors, faster current commutation, and higher short-circuit current interruption capability. As there is no inductor in the main conduction branch (in series with Sm), Y-SSCB presents a higher power density and an improved compactness.

[0128] LCS-based SSCBs have a lower number of thyristors and faster reclosing and rebreaking process compared with the proposed Y-SSCB. However, high current interruption capability is hard to achieve in these topologies due to the series connected IGBTs in the main branch. IGBTs also reduce the efficiency of the final design. MOV degradation reliability issue is another concern in LCS-based SSCBs.

[0129] Passive communication topologies may take the advantage of autonomous fault isolation, which is highly significant. On the other hand, the application of these SSCBs is limited as there is no manual tripping in the original structures. Also, they present relatively lower current interruption capability compared with the proposed Y-SSCB.

VII. Conclusion

[0130] A new Y-type thyristor-based dc SSCB has been described. The significances of the presented SSCB are summarized as follows.

[0131] 1) Obtained commutation path is capacitive, leading to a fast current commutation in the main thyristor.

[0132] 2) The proposed breaker protects the dc system during short circuit and overload scenarios, which enhances the practicality of newly introduced system-level protections.

[0133] 3) Benefiting from a high short-circuit capability of thyristor devices and full control switches in the main branch, high current interruption capability is obtained.

[0134] 4) MOVs are disconnected from the power line during SSCB OFF-state, which addresses the MOV degradation reliability issue. Also, it obtains the possibility to extend the maximum allowable dc bus voltage on the breaker by increasing the main switch voltage utilization rate.

[0135] 5) A complete design procedure was presented to optimize passive and active components.

[0136] 6) The proposed SSCB can perform the operating duty of reclosing and rebreaking process successfully. Experiments of 400 V/120 A in isolating short-circuit fault conditions validate the effectiveness of the proposed Y-SSCB in practice.

[0137] While the invention has been described with reference to the embodiments above, a person of ordinary skill in the art would understand that various changes or modifications may be made thereto without departing from the scope of the claims.