Electric circuit for the safe ramp-up and ramp-down of a consumer

Abstract

An electrical circuit for ensuring safe ramp-up and ramp-down of at least a regulated operating voltage, a reference voltage, and a reset signal for a consumer is described. The electrical circuit includes a voltage reference circuit and a voltage regulator. The voltage regulator is provided in order to furnish a regulated operating voltage, the voltage reference circuit is provided in order to be supplied with the regulated operating voltage furnished by the voltage regulator, and the voltage regulator is provided in order to obtain a reference voltage from the voltage reference circuit.

Claims

1. An electrical circuit comprising: a voltage reference circuit; and a voltage regulator that is configured to obtain a reference voltage from the voltage reference circuit and furnish a regulated operating voltage that is supplied to the voltage reference circuit; wherein the electrical circuit has at least one of the following four features (a)-(d): (a) the electrical circuit is configured to use control signals of the voltage reference circuit to prevent the voltage regulator from outputting the regulated operating voltage at a value that is determined to be too low for a voltage ramp-up; (b) the electrical circuit further comprises: a comparator configured to compare the regulated operating voltage and the reference voltage; and an AND gate that is configured to: evaluate an output signal of the comparator and a signal that is (i) output by the voltage reference circuit and (ii) indicates whether the value of the regulated operating voltage is high enough to make the reference voltage available; and output a reset signal based on the evaluation, the reset signal being generated in consideration of the regulated operating voltage and the reference voltage; (c) the voltage regulator includes: a first positive input by which the voltage regulator is configured to obtain the reference voltage from the voltage reference circuit; and a differential amplifier that has a second positive input and a third positive input by which two command variables, other than the reference voltage, is obtainable by the voltage regulator to set a lower limit for the regulated operating voltage of the voltage regulator; and (d) the electrical circuit is configured to prevent the voltage regulator from regulating the operating voltage to be lower than that which is required for ramp-up of the voltage reference circuit.

2. The electrical circuit as recited in claim 1, wherein the electrical circuit is configured to use the control signals of the voltage reference circuit to prevent the voltage regulator from outputting the regulated operating voltage at the value that is determined to be too low for the voltage ramp-up.

3. The electrical circuit as recited in claim 2, wherein the control signals are analog control signals and the voltage regulator is configured to evaluate the analog control signals of the voltage reference circuit.

4. The electrical circuit as recited in claim 1, wherein the electrical circuit comprises the comparator configured to compare the regulated operating voltage and the reference voltage.

5. The electrical circuit as recited in claim 4, wherein the electrical circuit comprises the AND gate.

6. The electrical circuit as recited in claim 5, further comprising: a timing element configured to delay a trailing edge of the signal (i) that is output by the voltage reference circuit and (ii) which the AND gate is configured to evaluate.

7. The electrical circuit as recited in claim 1, further comprising: a voltage divider configured to divide down the regulated operating voltage.

8. The electrical circuit as recited in claim 1, wherein the voltage reference circuit includes a current mirror configured to adjust a working point of transistors provided in the voltage reference circuit.

9. The electrical circuit as recited in claim 1, wherein the voltage regulator includes a current mirror which provides that an internal operating voltage tracks an external operating voltage during ramp-up.

10. The electrical circuit as recited in claim 1, wherein the voltage regulator includes the first positive input and the differential amplifier.

11. The electrical circuit as recited in claim 10, wherein the second positive input and the third positive input are configured to prevent the voltage regulator from regulating the regulated operating voltage to lower than that which is necessary in order to allow the voltage reference circuit to ramp up and to reach a target value of the voltage reference circuit.

12. The electrical circuit as recited in claim 10, wherein the second and third command variables are input voltages besides the reference voltage, and the electrical circuit is configured to prevent a gate of an output transistor from being pulled down during ramp-up of two of the input voltages of the differential amplifier, by limiting, using transistors, a voltage value to which an output stage can pull the gate of the output transistor.

13. The electrical circuit as recited in claim 1, wherein the voltage regulator includes at least two output transistors.

14. The electrical circuit as recited in claim 1, wherein the electrical circuit is configured to prevent the voltage regulator from regulating the operating voltage to be lower than required for the ramp-up of the voltage reference circuit.

15. The electrical circuit as recited in claim 1, wherein the reference voltage is furnished by the voltage reference circuit based on the supply of the regulated operating voltage to the voltage reference circuit, and the electrical circuit is configured to signal that a target for voltage ramp up or ramp down has been attained based on the reference voltage.

16. The electrical circuit as recited in claim 1, wherein the electrical circuit is configured to use the reference voltage to regulate the operating voltage during voltage ramp up to prevent an undervoltage.

17. The electrical circuit as recited in claim 1, wherein the electrical circuit is configured to use the reference voltage to regulate the operating voltage during voltage ramp down to prevent an overvoltage.

18. The electrical circuit as recited in claim 1, wherein the voltage regulator is configured to regulate the operating voltage in accordance with the reference voltage obtained from the voltage reference circuit conditional on the operating voltage supplied by the voltage regulator to the voltage reference circuit reaching a predefined target value.

19. The electrical circuit as recited in claim 1, wherein the electrical circuit is configured to signal that a target for voltage ramp up or ramp down has been attained conditional upon the operating voltage supplied by the voltage regulator to the voltage reference circuit reaching a predefined target value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplifying embodiments of the present invention are explained in further detail in the description below with reference to the figures.

(2) FIG. 1 shows a conventional circuit from the existing art, for furnishing a primary operating voltage, a reference voltage, and a reset signal.

(3) FIG. 2 shows an exemplifying embodiment of a circuit according to the present invention for furnishing a primary operating voltage, a reference voltage, and a reset signal.

(4) FIG. 3 shows an exemplifying embodiment of a voltage reference circuit usable according to the present invention, and of a voltage regulator usable according to the present invention.

(5) FIG. 4 shows an exemplifying embodiment of a symmetrical comparator, usable according to the present invention, for voltage monitoring.

(6) FIG. 5 shows an exemplifying embodiment of a basic cell according to the present invention for a primary voltage supply.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(7) Below, voltages (with reference to ground) at terminals and networks are labeled, for example, respectively as U.sub.VSUP for the V.sub.SUP terminal and U.sub.VBU for the network V.sub.BU, or alternatively labeled as U.sub.VSUP (t) and U.sub.VSU (t) if the time dependence is to be emphasized for better comprehension. Even without explicit emphasis, however, the time dependence always generally exists.

(8) FIG. 1 shows a conventional circuit from the existing art, for furnishing a primary operating voltage, a reference voltage, and a reset signal, in which a voltage reference circuit X.sub.1 and the comparators (only an undervoltage comparator X.sub.3 being illustrated in the interest of simplicity) are supplied with a first unregulated operating voltage U.sub.VBU, so that mutual dependence between reference voltage generation and operating voltage generation can be eliminated. It is thereby possible to prevent an excessively low reference voltage U.sub.VBG during ramp-up from causing the operating voltage to remain at too low a value, which in turn could cause the reference voltage U.sub.VBG to remain below a target value.

(9) As depicted in FIG. 1, the first unregulated operating voltage U.sub.VBU can be furnished by transistor M.sub.1 using a Zener diode D.sub.1 through which a current I.sub.Z flows. The current I.sub.Z is determined by resistor R.sub.1, supply voltage U.sub.VSUP, and the Zener voltage U.sub.Z of Zener diode D.sub.1. The voltage U.sub.VBU is approximately in the vicinity of the threshold voltage of transistor M.sub.1 below the Zener voltage U.sub.Z.

(10) In order to prevent comparator X.sub.3 from erroneously not indicating an undervoltage if an operating voltage U.sub.VBU is too low and a reference voltage U.sub.VBG is too low, it is necessary to ensure that the output signal of comparator X.sub.3 is not evaluated until the reference voltage U.sub.VBG has reached its target value. For that purpose, the signal of comparator X.sub.3 is not enabled by AND gate X.sub.4 until power-on reset circuit X.sub.5 has identified a voltage U.sub.VBU that is sufficiently high for the operation of voltage reference circuit X.sub.1 and of comparator X.sub.3.

(11) According to the existing art, power-on reset circuits exist which are based on the bandgap principle, and which signal more or less accurately when the ramping-up or ramping-down unregulated first internal operating voltage U.sub.VBU respectively exceeds or falls below a specific target value. This power-on reset threshold can allow a conclusion as to whether the available unregulated operating voltage is sufficient to operate voltage reference circuit X.sub.1 and comparator X.sub.3, which can then arrive at an exact conclusion as to whether the regulated internal operating voltage U.sub.VDDI is above the undervoltage reset threshold.

(12) The unregulated operating voltage U.sub.VBU is temperature-dependent; as a rule, the temperature response does not correlate with the temperature response of the bandgap, so that the temperature response of each individual component in the series would need to be trimmed or, alternatively, a certain greater inaccuracy in reference voltage U.sub.VBG would need to be considered. The unregulated voltage U.sub.VBU is furthermore dependent on the load current. Because the voltage reference circuit X.sub.1 has a finite power supply rejection ratio (PSRR), what results because of the unregulated operating voltage U.sub.VBU, in addition to the temperature response, is an additive inaccuracy in the reference voltage U.sub.VBG.

(13) Zener diode D.sub.1 must have a current I.sub.D flowing through it so that it can be operated in that part of its characteristic curve U.sub.Z (I.sub.D) in which the Zener voltage U.sub.Z changes only slightly upon a change in the current I.sub.D. That current is, as a rule, in the range of a few μA. In the context of an ASIC operating in standby mode, the additional power consumption for the Zener diode and the power-on reset circuit can have a disruptive effect.

(14) FIG. 2 shows an exemplifying embodiment of a circuit according to the present invention for furnishing a primary operating voltage U.sub.VDDI, a reference voltage U.sub.VBG, and an undervoltage reset signal NRST. Voltage regulator X.sub.2 is supplied with supply voltage U.sub.VSUP, and obtains its reference voltage U.sub.VBG from voltage reference circuit X.sub.1, which is turn is supplied with primary operating voltage U.sub.VDDI. Voltage reference circuit X.sub.1 indicates for that purpose, by way of its signal NRBG, whether the supply voltage U.sub.VDDI is high enough to make reference voltage U.sub.VBG available and to operate undervoltage comparator X.sub.3. Voltage regulator X.sub.2 is prevented from regulating to a lower voltage value U.sub.VDDI than the one needed in order to allow voltage reference circuit X.sub.1 to ramp up and to reach its target value. Analog control signals of voltage reference circuit X.sub.1 are evaluated for that purpose by voltage regulator X.sub.2, as indicated by the arrow proceeding from voltage reference circuit X.sub.1 to voltage regulator X.sub.2.

(15) FIG. 3 shows an exemplifying embodiment of a voltage reference circuit usable according to the present invention, and of a voltage regulator usable according to the present invention, in their circuit-engineering implementation. Voltage regulator X.sub.2 is embodied to generate an operating voltage U.sub.VDDI from an unregulated voltage U.sub.VSUP, and is further embodied, together with a voltage reference circuit X.sub.1, to generate a reference voltage U.sub.VBG that can ensure safe ramp-up and ramp-down of the primary voltage supplies and of the reference voltage of an ASIC. In addition, the reset signal NRBG indicates whether the supply voltage U.sub.VDDI is high enough to make the reference voltage U.sub.VBG available and to operate an undervoltage comparator X.sub.3 (not depicted). The left part of FIG. 3 depicts voltage reference circuit X.sub.1, made up of components C.sub.1, M.sub.1 to M.sub.15, Q.sub.1 to Q.sub.7, and R.sub.4 to R.sub.7. Voltage regulator X.sub.2, made up of components C.sub.2, C.sub.3, M.sub.16 to M.sub.32, Q.sub.8, Q.sub.9, and R.sub.8 to R.sub.10, is depicted on the right side of the image.

(16) Voltage reference circuit X.sub.1, depicted on the left in FIG. 3, operates according to the known bandgap principle. The two bipolar transistors Q.sub.3 and Q.sub.4 have different current/voltage characteristic curves I.sub.C3 (U.sub.B) and I.sub.C4 (U.sub.B) because of their different sizes (Q.sub.3 is larger than Q.sub.4 by a factor n) and because of the current feedback of Q.sub.3 produced by resistor R.sub.5. The current mirror made up of M.sub.6 and M.sub.7 adjusts, for the two bipolar transistors Q.sub.3 and Q.sub.4, the working point at which both their base voltage U.sub.B and their collector currents I.sub.C3 and I.sub.C4 are identical. The base voltage U.sub.B of Q.sub.3 and Q.sub.4 is regulated by M.sub.8 for that purpose. If the base voltage U.sub.B is too low, the collector current I.sub.C3 of Q.sub.3 is then higher than that of Q.sub.4 because of its area which is larger by the factor n, so that the gate of M.sub.8 is pulled upward by transistor M.sub.7 and the base voltage U.sub.B rises further. If the base voltage U.sub.B is too high, the collector current I.sub.C3 is lower than that of Q.sub.4 because of the current feedback of Q.sub.3 produced by resistor R.sub.5, so that the gate of M.sub.8 is pulled downward by bipolar transistor Q.sub.4 and the base voltage U.sub.B decreases further. The base-emitter voltage U.sub.BE3 of Q.sub.3 is lower, by ΔU.sub.BE=kT/q×ln(n), than the base-emitter voltage U.sub.BE4 of Q.sub.4, where k is the Boltzmann constant, T the absolute temperature, q the charge of an electron, and n the size ratio between Q.sub.3 and Q.sub.4. The voltage difference ΔU.sub.SE, together with the selection of resistor R.sub.5, defines the respective collector currents I.sub.C3 of Q.sub.3 and I.sub.C4 of Q.sub.4 and the respective drain-source currents I.sub.DS6 of M.sub.6 and I.sub.DS7 of M.sub.7, where I.sub.C3=I.sub.C4=I.sub.DS6=I.sub.DS7=I.sub.PTAT=1/R.sub.2×kT/q×ln(n). The current I.sub.PTAT is proportional to absolute temperature (PTAT), with a positive temperature coefficient. At the same time, however, the base-emitter voltage of bipolar transistors Q.sub.3 and Q.sub.4, and the base voltage U.sub.B, are also highly temperature-dependent. They have a negative temperature coefficient. The temperature profiles of both the base-emitter voltages and the collector currents are almost linear.

(17) M.sub.15 causes the current I.sub.PTAT also to flow through R.sub.4 and through Q.sub.7, where I.sub.R4=I.sub.C7=I.sub.PTAT (I.sub.B7 being ignored). Because Q.sub.4 and Q.sub.7 are identical in nature, then because I.sub.C4=I.sub.C7 (and ignoring I.sub.B7), they also have the same base-emitter voltage U.sub.BE4=U.sub.BE7=U.sub.8. A resistor R.sub.7 can be found for which the sum of the voltage drop U.sub.R7 across R.sub.7, caused by the collector current I.sub.C7=I.sub.PTAT flowing through it, and the base-emitter voltage U.sub.BE7, are independent of temperature to a first approximation. The total voltage U.sub.BE7+U.sub.R7 is also referred to as a “bandgap” voltage. It is equal to approximately 1.25 V regardless of the semiconductor technology that is used. This bandgap voltage reference circuit X.sub.1 requires a startup circuit, since the condition I.sub.C3=I.sub.C4 is also met for a current of 0.

(18) Voltage regulator X.sub.2 shown on the right in FIG. 3 is made up of a differential amplifier constituted by transistors M.sub.16 to M.sub.21 and an output stage in AB mode, constituted by way of transistors M.sub.25 to M.sub.28, for application of control to an output transistor M.sub.32. The differential amplifier obtains its cross current from transistor Q.sub.8, whose base is connected to that of Q.sub.2 and which thus functions as a current source. The current I.sub.PTAT of the voltage reference circuit therefore also flows through the difference pair made up of transistors M.sub.20 and M.sub.21. The gate of transistor M.sub.20 is connected to the reference voltage V.sub.BG. The gate of transistor M.sub.21 is connected to the internal operating voltage U.sub.VDDI divided down via the voltage divider made up of resistors R.sub.8 to R.sub.10, so that the output of the differential amplifier adjusts the gate of output transistor M.sub.32, by way of the output stage, in such a way that the target value of the internal operating voltage (for example, a target value of 2.5 to 5 volts) is produced, and the input difference voltage between the gates of transistors M.sub.20 and M.sub.21 becomes 0 V.

(19) Cascode transistors M.sub.18 and M.sub.19 can preferably be embodied as high-voltage transistors in order to enable higher input voltages, corresponding to the voltage class of those transistors, at the V.sub.SUP terminal. For the same reason, transistors M.sub.16 and M.sub.17 of the differential amplifier current mirror can preferably also be embodied as high-voltage transistors. The use of cascode transistors to increase the differential gain and the power supply rejection ratio would also be advantageous for this current mirror. In the interest of simplicity, however, cascode transistors are omitted at all points in FIG. 3 at which they are not necessary.

(20) The AB output stage made up of transistors M.sub.25 to M.sub.28 is connected to the gate of M.sub.27 at the differential amplifier output. It controls the gate of output transistor M.sub.32 of the voltage regulator. The transistors of the output stage, and the output transistor, can preferably be embodied as high-voltage transistors in order to enable higher input voltages at the V.sub.SUP terminal. Capacitor C.sub.2 can serve for frequency response compensation. Capacitor C.sub.3 can be used as a support capacitor or load capacitor for the voltage regulator.

(21) Startup of voltage reference circuit X.sub.1 and of voltage regulator X.sub.2 requires a startup circuit. As soon as the externally delivered unregulated operating voltage U.sub.VSUP(t) is high enough (in the present case, approximately 1 volt), the current I.sub.DS4(t) begins to flow through resistor R.sub.4 and transistors M.sub.2, M.sub.4, and Q.sub.1. Transistor M.sub.2 conducts because the voltage U.sub.VDDI(t) at its gate is initially 0 V. Assuming that M.sub.4 and M.sub.5 are identical in nature and that Q.sub.1 and Q.sub.2 are identical in nature, and ignoring the base currents of Q.sub.2 to Q.sub.5 and of Q.sub.8 and Q.sub.9, the same current also flows through transistors M.sub.5 and Q.sub.2, so that therefore I.sub.DS4(t)=I.sub.DS5(t). Because the base of Q.sub.9 is connected to the base of Q.sub.2, this current also flows via transistors Q.sub.9 and M.sub.24 into the current mirror constituted from M.sub.22 and M.sub.23, which raises the gate of M.sub.32 during ramp-up firstly to the value of the external operating voltage U.sub.VSUP(t), as long as the latter does not exceed the target value of the internal operating voltage by more than the threshold voltage of M.sub.32. Transistor M.sub.24 conducts because its gate is raised via resistor R.sub.4 to the sum of the base-emitter voltage U.sub.BE(t) of Q.sub.1 and the gate-source voltage U.sub.GS4(t) of M.sub.4. During ramp-up, the internal operating voltage U.sub.VDDI(t) (decreased by an amount equal to the threshold voltage of M.sub.32 and starting from 0 V) therefore initially tracks the external operating voltage U.sub.VSUP(t).

(22) Because the base of Q.sub.8 is also connected to the base of Q.sub.2, Q.sub.9 also begins to carry the same collector current as Q.sub.2 as soon as one of the transistors of the difference pair made up of M.sub.20 and M.sub.21 begins to conduct, and the internal operating voltage U.sub.VDDI(t) is already sufficiently high that the current mirror made up of M.sub.16 and M.sub.17 begins to function. The gates of transistors M.sub.20 and M.sub.21, constituting inputs of the difference pair, are connected on the one hand to the ramping-up reference voltage U.sub.VBG(t), and on the other hand to the ramping-up internal operating voltage U.sub.VDDI(t) that has been divided down via the voltage divider made up of resistors R.sub.5 to R.sub.7. The internal operating voltage is too low as ramp-up begins, however, so that the target value of the reference voltage V.sub.BG cannot at first occur, and the divided-down internal operating voltage also has not yet reached its target value. During ramp-up it is therefore not possible to predetermine which of these two voltages is higher as the ramp-up proceeds over time, or to predict the voltage profile over time that will occur at the output of the differential amplifier. Without further actions, the risk would exist that the voltage reference circuit might generate too low a reference voltage V.sub.BG and that the latter might remain at its excessively low value, since the ramping-up internal operating voltage might in fact not make possible a higher reference voltage. The result of this would be that the operating voltage would be unable to rise further and would never reach its target value, since from this perspective the differential amplifier would regulate to the excessively low value of the reference voltage.

(23) In the present case the reference voltage U.sub.VBG(t) is the sum of the base-emitter voltage U.sub.BE7(t) of transistor Q.sub.7 and the voltage drop U.sub.R7(t) across resistor R.sub.7. As long as the internal operating voltage is so low that the reference voltage has not yet reached its target value, U.sub.VDDI(t) must be higher, as the ramp-up proceeds over time, than the current value of the base-emitter voltage U.sub.BE7(t) of transistor Q.sub.7 plus the present value of the voltage drop U.sub.R7(t) across resistor R.sub.7 and the present value of the drain-source saturation voltage U.sub.DS15.sat(t) of transistor M.sub.15 functioning as a current source, yielding the following correlation:
U.sub.VDDI(t)>U.sub.BE7(t)+U.sub.R7(t)+U.sub.D15.sat(t)  (1)

(24) As long as the internal operating voltage is not sufficient to allow the reference voltage of the voltage reference circuit to reach the target value, the base voltage U.sub.B(t) is also too low, and the gate of transistor M.sub.8 is pulled upward because of the above-described regulating behavior of voltage reference circuit X.sub.1. In order for the reference voltage to be able to ramp up safely, in addition to the aforementioned condition (1) there must also be assurance that the internal operating voltage U.sub.VDDI(t) makes possible a further rise in the gate voltage of M.sub.8 during ramp-up. It follows from this that as the ramp-up proceeds over time, U.sub.VDDI(t) must be higher than the present value of the base voltage U.sub.B(t) plus the present value of the gate-source voltage U.sub.Gs8(t) of transistor Q.sub.8 and the present value of the drain-source saturation voltage U.sub.DS7.sat(t) of transistor M.sub.7 that functions as a current source, so that:
U.sub.VDDI(t)>U.sub.B(t)+U.sub.GS8(t)+U.sub.DS7.sat(t)  (2)

(25) In order to prevent the two ramping-up input voltages of the differential amplifier, namely the reference voltage U.sub.VBG(t) and the divided-down internal operating voltage U.sub.VDDI(t), from causing the differential amplifier to undesirably pull the gate of output transistor M.sub.32 downward during ramp-up, the voltage value to which the AB output stage can pull the gate of M.sub.32 is limited at the low end with the aid of transistors M.sub.29 to M.sub.31, so that the aforementioned inequalities (1) and (2) are always satisfied. The AB output stage can pull the gate of M.sub.32 downward only as long as transistors M.sub.28 to M.sub.31 are conducting. The source terminal of transistor M.sub.29 is thus always higher, by an amount equal to the respective threshold voltage U.sub.TH30 or U.sub.TH31 of transistors M.sub.30 or M.sub.31, than the higher of the two respective gate voltages U.sub.G30(t) or U.sub.G31(t) of M.sub.30 or M.sub.31. The gate of output transistor M.sub.32 can correspondingly be no lower than the sum of the threshold voltage U.sub.TH29 of M.sub.29, the respective threshold voltage U.sub.TH30 or U.sub.TH31 of M.sub.30 or M.sub.31, and the higher of the two respective gate voltages U.sub.G30(t) or U.sub.G31(t) of M.sub.30 or M.sub.31, so that U.sub.G32(t)≥U.sub.TH29+max(U.sub.G30(t)+U.sub.TH30; U.sub.G31(t)+U.sub.TH31). This yields a lower limit to which the voltage regulator can regulate the internal operating voltage. On the assumption that the threshold voltages of transistors M.sub.29 and M.sub.30 and those of transistors M.sub.30 and M.sub.31 are approximately the same, they are higher, by an amount approximately equal to the threshold voltage U.sub.THP of a PMOS transistor, than the higher of the two respective gate voltages U.sub.G30(t) or U.sub.G31(t) of M.sub.30 or M.sub.31, so that:
U.sub.VDDI(t)U.sub.G30(t)+U.sub.THP  (3)
and
U.sub.VDDI(t)>U.sub.G31(t)+U.sub.THP.  (4)

(26) The voltage U.sub.G31(t) is the sum of U.sub.BE7(t) and U.sub.R7(t). With suitable dimensioning, the threshold voltage U.sub.THP of M.sub.31 is higher than the drain-source saturation voltage U.sub.DS15.sat(t) of M.sub.15. Inequality (1) is thus always satisfied.

(27) The voltage U.sub.G30(t) is the sum of U.sub.BE6(t) and U.sub.GS10(t). Assuming that M.sub.8 and M.sub.10, and Q.sub.2 and Q.sub.6, are identical in nature, and ignoring the base currents of Q.sub.2 to Q.sub.5, Q.sub.8, and Q.sub.9 and the current I.sub.DS5, Q.sub.6 and M.sub.10 have the same current I.sub.PTAT flowing through them as M.sub.8 and Q.sub.2, so that U.sub.G30(t) corresponds to the sum of U.sub.GS8(t)+U.sub.B(t). With suitable dimensioning, it is permissible to ignore I.sub.DS5 if I.sub.DS5<<I.sub.PTAT over the entire temperature range. The base voltage U.sub.B(t) is equal to the base-emitter voltage U.sub.BE2(t) of Q.sub.2, whose collector receives the current from M.sub.8. With suitable dimensioning, the threshold voltage U.sub.THP of M.sub.30 is higher than the drain-source saturation voltage U.sub.DS7.sat(t) of M.sub.7. Inequality (2) is thus always satisfied. Satisfaction of inequalities (1) and (2) ensures that voltage reference circuit X.sub.1 can always ramp up.

(28) With suitable dimensioning of transistors M.sub.1 to M.sub.3 it is possible to ensure that the current that flows via resistor R.sub.4 out of the V.sub.SUP terminal is not completely dissipated to GND via transistors M.sub.2, M.sub.4, M.sub.5, Q.sub.1, and Q.sub.2, but instead partly feeds the internal operating voltage as soon as ramp-up has progressed sufficiently and the internal operating voltage U.sub.VDDI(t) has reached approximately the value U.sub.GS4(t)+U.sub.BE(t), since M.sub.3 then begins to conduct and M.sub.2 begins to block. The ratio of the currents through M.sub.2 and M.sub.3 can be adjusted with the aid of the coefficient α. This is beneficial especially in terms of a low standby current consumption.

(29) The internal operating voltage U.sub.VDDI can be monitored for under- and overvoltage. For that purpose, the operating voltage divided down with a voltage divider can be compared, with the aid of comparators, with the reference voltage in order to generate corresponding under- and overvoltage reset signals. To prevent the comparators from generating erroneous reset signals if the operating voltage U.sub.VDDI or reference voltage U.sub.VBG is too low, it is necessary to ensure that, during ramp-up and ramp-down and in normal operation, the output signals of the comparators are evaluated only if the internal operating voltage U.sub.VDDI is high enough to enable the functionality of the comparators and so that the reference voltage U.sub.VBG reaches its target value. The voltage reference circuit generates, for that purpose, a first reset signal NRBG that assumes a logical HIGH level if those two conditions are met and assumes a logical LOW level if one of the two conditions is not met.

(30) If the internal operating voltage U.sub.VDDI(t) during ramp-up or ramp-down is so low that the reference voltage U.sub.VBG(t) cannot reach its target value, at least one of transistors M.sub.7 or M.sub.15 acting respectively as a current source then respectively pulls the gate of M.sub.8 or the top terminal of resistor R.sub.7 very close to the operating voltage U.sub.VDDI(t), so that at least one of the two source-drain voltages U.sub.SD7(t) or U.sub.SD15(t) is almost 0 V. Which of the two source-drain voltages is lower depends, inter alia, on the threshold voltage of transistor M.sub.8.

(31) Only when the reference voltage U.sub.VBG(t) reaches its target value do the two transistor current sources M.sub.7 and M.sub.15 operate in saturation, so that there occurs in both of them a respective positive source-drain voltage U.sub.SD7(t) and U.sub.SD15(t) that is higher than the respective source-drain saturation voltages U.sub.SD7.sat(t) and U.sub.SD15.sat(t).

(32) Assuming that M.sub.8 and M.sub.10, and Q.sub.2 and Q.sub.6, are identical in nature, and ignoring the base currents of Q.sub.2 to Q.sub.5, Q.sub.8, and Q.sub.9 and the current I.sub.DS5, the same current I.sub.PTAT flows through Q.sub.6 and M.sub.10 as through M.sub.8 and Q.sub.2, so that the source-drain voltage U.sub.SD9(t) of M.sub.9 corresponds to the source-drain voltage U.sub.SD7(t) of M.sub.7.

(33) If the two source-drain voltages U.sub.SD9(t) and U.sub.SD15(t) of transistors M.sub.9 and M.sub.15 are higher than the threshold voltages U.sub.THP of the two transistors M.sub.12 and M.sub.13 (and, given suitable dimensioning, are therefore also higher than the respective source-drain saturation voltages U.sub.SD9.sat(t) and U.sub.SD15.sat(t)), they become conductive, and transistor M.sub.14, because its gate is connected to that of transistor M.sub.6, can provide, in its functionality as a current source, the current I.sub.PTAT that, with corresponding dimensioning of resistor R.sub.6, can cause the input of Schmitt trigger X.sub.6 to be pulled toward operating voltage U.sub.VDDI(t) so that there occurs at its output NRBG a HIGH level which indicates that the internal operating voltage U.sub.VDDI(t) is high enough for reference voltage U.sub.VBG(t) to reach its target value.

(34) The internal operating voltage U.sub.VDDI is then higher than the sum of the threshold voltage U.sub.TH12 of transistor M.sub.12, the gate-source voltage U.sub.GS10 of transistor M.sub.10, and the base-emitter voltage U.sub.BE6 of transistor Q.sub.6, i.e., in general higher than the sum of the threshold voltage U.sub.THP of a PMOS transistor, the threshold voltage U.sub.THN of an NMOS transistor, and the base-emitter voltage U.sub.BE of a bipolar transistor, yielding:
U.sub.VDDI>U.sub.THP+U.sub.THN+U.sub.BE,when NRBG=1  (5)

(35) In order to hold the input of Schmitt trigger X.sub.6, in the context of an abrupt rise in the internal operating voltage U.sub.VDDI, safely below its switching threshold for a signal change at the output from a LOW level to a HIGH level, capacitor C.sub.1 can pull the gate of M.sub.11 upward so that a dynamic source-drain current of transistor M.sub.14 can be dissipated via transistor M.sub.11 and, with suitable dimensioning, an undesired HIGH level at the output of Schmitt trigger X.sub.6 can be prevented.

(36) FIG. 4 shows an exemplifying embodiment of a symmetrical comparator X.sub.3, usable according to the present invention, for voltage monitoring, which is connected to a Schmitt trigger X.sub.6 that is connected in turn upstream from an AND gate X.sub.4. In order for such a comparator to be able to function, the internal operating value U.sub.VDDI must be at least equal to the sum of the threshold voltage U.sub.TH34 of transistor M.sub.34, the drain-source saturation voltage U.sub.DS37.sat of transistor M.sub.37, and the saturation voltage U.sub.CE10.sat of bipolar transistor Q.sub.10, i.e., in general greater than the sum of a threshold voltage U.sub.THP of a PMOS transistor, the drain-source saturation voltage U.sub.DSN.sat of an NMOS transistor, and the saturation voltage U.sub.CE.sat of a bipolar transistor, yielding the following correlation:
U.sub.VDDI>U.sub.THP+U.sub.DSN.sat+U.sub.CE.sat  (6)

(37) On the assumption that the drain-source saturation voltage U.sub.DS.sat of a MOS transistor is generally lower than its threshold voltage U.sub.TH, i.e., U.sub.DSN.sat<U.sub.THN; and that the saturation voltage U.sub.CE.sat of a bipolar transistor is lower than its base-emitter voltage U.sub.BE, i.e., U.sub.CE.sat<U.sub.BE, inequality (6) above is always satisfied for NRBG=1, and the functionality of the symmetrical comparator in FIG. 4 is thereby ensured.

(38) It should be noted that this consideration is valid only if the components M.sub.34, M.sub.35, M.sub.37, M.sub.38, and Q.sub.10 of the symmetrical comparator in FIG. 4 have, flowing through them, a current that is lower than or equal to the current that flows through the components M.sub.12, M.sub.10, and Q.sub.6 of voltage reference circuit X.sub.1 in FIG. 3. This is the case for symmetrical comparator X.sub.3 of FIG. 4, since transistor Q.sub.10 of that comparator has flowing through it the same current I.sub.PTAT as transistor Q.sub.6 of voltage reference circuit X.sub.1.

(39) Comparator X.sub.3 can supply a valid output signal as long as at least one of its input voltages respectively at terminals V.sub.BG or V.sub.MON is higher than the sum of the threshold voltage U.sub.TH37 or U.sub.TH38 of transistor M.sub.37 or M.sub.38, and the saturation voltage U.sub.CE10.sat of bipolar transistor Q.sub.10, i.e., in general higher than the sum of a threshold voltage U.sub.THN of an NMOS transistor and the saturation voltage U.sub.CE.sat of a bipolar transistor, yielding:
min(U.sub.VBG;U.sub.VMON)>U.sub.THN+U.sub.CE.sat  (7)

(40) Inequality (7) can easily be satisfied by suitable selection of NMOS transistors M.sub.37 and M.sub.38, and of a reference voltage U.sub.VBG=1.25 V.

(41) The result of AND gate X.sub.4 downstream from comparator X.sub.3 in FIG. 4 is that the output signal of Schmitt trigger X.sub.6 is not evaluated until the internal operating voltage U.sub.VDDI is sufficiently high that the comparator can function and the reference voltage U.sub.VBG has reached its target value, i.e., when inequalities (6) and (7) are both satisfied.

(42) FIG. 5 shows an exemplifying embodiment of a basic cell according to the present invention for a primary voltage supply with which a primary operating voltage is made available at terminal V.sub.DDI, a primary reference voltage at terminal V.sub.REF, a primary reference current at terminal I.sub.REF, and a primary reset signal, for indicating under- or overvoltage, at terminal NRST. The basic cell can be powered from an unregulated voltage source via terminal V.sub.SUP. Provision is advantageously made to make the available operating voltage V.sub.DDI and reference voltage V.sub.REF configurable with the aid of the respective control signals SET_VDDI[1:0] and SET_VREF[1:0], for example where U.sub.VDDI=5.0 V/4.5 V/3.3 V/2.5 V and where U.sub.VREF=1.25 V/1.2 V/1.0 V/0.8 V. A trimming functionality is furthermore provided via terminals TRIM_TK[5:0], TRIM_VREF[5:0], and TRIM_IREF[5:0] provided on the basic cell.

(43) A different topology can also be selected for voltage reference circuit X.sub.1 and voltage regulator X.sub.2, as long as the principle of the present invention, according to which voltage regulator X.sub.2 is prevented from regulating to a voltage lower than the one required in order to enable voltage reference circuit X.sub.1 to ramp up, is adhered to.

(44) Because such an intervention need not necessarily be made in the output stage of voltage regulator X.sub.2, it would also be possible to expand the differential amplifier of voltage regulator X.sub.2 to include a second and a third positive input in order to deliver to it, in addition to the reference voltage V.sub.BG, a second and a third command variable that then set a lower limit for the operating voltage. For that purpose, for example, the voltage values on the right side of the inequalities recited above could be divided down by circuit engineering at the same ratio as the operating voltage that is divided down with the aid of resistors R.sub.8 to R.sub.10, in order then to deliver them to those additional inputs. If the intervention is made in the differential amplifier of voltage regulator X.sub.2, then a PMOS output transistor can also be used instead of NMOS output transistor M.sub.32. The internal operating voltage U.sub.VDDI could then come very close to the external supply voltage U.sub.VSUP.

(45) Instead of intervening in the differential amplifier or the output stage, it is also possible to use, in voltage regulator X.sub.2, a second output transistor whose gate is not influenced at all by the differential amplifier but instead is raised respectively to the higher of the two voltages U.sub.G30 or U.sub.G31 plus a threshold voltage U.sub.THP of a PMOS transistor and a threshold voltage U.sub.THN of an NMOS transistor. The two aforementioned inequalities (3) and (4) can be satisfied in this case as well.

(46) An output stage, in particular an AB output stage, is also not obligatory for voltage regulator X.sub.2. If transistors M.sub.30 and M.sub.31 were inserted between the source terminal of transistor M.sub.19 and the drain terminal of transistor M.sub.21 in FIG. 3, the lower voltage value at the output of the differential amplifier would be limited in accordance with inequalities (3) and (4). In this case, output transistor M.sub.32 would be connected at its gate terminal directly to the output of the differential amplifier, and likewise cascode transistors M.sub.18 and M.sub.19 at their gate terminals.

(47) Generally, any desired topology can be selected for voltage reference circuit X.sub.1. In accordance with inequalities (1) and (2), it is necessary to ascertain the conditions that must be satisfied in order to enable that circuit to ramp up.

(48) Cascode transistors can be used both for M.sub.6, M.sub.7, M.sub.9 and M.sub.14 to M.sub.17, and for Q.sub.3 and Q.sub.4, in order to increase the power supply rejection ratio, although this is not depicted in FIG. 3.

(49) Because the power consumption of voltage reference circuit X.sub.1 can be in the single-digit μA range, provision can be made to use an RC filter, having a series resistor in the range of a few 10 s to 100 kilohm, as an input filter for the operating voltage of the voltage reference circuit.

(50) A timing element can delay the trailing edge of the NRBG signal in order to implement a defined power-on reset phase even in a context of smaller, shorter interruptions in the operating voltage.