Power converter with zero-voltage switching

Abstract

A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node between the switch and the primary winding having a switching voltage. The circuit also includes a switching controller configured to generate the PWM signal in response to a ramp signal. The ramp signal can have an amplitude of a slope that is proportional to a decay rate of a magnetizing current of the transformer and generated in response to feedback from the power stage. The switch can be activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal.

Claims

1. A power converter circuit comprising: a power stage comprising a transformer and a switch, the switch being controlled in response to a pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, the power stage comprising a switching node between the switch and the primary winding having a switching voltage; and a switching controller configured to generate the PWM signal in response to a ramp signal, the ramp signal having a slope that is proportional to a decay rate of a magnetizing current associated with the transformer and generated in response to at least one feedback voltage from the power stage, the switch being activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal.

2. The circuit of claim 1, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage, the ramp signal being generated based on the sampled auxiliary voltage.

3. The circuit of claim 2, wherein the switching controller comprises a ramp generator configured to generate the ramp signal, the ramp generator comprising a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp signal based on the sampled auxiliary voltage.

4. The circuit of claim 2, wherein the switching controller comprises a zero-voltage switching (ZVS) optimizer circuit configured to set a ramp threshold having an amplitude that is associated with the amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to set the switching voltage to approximately zero volts, such that the switching controller is configured to control the PWM signal to thereby activate the switch in response to the ramp signal increasing to approximately the amplitude of the ramp threshold.

5. The circuit of claim 1, wherein the PWM signal is a first PWM signal, and wherein the switch is a first switch, wherein the power stage further comprises an LC resonator formed by the primary winding and a capacitor and a second switch that is alternately activated via a second PWM signal to circulate the magnetizing current via the LC resonator, wherein the switching controller comprises a zero-voltage switching (ZVS) optimizer circuit configured to set a ramp threshold having an amplitude that is associated with an amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at the switching node, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximate the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to the switching voltage decreasing to less than an activation threshold voltage to activate the first switch in response to the switching voltage having an amplitude of approximately zero volts.

6. The circuit of claim 5, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined power stage parameter corresponding to a ratio of switching node capacitance and magnetizing inductance.

7. The circuit of claim 6, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage based on the second PWM signal to generate the ramp signal, and to sample the auxiliary voltage based on the first PWM signal to generate the ramp threshold.

8. The circuit of claim 5, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the ramp threshold in response to the timer counting to a predetermined time duration.

9. The circuit of claim 8, wherein the ZVS discriminator circuit comprises a high-voltage blocking circuit configured to block an amplitude of the switching voltage that is greater than a predetermined threshold, wherein the high-voltage blocking circuit comprises one of a JFET, an LDMOS device, and a diode interconnecting the switching voltage and an input of a comparator that is configured to compare the switching voltage with the activation threshold voltage.

10. An integrated circuit (IC) chip comprising at least a portion of the power converter circuit of claim 1.

11. A power converter circuit comprising: a power stage comprising a transformer, a first switch, and a second switch, the first switch being controlled via a first pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, and the second switch being controlled via a second PWM signal to re-circulate a magnetizing current associated with the transformer via an LC resonator formed by the primary winding and a capacitor; and a switching controller configured to generate the first PWM signal and the second PWM signal and to generate a ramp signal in response to feedback from the power stage such that a slope of the ramp signal is proportional to a decay rate of the magnetizing current to provide zero-volt switching (ZVS) activation of the first switch via the first PWM signal.

12. The circuit of claim 11, wherein the switching controller comprises a ZVS optimizer circuit configured to set a ramp threshold that has an amplitude that is associated with an amplitude of the ramp signal, which corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at a switching node associated with the first switch, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximately equal to the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to the switching voltage decreasing to less than an activation threshold voltage to provide the ZVS activation of the first switch.

13. The circuit of claim 12, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined output voltage threshold.

14. The circuit of claim 13, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the difference voltage in response to the timer counting to a predetermined time duration.

15. The circuit of claim 12, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage via the second PWM signal to generate the ramp signal and to sample the auxiliary voltage via the first PWM signal to generate the ramp threshold.

16. An integrated circuit (IC) chip comprising a power converter circuit, the power converter circuit comprising: a gate driver stage configured to generate a first switching signal in response to a first pulse-width modulation (PWM) signal and a second switching signal in response to a second PWM signal; a power stage comprising a transformer, a first switch, and a second switch, the first switch being controlled via the first switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage and induce an auxiliary voltage in an auxiliary winding of the transformer, and the second switch being controlled via the second switching signal to re-circulate a magnetizing current associated with the transformer via an LC resonator formed by the primary winding and a capacitor; and a switching controller configured to generate the first and second PWM signals and to generate a ramp signal based on the auxiliary voltage, the ramp signal having a slope that is proportional to a decay rate of the magnetizing current to provide zero-volt switching (ZVS) activation of the first switch via the first PWM signal.

17. The circuit of claim 16, wherein the switching controller comprises a ZVS optimizer circuit configured to set a ramp threshold that has an amplitude that is approximately associated with an amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at a switching node associated with the first switch, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximately equal to the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to a switching voltage at the switching node decreasing to less than an activation threshold voltage to activate the first switch in response to the switching voltage having an amplitude of approximately zero volts.

18. The circuit of claim 17, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined output voltage threshold.

19. The circuit of claim 18, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the difference voltage in response to the timer counting to a predetermined time duration.

20. The circuit of claim 17, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage from the auxiliary winding in response to the second PWM signal to generate the ramp signal and to sample the auxiliary voltage via the first PWM signal to generate the ramp threshold.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates an example of a power converter system.

(2) FIG. 2 illustrates an example of a power converter circuit.

(3) FIG. 3 illustrates an example of a timing diagram.

(4) FIG. 4 illustrates an example of a switching controller.

(5) FIG. 5 illustrates another example of a switching controller.

(6) FIG. 6 illustrates an example of a zero-voltage switching (ZVS) discriminator.

(7) FIG. 7 illustrates examples of high-voltage blocking circuits.

DETAILED DESCRIPTION

(8) This disclosure relates generally to electronic systems, and more specifically to a power converter with zero-voltage switching. The power converter can be implemented to generate an output voltage in response to an input voltage. As an example, the power converter can be configured as a flyback power converter. The power converter includes a gate driver stage that is configured to generate one or more switching signals in response to a respective at least one pulse-width modulation (PWM) signal. As an example, the gate driver can generate a first switching signal in response to a first PWM signal and a second switching signal in response to a second PWM signal. The power converter can also include a power stage. The power stage includes a transformer and at least one switch (e.g., transistor device) controlled by the switching signal(s) (e.g., a first switch and a second switch). As an example, the first switch can be activated via the first switching signal to provide a primary current through a primary winding of the transformer, from an input voltage to a low voltage rail (e.g., ground). The primary current can induce a secondary current in a secondary winding in an output stage to generate an output voltage (e.g., via a rectifier). The second switch can be activated via the second switching signal to circulate a magnetizing current associated with the transformer in a circuit path that includes an LC resonator.

(9) In addition, the power converter includes a switching controller that is configured to generate the PWM signal(s) based on feedback from the power stage. As an example, the switching controller includes a magnetizing ramp generator that is configured to generate a ramp signal that has a positive slope that is proportional to a decay rate of the magnetizing current during a deactivated state of the switch (e.g., during activation of the second switch). The ramp signal can be compared with a ramp threshold, such as generated by a zero-volt switching (ZVS) optimizer, that corresponds with a negative peak amplitude of the magnetizing current that is sufficient to dissipate a capacitive charge in a switching node associated with the switch (e.g., the first switch). As a result, in response to the ramp signal having an amplitude that is approximately equal to the ramp threshold, the switching controller can deactivate the second switch and activate the first switch to effect an approximate zero-volt switching of the first switch. As a result, the power converter can substantially eliminate switching losses, and can provide for an efficient switching operation in generating the output voltage.

(10) FIG. 1 illustrates an example of a power converter system 10. The power converter system 10 is configured to convert an input voltage V.sub.IN (e.g., a DC input voltage) to a DC output voltage V.sub.OUT. As an example, the power converter system 10 can be configured as a flyback power converter, as described in greater detail herein. The power converter system 10 can be implemented in any of a variety of electronic applications, such as in a portable electronic device, to provide efficient power conversion in generating the output voltage V.sub.OUT.

(11) The power converter system 10 includes a gate driver 12 that is configured to generate at least one switching signal SW based on a respective at least one pulse-width modulation (PWM) signal PWM (hereinafter “signal PWM”). The switching signal(s) SW are provided to a power stage 14. In the example of FIG. 1, the power stage 14 includes a transformer 16 and at least one switch 18 that is controlled by the switching signal(s) SW. As an example, one of the switch(es) 18 can be activated via a respective switching signal SW to provide a primary current through a primary winding of the transformer 16. The primary current can induce a secondary current in a secondary winding of the transformer 16 to generate the output voltage V.sub.OUT (e.g., via a rectifier). As an example, the switch(es) 18 can include a second switch that can be activated via a respective second switching signal SW to circulate a magnetizing current associated with the transformer 16, such as via an LC resonator.

(12) The power converter system 10 further includes a switching controller 20 that is configured to generate the signal(s) PWM that are provided to the gate driver 12. The switching controller 20 includes a magnetizing ramp generator (hereinafter “ramp generator”) 22 that is configured to generate a ramp signal that is implemented for the control of the signal(s) PWM, and therefore the control of the switch(es) 18 via the switching signal(s) SW. In the example of FIG. 1, the switching controller 20 is configured to generate the signal(s) PWM based on at least one feedback voltage V.sub.FB. As an example, the feedback voltage(s) V.sub.FB can be associated with one or more voltages that characterize the performance of the power stage 14, such as including characterizing magnetizing current in the transformer. As described herein, the ramp signal can be generated as having a positive slope that is proportional to a decay rate of a magnetizing current associated with the transformer 16 to implement zero-volt switching (ZVS) of one of the switch(es) 18 to substantially mitigate switching losses associated with the power converter system 10. As a result, the power converter system 10 can operate in a significantly efficient manner.

(13) FIG. 2 illustrates an example of a power converter circuit 50. The power converter circuit 50 is configured to convert a DC input voltage V.sub.IN to a DC output voltage V.sub.OUT. The power converter circuit 50 can be implemented in any of a variety of electronic applications, such as in a portable electronic device, to provide efficient power conversion in generating the output voltage V.sub.OUT.

(14) The power converter circuit 50 includes a gate driver 52 that is configured to generate a first switching signal SW.sub.1 and a second switching signal SW.sub.2 based on respective signals PWM.sub.1 and PWM.sub.2. The power converter circuit 50 also includes a power stage 54. The power stage 54 includes a transformer 56 having a primary winding N.sub.P, a secondary winding N.sub.S, and an auxiliary winding N.sub.A, as well as a magnetizing inductor L.sub.M that corresponds to the magnetic energy associated with the transformer 56. The power stage 54 also includes an input inductor L.sub.K corresponding to a leakage inductance of the transformer 56, a resonant capacitor C.sub.1, and a pair of switches demonstrated in the example of FIG. 2 as a first N-channel field effect transistor device (“N-FET”) Q.sub.1 and a second N-FET Q.sub.2. The N-FET Q.sub.1 is controlled via the switching signal SW.sub.1 and the N-FET Q.sub.2 is controlled via the switching signal SW.sub.2. The N-FETs Q.sub.1 and Q.sub.2 are coupled via a switching node 58.

(15) During a first switching phase, the N-FET Q.sub.1 is activated (e.g., with a gate-source voltage sufficient for saturation mode) via the first switching signal SW.sub.1 to conduct a primary current I.sub.P from the input voltage V.sub.IN through the input inductor L.sub.K, through the primary winding N.sub.P, and through the N-FET Q.sub.1 to a low-voltage rail (e.g., ground). In response, the primary current I.sub.P in the primary winding N.sub.P induces a secondary current I.sub.S in the secondary winding N.sub.S through an output diode D.sub.OUT to generate the output voltage V.sub.OUT across a load, demonstrated by a resistor R.sub.OUT, and an output filter formed by a capacitor C.sub.F and a corresponding internal resistance R.sub.F. Upon deactivation of the N-FET Q.sub.1 via the first switching signal SW.sub.1, during a second switching phase, the N-FET Q.sub.2 is activated via the second switching signal SW.sub.2 (e.g., after expiration of a predetermined dead-time) to decay a magnetizing current I.sub.M in a reverse direction by the voltage of the resonant capacitor C.sub.1, such that the negative magnetizing current (I.sub.M−) discharges the junction capacitance of the N-FET Q.sub.1 and charges the junction capacitance of the N-FET Q.sub.2. As the charge of the N-FET Q.sub.1 is removed, the drain-to-source voltage of the N-FET Q.sub.1 reduces to zero volts before activating the N-FET SW.sub.1. As a result, the power converter circuit 50 can operate to efficiently reduce switching losses. During the activation time of the N-FET Q.sub.2, the leakage inductance L.sub.K and the capacitor C.sub.1 forms a resonant tank to circulate the leakage inductance L.sub.K energy to the output, such that clamping losses can also be efficiently reduced.

(16) The power converter circuit 50 further includes a switching controller 60 that is configured to generate the first signal PWM.sub.1 and the second signal PWM.sub.2 that are provided to the gate driver 52. In the example of FIG. 2, the switching controller 60 includes a magnetizing ramp generator (hereinafter “ramp generator”) 62 that is configured to generate a ramp signal that is implemented for the control of the signals PWM.sub.1 and PWM.sub.2, and therefore the control of the N-FETs Q.sub.1 and Q.sub.2 via the switching signals SW.sub.1 and SW.sub.2, respectively. The switching controller 60 is demonstrated as receiving a voltage V.sub.S, a voltage V.sub.T1, a voltage V.sub.SW, and a voltage V.sub.RS that can collectively correspond to the feedback voltage(s) V.sub.FB in the example of FIG. 1. The switching controller 60 is thus configured to generate the signals PWM.sub.1 and PWM.sub.2 in response to the voltages V.sub.S, V.sub.T1, V.sub.SW, and V.sub.RS.

(17) The voltage V.sub.T1 is generated by a constant current/constant voltage compensation system (“CC/CV COMP”) 64 that is configured to provide the voltage V.sub.T1 as a threshold voltage to limit the magnitude of a positive peak magnetizing current (I.sub.M+), so a substantially constant output current I.sub.OUT or output voltage V.sub.OUT can be regulated. The voltage V.sub.S can correspond to a voltage-divided auxiliary current V.sub.AUX associated with the auxiliary winding N.sub.A, based on the voltage-divider formed by resistors R.sub.1 and R.sub.2 in series with the auxiliary winding N.sub.A. The voltage V.sub.RS corresponds to a measure of amplitude of the peak magnetizing current I.sub.M+ across a sense resistor R.sub.S. The switching voltage V.sub.SW corresponds to a switching node voltage associated with the N-FET Q.sub.1.

(18) As described herein, the power converter circuit 50 is configured to implement zero-volt switching of the N-FET Q.sub.1, and thus to activate the N-FET Q.sub.1 at approximately zero volts amplitude of the switching voltage V.sub.SW at the switching node 58. As an example, to implement zero-volt switching, the power converter circuit 50 can implement the following criterion:
½*L.sub.M*I.sub.M(−).sup.2≥½*C.sub.SW*V.sub.SW.sup.2  Equation 1

(19) Where: I.sub.M(−) corresponds to the negative peak amplitude of the magnetizing current I.sub.M;

(20) C.sub.SW corresponds to the capacitance of the switching node 58.

(21) $\begin{array}{cc}{I}_M(-)=\left(K_O*\sqrt{\frac{C_{\mathrm{SW}}}{L_M}}\right)*\left(V_{\mathrm{IN}}+\left(N_P/N_S\right)*V_{\mathrm{OUT}}\right)& \mathrm{Equation}2\end{array}$
Where: L.sub.M corresponds to the magnetizing inductance (of the magnetizing inductor L.sub.M);

(22) N.sub.P/N.sub.S is a turns ratio between the secondary winding N.sub.S and the primary winding

(23) N.sub.P;

(24) K.sub.O corresponds to a gain constant greater than or equal to one.

(25) For example, as described in greater detail herein, the switching controller 60 can generate the ramp signal as having a positive slope that is proportional to a decay rate of a magnetizing current I.sub.M to implement zero-volt switching (ZVS) of the N-FET Q.sub.1 to substantially mitigate switching losses associated with the power converter system 50. As a result, the power converter system 50 can operate in a significantly efficient manner based on having significantly mitigated switching losses and clamping losses.

(26) FIG. 3 illustrates an example of a timing diagram 100. The timing diagram 100 demonstrates signals demonstrated in the example of FIG. 2 plotted as a function of time. Thus, reference is to be made to the example of FIG. 2 in the following description of the example of FIG. 3.

(27) The timing diagram 100 demonstrates the first signal PWM.sub.1, the second signal PWM.sub.2, the magnetizing current I.sub.M, the voltage V.sub.RS, a voltage V.sub.R corresponding to the ramp signal generated by the magnetizing ramp generator 62, the switching voltage V.sub.SW, and the voltage V.sub.S plotted over time. At approximately a time T.sub.0, the signal PWM.sub.1 is asserted from a logic-low to a logic-high state. As described herein, the signal PWM.sub.1 can be asserted in response to the switching voltage decreasing less than a threshold voltage V.sub.TH. Thus, in response to the switching voltage V.sub.SW decreasing less than the threshold voltage V.sub.TH at approximately the time T.sub.0, the signal PWM.sub.1 can be asserted. Accordingly, the switching signal SW.sub.1 can likewise be asserted via the gate driver 52 in response to the signal PWM.sub.1 to activate the N-FET Q.sub.1 at approximately the time T.sub.0.

(28) Prior to the time T.sub.0, the magnetizing current I.sub.M can be negative (e.g., with respect to the direction of the current flow of the magnetizing current I.sub.M in the example of FIG. 2). In response to activation of the N-FET Q.sub.1, a current path is formed for the primary current I.sub.P between the input voltage V.sub.IN and the low-voltage rail (e.g., ground) via the leakage inductance L.sub.K, the primary winding N.sub.P, the activated N-FET Q.sub.1, and the sense resistor R.sub.S. In response, the primary current Ip initially has a negative amplitude (e.g., with respect to the direction of the current flow of the primary current I.sub.P in the example of FIG. 2), but begins to reverse direction (e.g., becomes less negative) to eventually become positive to flow from the input voltage V.sub.IN to the low-voltage rail. In the example of FIG. 3, the primary current I.sub.P is represented by the voltage V.sub.RS as having an amplitude that is equal to the primary current I.sub.P multiplied by the sense resistance R.sub.S. Thus, subsequent to the time T.sub.0, the voltage V.sub.RS is demonstrated as increasing linearly. Similarly, the magnetizing current I.sub.M can likewise increase linearly. Additionally, during activation of the N-FET Q.sub.1, the switching voltage V.sub.SW can have an amplitude of approximately zero volts, and the voltage V.sub.S can have a negative amplitude (e.g., approximately proportional to a negative turns ratio between the primary winding N.sub.P and the auxiliary winding N.sub.A times the input voltage V.sub.IN).

(29) As described in greater detail herein, the switching controller 60 can be configured to compare the voltage V.sub.RS with the voltage V.sub.T1, such as provided from the CC/CV compensation system 64. In response to the voltage V.sub.RS increasing to an amplitude that is approximately equal to (e.g., just greater than) the voltage V.sub.T1, at approximately a time T.sub.1, the switching controller 60 can be configured to de-assert the signal PWM.sub.1 to deactivate the N-FET Q.sub.1 via the first switching signal SW.sub.1. Thus, at approximately the time T.sub.1, the primary current I.sub.P can have an amplitude that is sufficient for the secondary current I.sub.S to maintain the substantially constant amplitude of the output voltage V.sub.OUT and/or substantially constant amplitude of the output current IOUT. In response to deactivation of the N-FET Q.sub.1, the magnetizing current I.sub.M can begin to decrease linearly from a maximum amplitude of I.sub.M+, and the voltage V.sub.RS can substantially immediately decrease to approximately zero volts. Additionally, the switching voltage V.sub.SW can substantially immediately increase to a maximum amplitude, and the voltage V.sub.S can likewise immediately increase to a maximum amplitude (e.g., approximately proportional to the turns ratio between the secondary winding N.sub.S and the auxiliary winding N.sub.A times the output voltage V.sub.OUT). Furthermore, the ramp signal V.sub.R, generated by the ramp generator 62, can begin to increase linearly at an increment rate that is proportional to the rate of decay (decrease) of the magnetizing current I.sub.M.

(30) At approximately a time T.sub.2, the switching controller 60 can be configured to assert the signal PWM.sub.2. For example, the switching controller 60 can provide subsequent assertion of the signal PWM.sub.2 after de-assertion of the signal PWM.sub.1 based on a predetermined dead-time to prevent shoot-through of current through concurrently activated N-FETs Q.sub.1 and Q.sub.2. At a time T.sub.3, the decreasing magnetizing current I.sub.M can reverse direction by demagnetizing the magnetizing inductance L.sub.M with the voltage of resonant capacitor C.sub.1. As a result, the negative magnetizing current I.sub.M can operate to discharge the stored capacitance in the switching node 58. As an example, the switching node 58 can have parasitic capacitance associated with the primary inductor N.sub.P, the N-FET Q.sub.1, the N-FET Q.sub.2 and/or other sources of parasitic capacitance. As described in greater detail herein, by discharging the stored capacitance in the switching node, the N-FET Q.sub.1 can be subsequently activated in a ZVS manner.

(31) Subsequent to the time T.sub.3, as described in greater detail herein, the switching controller 60 can be configured to compare the ramp signal V.sub.R with the voltage V.sub.T2. As an example, as described in greater detail herein, the voltage V.sub.T2 can be generated as a difference voltage that is added to the voltage V.sub.T1, and can be tunable after startup of the power converter circuit 50, such as based on changing operational conditions of the power converter circuit 50. In response to the ramp signal V.sub.R increasing to an amplitude that is approximately equal to (e.g., just greater than) the voltage V.sub.T2, at approximately a time T.sub.4, the switching controller 60 can be configured to de-assert the signal PWM.sub.2 to deactivate the N-FET Q.sub.2 via the second switching signal SW.sub.2. At approximately the time T.sub.4, the magnetizing current I.sub.M has a negative peak amplitude equal to approximately I.sub.M− (e.g., as defined by Equation 2 previously) that can correspond to an amplitude that is approximately sufficient to substantially discharge the capacitance of the switching node 58.

(32) In response to deactivation of the N-FET Q.sub.2, the magnetizing inductor L.sub.M can switch polarity, causing the magnetizing current I.sub.M to begin to increase (e.g., become less negative) linearly. In addition, the voltage V.sub.S can likewise decrease rapidly at approximately the time T.sub.4, and can ring slightly before settling to the negative amplitude. Similarly, in response to the deactivation of the N-FET Q.sub.2, the switching voltage V.sub.SW can begin to decrease rapidly. Upon decrease of the switching voltage V.sub.SW to less than the threshold voltage V.sub.TH at approximately a time T.sub.5, the switching controller 60 can assert the signal PWM.sub.1, similar to as described previously at approximately the time T.sub.0. Accordingly, the power converter circuit 50 can repeat the control of the respective signals PWM.sub.1 and PWM.sub.2 with respect to assertion and de-assertion, and thus the activation and deactivation of the respective N-FETs Q.sub.1 and Q.sub.2.

(33) FIG. 4 illustrates an example of a switching controller 150. The switching controller 150 can correspond to the switching controller 60 in the example of FIG. 2. Therefore, reference is to be made to the example of FIGS. 2 and 3 in the following description of the example of FIG. 4.

(34) The switching controller 150 is configured to receive, as inputs, the voltage V.sub.RS, the switching voltage V.sub.SW, the voltage V.sub.S, and the voltage V.sub.T1. The switching controller 150 includes a comparator 152 that is configured to compare the voltage V.sub.S and the voltage V.sub.T1. In the example of FIG. 4, the comparator 152 receives the voltage V.sub.RS at a non-inverting input, and the voltage V.sub.T1 at an inverting input. The comparator 152 thus provides a first comparison signal CMP1 that is logic-high in response to the voltage V.sub.RS increasing greater than the voltage V.sub.T1, such as demonstrated at approximately the time T.sub.1 in the example of FIG. 3. The first comparison signal CMP1 is provided to a reset input of an SR latch 154 to thus de-assert the signal PWM.sub.1, provided from the Q output of the SR latch 154. The switching controller 150 also includes a ZVS discriminator 156 that is configured to generate an activation signal ACT in response to the switching voltage V.sub.SW and based on the threshold voltage V.sub.TH. For example, in response to the switching voltage V.sub.SW decreasing less than the threshold voltage V.sub.TH, such as demonstrated at approximately the times T.sub.0 and T.sub.5 in the example of FIG. 3, the ZVS discriminator 156 can assert the activation signal ACT that is provided to the set input of the SR latch 154 to assert the signal PWM.sub.1. In addition, as described in additional detail herein, the ZVS discriminator 156 can generate a tuning signal TN, such as based on detecting a non-zero switching condition associated with the switching of the N-FET Q.sub.1.

(35) The switching controller 150 also includes a V.sub.S sampler circuit 158 that is configured to generate sample voltages associated with the voltage V.sub.S. As an example, the voltage V.sub.S can be sampled by the respective signals PWM.sub.1 and PWM.sub.2. For example, the voltage V.sub.S can be sampled at each of the substantially stable amplitudes of the voltage V.sub.S, such as after stabilization, by the respective signals PWM.sub.1 and PWM.sub.2. Thus, the V.sub.S sampler circuit 158 can provide a first sampled voltage V.sub.SMPL1 and a second sampled voltage V.sub.SMPL2. For example, the first sampled voltage V.sub.SMPL1 can be associated with the voltage V.sub.S being sampled at a substantially maximum amplitude (e.g., positive plateau) via the signal PWM.sub.1, and the second sampled voltage V.sub.SMPL2 can be associated with the voltage V.sub.S being sampled at a substantially minimum amplitude (e.g., negative plateau) via the signal PWM.sub.1.

(36) The second sampled voltage V.sub.SMPL2 is provided to a ZVS optimizer 160 that is configured to generate the voltage V.sub.T2. As an example, the ZVS optimizer 160 can include a transconductance amplifier that is configured to generate the voltage V.sub.T2 based on the second sampled voltage V.sub.SMPL2 and based on the voltage V.sub.T1. For example, the ZVS optimizer 160 can be circuitry configured to generate a difference voltage that is added to the voltage V.sub.T1 to provide the voltage V.sub.T2. Additionally, the ZVS optimizer 160 is provided the tuning signal TN that is configured to adjust an amplitude of the voltage V.sub.T2, such as in response to detection of a non-zero voltage switching condition of the N-FET Q.sub.1. Furthermore, the ZVS optimizer 160 is demonstrated in the example of FIG. 4 as being tuned by an externally provided resistor R.sub.ZVS. As an example, the externally provided resistor R.sub.ZVS can be coupled to the IC package (e.g., via one or more pins) by a respective customer to set a transconductance of the associated transconductance amplifier to tune the amplitude of the voltage V.sub.T2. Accordingly, the voltage V.sub.T2 can be associated with a zero-voltage switching condition of the N-FET Q.sub.1 with respect to the ramp signal V.sub.R, as described herein.

(37) The first sampled voltage V.sub.SMPL1 is provided to a ramp generator 162 that is configured to generate the ramp signal (e.g., ramp voltage) V.sub.R. As an example, the ramp generator 162 can include a transconductance amplifier that is configured to generate the ramp signal V.sub.R based on the first sampled voltage V.sub.SMPL1 and based on the signal PWM.sub.2. For example, the positive slope of the ramp signal V.sub.R can be proportional to a rate of decay of the magnetizing current I.sub.M, such that the ramp signal V.sub.R can be indicative of the slope of the magnetizing current I.sub.M. Furthermore, the ramp generator 162 is demonstrated in the example of FIG. 4 as being tuned by an externally provided resistor R.sub.R. As an example, the externally provided resistor R.sub.R can be coupled to the IC package (e.g., via a pin) by a respective customer to set a transconductance of the associated transconductance amplifier to tune the slope of the ramp signal V.sub.R.

(38) The switching controller 150 further includes a comparator 164 that is configured to compare the ramp signal V.sub.R and the voltage V.sub.T2. In the example of FIG. 4, the comparator 164 receives the ramp signal V.sub.R at a non-inverting input and receives the voltage V.sub.T2 at an inverting input. Therefore, in response to the voltage V.sub.R increasing to an amplitude that is approximately equal to (e.g., just greater than) the voltage V.sub.T2, such as at approximately the time T.sub.4 in the example of FIG. 3, the comparator 164 can provide a second comparison signal CMP2 that is provided to a reset input of an SR latch 166. The SR latch 166 is configured to generate the signal PWM.sub.2 at a Q output. Therefore, the SR latch 166 can de-assert the signal PWM.sub.2 in response to the second comparison signal CMP2. The SR latch 166 also receives a delayed inverted version of the signal PWM.sub.1 at the set input, as provided from the Q′ output of the SR latch 154 and provided via a buffer 168. For example, the buffer 168 can provide a requisite dead-time delay for delaying assertion of the signal PWM.sub.2 in response to de-assertion of the signal PWM.sub.1.

(39) FIG. 5 illustrates an example of a switching controller 200. The switching controller 200 can correspond to a portion of the switching controller 150 in the example of FIG. 4. Particularly, the switching controller 200 demonstrates a V.sub.S sampler circuit 202, a ZVS optimizer 204, and a ramp generator 206 that can correspond to the V.sub.S sampler circuit 158, the ZVS optimizer 160, and the ramp generator 162, respectively, in the example of FIG. 3. Therefore, reference is to be made to the example of FIGS. 2-4 in the following description of the example of FIG. 5.

(40) The V.sub.S sampler circuit 202 includes a first sensing component 208 and a second sensing component 210 that are configured to sample the voltage V.sub.S. In the example of FIG. 5, the first sensing component 208 is configured to sample the voltage V.sub.S in response to assertion of the signal PWM.sub.2 to provide a first sample voltage V.sub.SMPL1. As an example, the first sample voltage V.sub.SMPL1 can be expressed as:
V.sub.SMPL1=K.sub.1*(N.sub.P/N.sub.S)*V.sub.OUT  Equation 3

(41) Where: K.sub.1 is a constant corresponding to the sampling of the voltage V.sub.S, expressed as:
K.sub.1=(N.sub.A/N.sub.P)*R.sub.2/(R.sub.1+R.sub.2)  Equation 4

(42) Where:N.sub.A/N.sub.P is a turns ratio between the auxiliary winding N.sub.A and the primary winding N.sub.P.

(43) Similarly, the second sensing component 210 is configured to sample the voltage V.sub.S in response to assertion of the signal PWM.sub.1 to provide a second sample voltage V.sub.SMPL2. The voltage V.sub.S, at the time of sampling via the signal PWM.sub.1, has a negative amplitude, and thus is provided to the second sensing component 210 via an N-FET N.sub.3 having a drain coupled to the second sensing component 210, a source coupled to the voltage V.sub.S, and a gate coupled to a low-voltage rail (e.g., ground). The second sensing component 210 is configured to generate a voltage V.sub.SL that is added to the first sample voltage V.sub.SMPL1 via a summer 212 to generate the second sample voltage V.sub.SMPL2. In the example of FIG. 5, the gate of the N-FET N.sub.3 is coupled to the low-voltage rail, and the voltage V.sub.SL is separated from the low-voltage rail via a resistor R.sub.3. As an example, the resistor R.sub.3 can be expressed as:
R.sub.3=(R.sub.1*R.sub.2)/(R.sub.1+R.sub.2)  Equation 5
Thus, the second sample voltage V.sub.SMPL2 can be expressed as:
V.sub.SMPL2=K.sub.1*(V.sub.IN+(N.sub.P/N.sub.S)*V.sub.OUT)  Equation 6

(44) The first sample voltage V.sub.SMPL1 is provided to the ramp generator 206, and is particularly provided as an input to a transconductance amplifier 214 that is configured to generate the ramp signal V.sub.R at an output node 216. The ramp generator 206 includes a capacitor C.sub.R and a switch S.sub.1 that are arranged in parallel between the output node 216. The switch S.sub.1 is controlled by the signal PWM.sub.1. Additionally, in the example of FIG. 5, the transconductance amplifier 214 includes a resistor R.sub.R that is provided externally (e.g., via an IC package pin) to set the gain of the transconductance amplifier 214. As an example, the resistor R.sub.R can have a resistance value expressed as follows:
R.sub.R=K.sub.1*K.sub.R*L.sub.M/(R.sub.S*C.sub.R)  Equation 7
Where: K.sub.R is a gain constant of the transconductance amplifier 214, such that the gain of the transconductance amplifier 214 is defined as (K.sub.R/R.sub.R).

(45) Therefore, in response to the first sample voltage V.sub.SMPL1, the transconductance amplifier 214 can provide a current based on the external resistor R.sub.R, which can charge the capacitor C.sub.R while the switch S.sub.1 is open based on the signal PWM.sub.1 being de-asserted.

(46) As a result, the ramp generator 206 generates the ramp signal V.sub.R having a linear slope that is proportional to the decay rate of the magnetizing current I.sub.M based on the first sample voltage V.sub.SMPL1. As an example, the slope ramp signal S.sub.R corresponding to the ramp voltage V.sub.R can be expressed as follows:
S.sub.R=K.sub.1*(N.sub.P/N.sub.S)*V.sub.OUT*K.sub.R/(R.sub.R*C.sub.R)=(N.sub.P/N.sub.S)*V.sub.OUT*R.sub.S/L.sub.M  Equation 8

(47) Thus, the ramp signal V.sub.R can be generated to be substantially free of noise and drift that can result in errors in the de-assertion of the signal PWM.sub.2, and thus the zero-volt switching of the N-FET Q.sub.1.

(48) In response to the ramp signal V.sub.R having an amplitude that is approximately equal to the voltage V.sub.T2, such as at approximately the time T.sub.4 in the example of FIG. 3, the switching controller 150 is configured to de-assert the signal PWM.sub.2 (e.g., via the comparator 164 and the SR latch 166 in the example of FIG. 4), and to thus subsequently assert the signal PWM.sub.1 (e.g., via the ZVS discriminator 156, as described in greater detail herein). Upon assertion of the signal PWM.sub.1, the switch S.sub.1 closes to couple the output node 216 to the low-voltage rail (e.g., ground), and to thus reset the ramp signal V.sub.R. Upon de-assertion of the signal PWM.sub.1, the switch S.sub.1 can open again, and thus the transconductance amplifier 214 can begin to generate the ramp signal V.sub.R again, as described previously.

(49) The second sample voltage V.sub.SMPL2 is provided to the ZVS optimizer 204, and is particularly provided an input to a transconductance amplifier 218 that is configured to generate the voltage V.sub.T2 at an output node 220. The ZVS optimizer 204 also includes a tuner circuit 222 and a resistor R.sub.4 that are coupled to the output node 220. In the example of FIG. 5, the transconductance amplifier 218 includes a resistor R.sub.ZVS that is provided externally (e.g., via an IC package pin) to set the gain of the transconductance amplifier 218. As an example, the resistor R.sub.ZVS can have a resistance value defined as:

(50) $\begin{array}{cc}{R}_{\mathrm{ZVS}}=K_1*K_{\mathrm{ZVS}}*R_4/\left(R_S*K_O*\sqrt{\frac{C_{\mathrm{SW}}}{L_M}}\right)& \mathrm{Equation}9\end{array}$

(51) Where: K.sub.ZVX is a gain constant of the transconductance amplifier 218, such that the gain of the transconductance amplifier 214 is defined as (K.sub.ZVS/R.sub.ZVX).

(52) The tuner circuit 222 is configured to receive the tuning signal TN, and can generate a tuning current I.sub.TN that is provided to the output node 220. As an example, the tuning circuit 222 can be configured as a switchable network of current mirrors that are configured to provide incremental portions of the tuning current I.sub.TN that can increase the amplitude of the voltage V.sub.T2. Additionally, the resistor R.sub.4 separates the voltage V.sub.T1 from the output node 220, and thus has a difference voltage ΔV.sub.T across the resistor R.sub.4. Accordingly, the voltage V.sub.T2 can be expressed as a sum of the voltage V.sub.T1 and the difference voltage ΔV.sub.T. The difference voltage ΔV.sub.T is generated by a current sum of a feedforward current signal and a tuning current I.sub.TN flowing though resistor R.sub.4. The feedforward signal comprises a transconductance amplifier 218 having a transconductance constant that is set via an external resistor R.sub.ZVS to set the feedforward gain for the amplifier input, which is the sampled auxiliary voltage V.sub.SMPL2. The external resistor configures the feedforward gain based on a predetermined power stage parameter, which can be expressed as C.sub.SW/L.sub.M.

(53) The difference voltage ΔV.sub.T can be additionally tuned (as described in greater detail herein) based on the tuning current I.sub.TN to further increase or decrease the amplitude of the voltage V.sub.T2. The voltage V.sub.T2 can thus be generated based on the amplitude of the magnetizing current I.sub.M sufficient to provide the zero-volt switching, as provided in Equation 2. As an example, the voltage V.sub.T2 can be expressed as follows:

(54) $\begin{array}{cc}{V}_{T2}=V_{T1}+\left[\left(R_S*K_0*\sqrt{\frac{C_{\mathrm{SW}}}{L_M}}\right)*\left(V_{\mathrm{IN}}+\left(N_P/N_S\right)*V_{\mathrm{OUT}}\right)+I_{\mathrm{TN}}\right]*R_4& \mathrm{Equation}10\end{array}$

(55) Equation 10 thus demonstrates that the voltage V.sub.T2 is generated as a result of the input voltage V.sub.IN, the output voltage V.sub.OUT, the predetermined parameter (C.sub.SW/L.sub.M) of the power stage, and a tuning signal I.sub.TN 54. Accordingly, ZVS optimizer 204 can generate the voltage V.sub.T2 in a manner that provides dynamic zero-volt switching of the N-FET Q.sub.1 in response to changes in the input voltage V.sub.IN, the output voltage V.sub.OUT based on the feed forward signal, and correct any error from the feedforward gain setting by a tuning signal I.sub.TN.

(56) FIG. 6 illustrates an example of a zero-voltage switching (ZVS) discriminator 250. The ZVS discriminator 250 can correspond to the ZVS discriminator 156 in the example of FIG. 4. Therefore, reference is to be made to the examples of FIGS. 2-4 in the following description of the example of FIG. 6.

(57) The ZVS discriminator 250 includes a comparator 252 that is configured to compare the switching voltage V.sub.SW and the threshold voltage V.sub.TH. In the example of FIG. 6, the comparator 252 receives the threshold voltage V.sub.TH, demonstrated as being generated via a voltage source 254, at a non-inverting input, and a voltage V.sub.SWV at an inverting input. The voltage V.sub.SWV corresponds to the switching voltage V.sub.SW having been provided via a high voltage blocking circuit (“HIGH V BLOCKING”) 256. As an example, the high voltage blocking circuit 256 is configured to block the switching voltage V.sub.SW at an amplitude that is greater than a predetermined threshold. For example, the high voltage blocking circuit 256 can be configured in a variety of ways, such as including an arrangement of diode(s), a JFET, an LDMOS transistor, or a variety of other ways to block amplitudes of the switching voltage above a predetermined threshold (e.g., approximately five volts).

(58) FIG. 7 illustrates a diagram 300 of separate examples of high-voltage blocking circuits. The diagram 300 demonstrates three separate examples of high-voltage blocking systems, demonstrated at 302, 304, and 306, respectively, that could each be configured as the high voltage blocking circuit 256 in the example of FIG. 6. Therefore, reference is to be made to the example of the example of FIG. 6 in the following discussion of the example of FIG. 7.

(59) The first example of a high-voltage blocking circuit 302 includes a gate control circuit 308 that controls a gate of a JFET Q.sub.3 via a gate control signal GC. As an example, the JFET Q.sub.3 can be configured as a high-voltage N-channel JFET. The JFET Q.sub.3 has a drain that is coupled to the switching voltage V.sub.SW and a source that provides the voltage V.sub.SWV. Therefore, the gate control circuit 308 can be configured to control an activation state of the JFET Q.sub.3 to substantially block a high-voltage amplitude of the voltage V.sub.SW. For example, the gate control circuit 308 can be configured to hold the gate voltage of the JFET Q.sub.3 to a relatively high voltage based on the gate control signal GC for high-voltage start up of the power converter circuit 50, and can subsequently decrease the gate voltage of the JFET Q.sub.3 based on the gate control signal GC for sensing the switching voltage V.sub.SW and protecting the ZVS discriminator 250 from high-voltage amplitudes of the switching voltage V.sub.SW.

(60) The second example of a high-voltage blocking circuit 304 includes an LDMOS Q.sub.4 that has a gate coupled to a 5V voltage source (e.g., from a low-dropout voltage source). The LDMOS Q.sub.4 has a drain that is coupled to the switching voltage V.sub.SW and a source that provides the voltage V.sub.SWV. Additionally, the source of the LDMOS Q.sub.4 is coupled to an anode of a diode D.sub.HV1, with the diode D.sub.HV1 having a cathode that is coupled to the 5V voltage source. Additionally, the LDMOS Q.sub.4 includes a body-diode D.sub.B that interconnects the source and the drain of the LDMOS Q.sub.4. Thus, the LDMOS Q.sub.4 acts as a diode interconnecting the switching voltage V.sub.SW and the inverting input of the comparator 252. Accordingly, the LDMOS Q.sub.4 can provide high-voltage blocking of the switching voltage V.sub.SW.

(61) The third example of a high-voltage blocking circuit 306 includes a resistor R.sub.HV interconnecting a high-voltage power rail (e.g., the voltage VDD) and the inverting input of the comparator 252 on which the voltage V.sub.SWV is provided. An anode of a diode D.sub.HV2 is likewise coupled to the inverting input of the comparator 252 on which the voltage V.sub.SWV is provided, with the diode D.sub.HV2 having a cathode that is coupled to the high-voltage rail. Additionally, the third example of a high-voltage blocking circuit 306 includes a diode D.sub.HV3 that interconnects the inverting input of the comparator 252 on which the voltage V.sub.SWV is provided at an anode and the switching voltage V.sub.SW at a cathode. Thus, the third example of a high-voltage blocking circuit 306 is arranged similar to the second example of the high-voltage blocking circuit 304, except that it substitutes the LDMOS Q.sub.4 with the diode D.sub.HV3. Accordingly, the diode D.sub.HV3 can provide high-voltage blocking of the switching voltage V.sub.SW.

(62) Referring back to the example of FIG. 6, in response to the switching voltage V.sub.SW decreasing less than the threshold voltage V.sub.TH (e.g., less than one volt), then the comparator 252 is configured to assert an output signal L.sub.1 that is provided as an input to a logic OR gate 258. The logic OR gate 258 can thus assert a signal output L.sub.2 that is provided as an input to a logic AND gate 260. The logic AND gate 260 also receives the signal PWM.sub.1 and the signal PWM.sub.2 at inverted inputs, such that the logic AND gate 260 is configured to assert the activation signal ACT in response to the switching voltage V.sub.SW decreasing less than the threshold voltage V.sub.TH, via the output signal L.sub.2, while the signals PWM.sub.1 and PWM.sub.2 are logic-low. As demonstrated in the example of FIG. 4, the activation signal ACT is provided to the SR latch 154 to assert the signal PWM.sub.1.

(63) In addition, in the example of FIG. 6, the ZVS discriminator 250 also includes a timer 262. The timer 262 is configured to implement a timer count sequence in response to a falling-edge of the signal PWM.sub.2. As an example, the timing associated with the zero-volt switching of the N-FET Q.sub.1 may not be correct, in that it is possible that the N-FET Q.sub.1 is commanded to activate too soon (e.g., at initialization of the power converter circuit 50), such as prior to the magnetizing current I.sub.M flowing negative for sufficient time to discharge the capacitance of the switching node 58. Thus, in response to de-assertion of the signal PWM.sub.2, the presence of capacitive charge on the switching node 58 can be such that the switching voltage V.sub.SW does not decrease to approximately zero volts, but could instead decrease to a non-zero positive amplitude that is greater than the threshold voltage V.sub.TH. As a result, in that example, the comparator 252 would not assert the output signal L.sub.1, likewise resulting in the activation signal ACT never being activated.

(64) Therefore, the timer 262 is configured to monitor the time-elapsed since de-assertion of the signal PWM.sub.2, and to assert a dead-time signal DT in response to the timer value being equal to a predetermined dead-time that indicates that the switching voltage V.sub.SW did not decrease less than the threshold voltage V.sub.TH. The dead-time signal DT can thus be provided to the logic OR gate 258 to assert the output signal L.sub.2, and thus to ensure that the activation signal ACT is asserted to subsequently assert the signal PWM.sub.1.

(65) In addition, the dead-time signal DT is provided to a logic AND gate 264 along with an inverted version of the output signal L.sub.1. In response to the dead-time signal DT being asserted the logic AND gate 264 can assert the tuning signal TN. The tuning signal TN is provided to the tuner circuit 222 in the example of FIG. 5. As a result, in response to the tuning signal TN being provided to the tuner circuit 222, the tuner circuit 222 can be configured to provide a current increment to the output node 220 of the ZVS optimizer 204 to increase the voltage V.sub.T2. For example, the tuner circuit 222 can be configured as a shift register that is configured to selectively activate one or more current mirrors that each provide a predetermined current increment, such that each time the tuning signal TN is provided to the tuner circuit 222, an additional current mirror can be activated to provide a respective additional current increment to the output node 220 of the ZVS optimizer 204.

(66) As a result of the increase of the voltage V.sub.T2, the ramp signal V.sub.R linearly increases for a longer duration of time. Because the slope of ramp signal V.sub.R is proportional to the decay rate of magnetizing current I.sub.M, the magnetizing current I.sub.M thus flows in the negative direction for a longer duration of time to discharge more of the capacitive charge from the switching node 58. As a result, in response to de-assertion of the signal PWM.sub.2, the switching voltage V.sub.SW can decrease to a lesser amplitude based on the decrease in the capacitive charge stored in the switching node 58. The ZVS discriminator 250 can therefore provide the tuning signal TN to iteratively tune the voltage V.sub.T2 to set the voltage V.sub.T2 to eventually correspond to the sufficient duration, and thus sufficient negative amplitude, of the magnetizing current I.sub.M that provides for zero-volt switching of the N-FET Q.sub.1.

(67) On the other hand, when the switching voltage reaches the threshold voltage V.sub.TH before the dead-time signal DT time elapsed, the tuning signal TN cannot be asserted. Therefore, the tuner circuit 222 can be configured to provide a current decrement to the output node 220 of the ZVS optimizer 204 to reduce the voltage V. For example, the tuner circuit 222 can be configured as a shift register that is configured to selectively deactivate one or more current mirrors that each provide a predetermined current decrement, such that when the tuning signal TN for a switching cycle is not provided to the tuner circuit 222, a reduced number of mirrored currents can provide a respective current decrement to the output node 220 of the ZVS optimizer 204.

(68) As a result of the decreasing of the voltage V.sub.T2, the ramp signal V.sub.R linearly decreases for a shorter duration of time. Because the slope of ramp signal V.sub.R is proportional to the decay rate of magnetizing current I.sub.M, the magnetizing current I.sub.M thus flows in the negative direction for a shorter duration of time to discharge less of the capacitive charge from the switching node 58. As a result, in response to de-assertion of the signal PWM.sub.2, the switching voltage V.sub.SW can reach the threshold voltage V.sub.TH closer to the dead-time signal DT elapsed time. As a result, the negative magnetizing current I.sub.M does not decrease unnecessarily larger than the amplitude necessary that is sufficient for the switching voltage V.sub.SW to be approximately equal to the threshold voltage V.sub.TH during a given elapsed time of the dead-time signal DT.

(69) What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements. As used herein, the term “includes” means includes but not limited to, and the term “including” means including but not limited to. The term “based on” means based at least in part on.