Abstract
A ferroelectric static random access memory (FeSRAM) cell includes (a) first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; (b) first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and (c) first, second, third and fourth ferroelectric capacitors, wherein the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.
Claims
1. A ferroelectric static random access memory (FeSRAM) cell, capable of operating under a static random access memory (SRAM) phase and a ferroelectric capacitor programming phase, comprising: first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and first, second, third and fourth ferroelectric capacitors, wherein, during the SRAM phase, the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.
2. The FeSRAM cell of claim 1, wherein first select transistor is formed at the surface of a semiconductor substrate, and wherein the first and second ferroelectric capacitors are implemented between conductor layers above the select transistor within the silicon footprint of the first select transistor.
3. The FeSRAM cell of claim 1, wherein the power supply voltage signal selectably provides a first voltage and a second voltage and wherein the second voltage selectably programs one or more of the ferroelectric capacitors to a non-volatile state.
4. The FeSRAM cell of claim 3, wherein the first voltage selectably programs one or more of the ferroelectric capacitors to a volatile state.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1(a) illustrates the programmed states of storage operations of storage capacitor 100 when used as a non-volatile memory circuit.
(2) FIG. 1(b) illustrates the programmed states of storage operations of storage capacitor 100 when used as a volatile memory circuit
(3) FIG. 1(c) shows storage capacitor 100, which is a simple model of a ferroelectric memory circuit.
(4) FIG. 2(a) shows a ferroelectric static random access memory (FeSRAM) cell 200, which operate as a non-volatile memory cell.
(5) FIG. 2(b) shows, when power is restored, voltage signal VPW at the power supply line of the SRAM cell, voltage signal PL on the plate line and voltage signals BT and BC at the input terminals of the cross-coupled inverters of the SRAM cell.
(6) FIG. 2(c) shows, before FeSRAM cell 200 is powered down, voltage signal VPW at the power supply line of the SRAM cell, voltage signal PL on the plate line and voltage signals BT and BC at the input terminals of the cross-coupled inverters of the SRAM cell.
(7) FIG. 3(a) shows FeSRAM cell 300, in accordance with one embodiment of the present invention.
(8) FIG. 3(b) shows the operations to write the signal states at terminals 204a and 204b of the cross-coupled inverters into some of the ferroelectric capacitors C0U, C1U, C0D and C1D.
(9) FIG. 3(c) shows, upon restoring power, the operations to restore the states of signals BT and BC at terminals 204a and 204b, respectively, according to one embodiment of the present invention.
(10) FIG. 4(a) summarizes storing non-volatile states in ferroelectric capacitors C1D and C1U of FeSRAM 300, when terminal 204a is at the V.sub.PP and terminal 204b is at ground voltage at the time of writing into the ferroelectric capacitors in preparation of powering down.
(11) FIG. 4(b) summarizes storing non-volatile states in ferroelectric capacitors C0D and C0U of FeSRAM 300, when terminal 204b is at the V.sub.PP and terminal 204a is at ground voltage at the time of writing into the ferroelectric capacitors in preparation of powering down.
(12) FIGS. 5(a) and 5(b) illustrate how select transistor 201b and ferroelectric capacitors C1U and C0D may be implemented on the same silicon footprint of select transistor 201b.
(13) To facilitate cross-referencing and to simplify the detailed description below, like elements in the figures are assigned like reference numerals.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(14) The present invention provides for the programming needs of an FeSRAM cell without requiring a plate line. FIG. 3(a) shows FeSRAM cell 300, in accordance with one embodiment of the present invention. As shown in FIG. 3, like FeSRAM cell 200 of FIG. 2, FeSRAM cell 300 includes a conventional 6-transistor SRAM cell. To simplify this detailed description, the transistors of the conventional SRAM cells in FeSRAM cells 200 and 300 are assigned like reference numerals. Unlike FeSRSAM cell 200, having two ferroelectric storage capacitors C0 and C1 connected to a plate line, FeSRAM cell 300 includes four ferroelectric storage capacitors C0U, C1U, C1D and C0D, without a plate line. Instead, ferroelectric storage capacitors C0U and C1U are coupled across power supply voltage VPW and cross-coupled inverter terminals 204a and 204b, respectively. Ferroelectric capacitors C1D and C0D are connected across cross-coupled inverter terminals 204a and 204b and the ground reference voltage (V.sub.SS),
(15) FIG. 3(b) shows the operations to write the signal states at terminals 204a and 204b of the cross-coupled inverters into some of the ferroelectric capacitors C0U, C1U, C0D and C1D. In FIG. 3(b), initially, supply voltage VPW is at voltage V.sub.CC, voltage BT is at voltage V.sub.CC, while voltage BC is at 0 volts, suggesting that transistors 203a and 202b are conducting while transistors 203b and 202a are not conducting. As shown in FIG. 3(b), voltage VPW is brought to programming voltage V.sub.PP, which in turn, brings terminal 204a to programming voltage V.sub.PP as well, while the voltage at terminal 204b remains at 0 volts. As a result, programming voltage V.sub.PP is imposed across ferroelectric capacitors C1D and C1U, thus writing ferroelectric capacitor C1D to the non-volatile “1” state and ferroelectric capacitor C1U to the non-volatile ‘0’ state. As full programming voltage V.sub.PP does not appear across ferroelectric capacitors C0U and C0D in these operations, the states in ferroelectric capacitors C0U and C0D are volatile states and are lost upon powering down. The preceding description therefore corresponds to the case when terminal 204a is at the V.sub.PP and terminal 204b is at ground voltage at the time of writing into capacitor C1D and C1U. FIG. 4(a) summarizes this condition, pointing out that the programmed states at ferroelectric capacitors C0U and C0D are volatile and not preserved by the power down.
(16) FIG. 3(c) shows, upon restoring power, the operations to restore the states of signals BT and BC at terminals 204a and 204b, respectively, according to one embodiment of the present invention. As shown in FIG. 3(c), when power is restored, the non-volatile states of ferroelectric capacitors C1U and C1D restore terminals 204a and 204b to V.sub.CC and 0 volts, respectively, thus restoring them to their previous states prior to powering down.
(17) In the event that, at the time of programming non-volatile states into the ferroelectric capacitors, terminal 204b is at the V.sub.PP and terminal 204a is at ground voltage, non-volatile states would be written into ferroelectric capacitor C0U and C0D, and volatile states (that are not preserved by the power down) would be written into ferroelectric capacitors C1D and C1U. This condition is summarized in FIG. 4(b).
(18) By eliminating the plate line, FeSRAM cell 300 may be provided at the same size as the conventional 6-transistor SRAM cell. This is achieved by providing the ferroelectric capacitors between conductor layers above the conventional 6-transistor SRAM cell. For example, FIGS. 5(a) and 5(b) illustrate how select transistor 201b and ferroelectric capacitors C1U and C0D (i.e., the combination shown in the dashed oval of FIG. 5(a)) may be implemented on the same silicon footprint of select transistor 201b. FIG. 5(b) shows select transistor 201b being implemented by gate electrode WL and source and drain regions BC and BLC separated by a channel region. Contact CONT connects source region BC to the common capacitor plate MO in a first conductor layer. The other capacitor plates of capacitor C1U and C0D are implemented on a second conductor layer separated by ferroelectric material. As shown in FIG. 5(c), power supply voltage VPW is routed to the capacitor plate of ferroelectric capacitor C1U at the second conductor level, while ground reference voltage V.sub.SS is routed to the capacitor plate of ferroelectric capacitor C0D at the second conductor level.
(19) In addition to its compact size, a FeSRAM of the present invention also has the advantage of not having to provide a decoder for signal PL of the plate line, which is eliminated.
(20) The above detailed description is provided to illustrate specific embodiments of the present invention and is not to be taken as limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.
