METHOD FOR PROCESSING A MEASURED-VALUE SIGNAL DETERMINED IN AN ANALOG MANNER, A RESOLVER SYSTEM FOR IMPLEMENTING THE METHOD AND A METHOD FOR DETERMINING AN OUTPUT CURRENT OF A CONVERTER

Abstract

In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency f.sub.S, that is, at a clock-pulse period T.sub.S=1/f.sub.S, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency f.sub.D, that is, at a clock-pulse period T.sub.D=1/f.sub.D, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.

Claims

1-18. (canceled)

19. A method for processing a measured-value signal determined in an analog manner, comprising: supplying the measured-value signal to a delta-sigma modulator, which makes a bit stream available on an output side; supplying the bit stream to a first digital filter, the first digital filter having a number n of serially arranged accumulators, n being a whole number and equal to at least 1; converting the bit stream, by the first digital filter, into a stream of digital intermediate words, the bit stream being clocked at a clock-pulse frequency fS and a clock-pulse period TS=1/fS, and the stream of digital intermediate words being clocked and updated at a clock-pulse frequency fS and a clock-pulse period TS=1/fS, and supplying an output signal of the first digital filter to a second digital filter.

20. The method according to claim 19, wherein the bit stream includes a one-bit data stream.

21. The method according to claim 19, wherein the stream of digital intermediate words includes a multi-bit data stream.

22. The method according to claim 19, wherein the serially arranged accumulators include integrators.

23. The method according to claim 19, wherein the second digital filter produces a difference between a first and a second result data-word stream as an output data-word stream, the first and second result data-word stream being determined over a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined from the intermediate data-word stream as a time discrete differential of the (n−1)th order at time scale TD, and the second result data-word stream being determined from the intermediate data-word stream as a time-discrete differential of the (n−1)th order at time scale TD, the distance in time T1 being alterable to at least one of (a) being greater than the time scale TD, (b) being an integral multiple of clock-pulse period TS, and (c) not being an integral multiple of time scale TD.

24. A resolver system adapted to detect an angular position of a rotor in relation to a stator, the rotor bearing a rotor coil and the stator having two stator coils that are mutually shifted in a circumferential direction by 90°, the rotor coil having a carrier signal produced by a carrier signal generator applied to it, wherein each signal occurring at a respective stator coil is supplied as a respective measured-value signal to a respective processing channel, the resolver system adapted to perform the method recited in claim 19.

25. A method for processing a measured-value signal determined in an analog manner, comprising: supplying the measured-value signal to a delta-sigma modulator, which makes a bit stream available on an output side, at least one of (a) an average value and (b) a moving average corresponding to the measured-value signal; supplying the bit stream to a first digital filter that converts the bit stream into a stream of digital intermediate words, the first digital filter having a number n of serially disposed accumulators, where n is an integer and is at least 1, the bit stream being clocked at a clock-pulse frequency fS and a clock-pulse period TS=1/fS, and the stream of digital intermediate words being clocked and updated at a clock-pulse frequency fS and clock-pulse period TS=1/fS, and supplying an output signal of the first digital filter to a second digital filter.

26. The method according to claim 25, wherein the bit stream includes a one-bit data stream.

27. The method according to claim 25, wherein the stream of digital intermediate words includes a multi-bit data stream.

28. The method according to claim 25, wherein the serially disposed accumulators include integrators.

29. The method according to claim 25, wherein the second digital filter produces a difference between a first and a second result data-word stream as an output data-word stream, the first and second result data-word streams being determined from the intermediate data-word stream over a first and second time interval, the first and second time intervals being situated at a distance in time T1, the first result data-word stream being determined from a double of the intermediate data word belonging to a first instant, the intermediate data word located at the distance in time TD prior to the first instant and the intermediate data word located at the distance in time TD after the first instant being subtracted, the second result data-word stream being determined from a double of the intermediate data word belonging to the second instant, the intermediate data word located at the distance in time TD prior to the second instant and the intermediate data word located at the distance in time TD after the second instant being subtracted, the distance in time T1 being alterable to at least one of (a) being greater than the time scale TD, (b) being an integral multiple of clock-pulse period TS, and (c) not being an integral multiple of time scale TD.

30. The method according to claim 29, wherein T1 is greater than or equal to a double of TD.

31. The method according to claim 29, wherein the clock-pulse period duration TD is an integral multiple of TS.

32. The method according to claim 25, wherein the first digital filter includes three integrators or accumulators disposed directly one after another.

33. The method according to claim 25, wherein the moving average of the bit stream corresponds to the measured-value signal.

34. The method according to claim 25, wherein the clock-pulse period used in the delta-sigma modulator is applied to a clock-pulse input of the first digital filter.

35. The method according to claim 25, wherein a carrier signal generator produces a pulse-width-modulated signal, which is supplied to a rotor coil and substantially represents a sine signal.

36. A resolver system adapted to detect an angular position of a rotor in relation to a stator, the rotor bearing a rotor coil and the stator having two stator coils that are mutually shifted in a circumferential direction by 90°, the rotor coil having a carrier signal produced by a carrier signal generator applied to it, wherein each signal occurring at a respective stator coil is supplied as a respective measured-value signal to a respective processing channel, the resolver system adapted to perform the method recited in claim 26.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG. 1 shows a portion of a filter according to an example embodiment of the present invention, downstream of a delta-sigma modulator, for one respective processing channel.

[0050] FIG. 2 shows an example embodiment, in which the method is used to detect an output current of a converter, which is operated in a pulse-width modulated manner.

DETAILED DESCRIPTION

[0051] For this purpose, the analog-digital conversion according to example embodiments of the present invention is described for a resolver evaluation corresponding to 10 2005 005 024 B4. However, it is also applicable analogously to other measured-value detections.

[0052] As in FIG. 1 of DE 10 2005 005 024, stator coils mutually shifted in the circumferential direction by 90° are situated for detecting the angular position of the rotor shaft in relation to a stator. The rotor coil has a carrier signal applied to it that runs preferably in a sinusoidal manner and has a period duration T.sub.C.

[0053] A sine signal is thus induced on the first stator coil and a cosine signal is induced on the second stator coil, which are supplied to a respective processing channel.

[0054] Each processing channel comprises a delta-sigma modulator having an output that supplies a bit stream, that is, a one-bit data stream.

[0055] This one-bit data stream has the information about the measured value of the supplied signal as time average.

[0056] FIG. 1 shows a portion of a filter according to an example embodiment of the present invention, downstream of the delta-sigma modulator, for one respective processing channel.

[0057] As in the case of DE 10 2005 005 024, three integrators, which may also be called accumulators or integrating elements and are not shown in FIG. 1, and which are also included by the filter and are operated at a clock-pulse frequency f.sub.S, that is, clock-pulse period T.sub.S=1/f.sub.S, are disposed serially one after the other, so that an intermediate data-word stream is output at this serial configuration. In contrast to DE 10 2005 005 024, in which the intermediate data-word stream is supplied to the three following, again serially disposed differentiators, which, however, are operated at the much slower clock-pulse frequency f.sub.D, that is, clock-pulse period T.sub.D=1/f.sub.D, a special data-processing method is carried out in example embodiments of the present invention.

[0058] This special data processing is illustrated in FIG. 1.

[0059] For this purpose, it is important that the intermediate data-word stream be updated in the clock pulse of clock-pulse period T.sub.S, that is, in the sampling clock pulse of the delta-sigma modulator.

[0060] From this intermediate data stream, a 2nd time-discrete differential, that is, a time-discrete differential of the second order, is determined by adding a first intermediate data word at a first instant to an intermediate data word at a distance 2×T.sub.D away in time, and from the sum thus formed, subtracting the double value of the intermediate data word lying centrally in time between these two intermediate data words. Thus, a first result value is formed.

[0061] In order to form a second result value, the same operation is performed at a time interval lying at the distance in time T.sub.1 from the first intermediate data word indicated. Thus, an intermediate data word at that place has again added to it an intermediate data word at a distance 2×T.sub.D away in time, and from the sum thus formed, the double value of the intermediate data word lying centrally between these two intermediate data words is subtracted, the centrally lying intermediate data word having the distance in time T.sub.1 to the centrally lying intermediate data word utilized for calculating the first result value. Thus, a second result value is formed.

[0062] Difference D between the two result values is made available on the output side and represents the filtered measured value in digital form, a high accuracy being achievable in the process.

[0063] In contrast to DE 10 2005 005 024, neither any differentiators nor an output-side decimation filter OSR2 are necessary, since according to example embodiments of the present invention, the result on the output side is determined directly by the difference between the first and second result.

[0064] A special advantage of example embodiments of the present invention is also that T1 is an arbitrary integral multiple of T.sub.S, no further specification having to be made. Naturally, in this context, T1 is advantageously greater than the double of T.sub.D, that is, T1>T.sub.D. Since, for example, 1/T.sub.S amounts to several MHz, thus, for instance, more than 10 MHz, T1 is alterable in fine steps.

[0065] Consequently—in particular in operation—T1 is alterable at a high time resolution, and synchronizations to different clocked signal streams are therefore practicable without special effort. If, for example, the measured value of the signals of a resolver processed according to example embodiments of the present invention is supplied to control electronics of a converter, it is therefore possible in easy manner to carry out a synchronization to a clock pulse predefined by a field bus connected to the converter. To that end, only the value of T1 must thus be changed, which is practicable with the high time resolution of T.sub.S.

[0066] In further exemplary embodiments of the present invention, instead of the second time-discrete differential, a first, third or higher differential, that is, a time-discrete differential of the first, third or higher order is used, if the number of integrators, that is, accumulators, is changed correspondingly. Thus, if n integrators are provided, in order to form the first and second result value, in each case an n-tuple of intermediate data words f.sub.k set apart from one another at regular intervals at distance in time T.sub.D is used, where k runs from 0 to n−1. In this context, the differential is formed by forming the sum of

(−1).sup.k(.sub.k.sup.n−1)f.sub.k,

[0067] k running from 0 to n−1.

[0068] FIG. 2 shows, by way of example, an example embodiment, in which the method is used to detect the output current “i” of a converter, which is operated in a pulse-width modulated manner. For this purpose, the measuring duration T1 should extend over half a PWM period duration for example. Consequently, T1 may be set very precisely at the high time resolution of T.sub.S in accordance with the desired measuring duration.

[0069] In FIG. 2, the instants that are used for determining the differentials of the second order are in each case represented by a set of three small bars. Each set of three has a time length of 2×T.sub.D. However, since T.sub.D is very much greater than T.sub.S, a representation of distance in time T.sub.S is no longer possible in FIG. 2.

[0070] In addition, one measurement is to be performed in each PWM period. Consequently, T.sub.U is specified according to PWM period duration T.sub.PWM, independently of T1. This may likewise occur at the high time resolution of T.sub.S. Even if e.g. T.sub.PWM is not an integral multiple of T.sub.S, the time deviation from it when defining T.sub.U remains very low when using the method described herein.

LIST OF REFERENCE NUMERALS

[0071] T.sub.S=1/f.sub.S clock-pulse period

[0072] T.sub.D=1/f.sub.D clock-pulse period

[0073] T1 Distance in time