BLIND, BURIED, MULTI-LAYER SUBSTRATE-EMBEDDED WAVEGUIDE

Abstract

Waveguides and methods for manufacturing a waveguide that include forming a first channel in a first layer of dielectric material, the first channel comprising one or more walls; forming a second channel in a second layer of dielectric material, the second channel comprising one or more walls; depositing electrically conductive material on the one or more walls of the first channel; depositing electrically conductive material on the one or more walls of the second channel; arranging the first layer adjacent to the second layer to form a stack with the first channel axially aligned with and facing the second channel; and heating the stack so that the conductive material on the one or more walls of the first channel and the conductive material on the one or more walls of the second channel connect to form the waveguide.

Claims

1. An embedded waveguide comprising: a substrate comprising— a first outer surface, a second outer surface opposing the first outer surface, and a channel formed between the first outer surface and the second outer surface and comprising inner surfaces; conductive walls located on the inner surfaces to define a cavity, each conductive wall comprising a first end and a second end; a first solid via extending from the first outer surface to the first end of one of the conductive walls; a second solid via extending from the first outer surface to the second end of the one of the conductive walls; and a secondary material located within the cavity.

2. The embedded waveguide of claim 1, wherein the secondary material comprises ceramic material.

3. The embedded waveguide of claim 1, wherein the channel includes two opposing end walls.

4. The embedded waveguide of claim 3, wherein the conductive walls include end conductive walls located on the two opposing end walls of the channel.

5. The embedded waveguide of claim 1, wherein the channel has a hexagonal cross-sectional shape.

6. The embedded waveguide of claim 1, wherein the channel comprises a top inner surface parallel to the first outer surface.

7. The embedded waveguide of claim 6, wherein the conductive walls include a top conductive wall located on the top inner surface, and the first solid via and the second solid via are connected to the top conductive wall.

8. The embedded waveguide of claim 1, wherein the secondary material comprises a dielectric material.

9. An embedded waveguide comprising: a substrate comprising— a first outer surface, a second outer surface opposing the first outer surface, a side surface between the first outer surface and the second outer surface, and a channel formed in the side surface between the first outer surface and the second outer surface and comprising inner surfaces; conductive walls located on the inner surfaces to define a cavity, each conductive wall comprising a first end and a second end; a via extending from the first outer surface to the second end of one of the conductive walls; and a secondary material located within the cavity.

10. The embedded waveguide of claim 9, further comprising a flange located on the side surface and electrically connected to the conductive walls.

11. The embedded waveguide of claim 9, wherein the channel includes an end wall opposite to the side surface.

12. The embedded waveguide of claim 11, wherein the conductive walls include an end conductive wall located on the end wall.

13. The embedded waveguide of claim 9, wherein the channel has a hexagonal cross-sectional shape.

14. The embedded waveguide of claim 9, wherein the channel comprises a top inner surface parallel to the first outer surface.

15. The embedded waveguide of claim 14, wherein the conductive walls include a top conductive wall located on the top inner surface, and the via is connected to the top conductive wall.

16. The embedded waveguide of claim 9, wherein the secondary material comprises a dielectric material.

17. A circuit board comprising: a substrate with a first outer surface, a second outer surface opposing the first outer surface, and a channel formed between the first outer surface and the second outer surface and having inner surfaces; conductive walls located on the inner surfaces to define a cavity, each conductive wall comprising a first end and a second end; a first solid via extending from the first outer surface to the first end of one of the conductive walls; a circuit component electrically connected to the first solid via; an antenna electrically connected to the second end of one of the conductive walls; and a secondary material located within the cavity.

18. The circuit board of claim 17, further comprising a second solid via extending from the first outer surface to the second end of one of the conductive walls, wherein the antenna is electrically connected to the second end of the one of the conductive walls through the second solid via.

19. The circuit board of claim 17, wherein the substrate comprises a side surface located between the first outer surface and the second outer surface, the channel is formed in the side surface, and the antenna is located on the side surface of the substrate.

20. The circuit board of claim 17, wherein the secondary material comprises a dielectric material.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0010] Embodiments of the present invention are described in detail below with reference to the attached drawing figures, wherein:

[0011] FIG. 1 is a partial view of a circuit board implementing a waveguide constructed in accordance with an embodiment of the present invention;

[0012] FIG. 2 is a cross-sectional view of the circuit board of FIG. 1 without the waveguide;

[0013] FIG. 3A is a perspective view of the waveguide of FIG. 1;

[0014] FIG. 3B is a cross-sectional view of the circuit board with the waveguide of FIG. 3A;

[0015] FIG. 3C is a cross-sectional view of the circuit board along lines 3B with the waveguide of FIG. 3A having secondary material;

[0016] FIG. 4 is a partial view of a circuit board implementing a waveguide constructed in accordance with another embodiment of the present invention;

[0017] FIG. 5 is a perspective view of the waveguide of FIG. 4;

[0018] FIG. 6 is a flowchart illustrating steps for manufacturing a waveguide according to an embodiment of the present invention;

[0019] FIG. 7 is a perspective view of a first sheet of a waveguide constructed according to an embodiment of the present invention;

[0020] FIG. 8 is a perspective view of a second sheet of the waveguide of FIG. 7;

[0021] FIG. 9 is a perspective view of a first dielectric layer of the waveguide of FIG. 7;

[0022] FIG. 10 is a perspective view of a third sheet of the waveguide of FIG. 7;

[0023] FIG. 11 is a perspective view of a fourth sheet of the waveguide of FIG. 7;

[0024] FIG. 12 is a perspective view of a second dielectric layer of the waveguide of FIG. 7;

[0025] FIG. 13 is a perspective view the first and second dielectric layers of the waveguide of FIG. 7 having secondary material;

[0026] FIG. 14 is a perspective view of the first and second dielectric layers of the waveguide of FIG. 7 being stacked;

[0027] FIG. 15A is a perspective view of the waveguide of FIG. 7 without secondary material removed; and

[0028] FIG. 15B is a perspective view of the waveguide of FIG. 7 having remaining secondary material.

[0029] The drawing figures do not limit the present invention to the specific embodiments disclosed and described herein. The drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following detailed description of the invention references the accompanying drawings that illustrate specific embodiments in which the invention can be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments can be utilized and changes can be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. The scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0031] In this description, references to “one embodiment”, “an embodiment”, or “embodiments” mean that the feature or features being referred to are included in at least one embodiment of the technology. Separate references to “one embodiment”, “an embodiment”, or “embodiments” in this description do not necessarily refer to the same embodiment and are also not mutually exclusive unless so stated and/or except as will be readily apparent to those skilled in the art from the description. For example, a feature, structure, act, etc. described in one embodiment may also be included in other embodiments, but is not necessarily included. Thus, the present technology can include a variety of combinations and/or integrations of the embodiments described herein.

[0032] Turning to FIG. 1, an embedded waveguide 10 constructed in accordance with an embodiment of the present invention is illustrated. The waveguide 10 may be implemented in a circuit board 12 having a circuit component 14, an antenna 16, a first outer surface 18, a second outer surface 20, and a channel 22 disposed between the first outer surface 18 and the second outer surface 20. Turning to FIG. 2, the channel 22 may comprise one or more inner surfaces 24, 26, 28, 30, 32, 34. For example, the channel 22 may comprise a bottom inner surface 24 parallel with the first outer surface 18, a top inner surface 30 parallel with the second outer surface 20, a pair of first inner side surfaces 26, 28, and a pair of second inner side surfaces 32, 34. The circuit board 12 may comprise low temperature cofired ceramic, high temperature cofired ceramic, ultra-low temperature cofired ceramic, laminate printed circuit board material, or other multilayer or additively manufactured microelectronic packaging substrate material. The channel 22 may have any cross-sectional shape without departing from the scope of the present invention including but not limited to a square cross-sectional shape, a rectangular cross-sectional shape, a rounded cross-section shape, or the like. For example, as shown in FIG. 1, the channel 22 may have a hexagonal cross-sectional shape.

[0033] Turning to FIG. 3A, the waveguide 10 directs signals from the circuit component 14 to the antenna 16 through the channel 22 and broadly comprises a plurality of conductive walls 36, 38, 40, 42, 44, 46. The conductive walls 36, 38, 40, 42, 44, 46 may be made of conductive material, such as metal. The conductive walls 36, 38, 40, 42, 44, 46 are positioned on the one or more inner surfaces 24, 26, 28, 30, 32, 34 of the channel 22 to define a cavity 48 therein, as depicted in FIG. 3B. For example, one of the conductive walls 36, 38, 40, 42, 44, 46 may be a bottom wall 36 positioned on the bottom inner surface 24, one conductive wall may be a top wall 42 positioned on the top inner surface 30, some conductive walls may be first side walls 38, 40 positioned on the first pair of inner side surfaces 26, 28, and the rest of the conductive walls may be second side walls 44, 46 positioned on the second pair of inner side surfaces 32, 34. The cavity 48 may be empty, i.e., filled with air or gas of some sort. In some embodiments, the cavity 48 is filled with a dielectric material 49, as depicted in FIG. 3C. The type of dielectric material 49 may be selected for optimal tuning with the antenna 16. The cavity 48 may have any cross-sectional shape without departing from the scope of the present invention. For example, the cavity 48 may have a hexagonal cross-sectional shape.

[0034] As shown in FIG. 3A, the waveguide 10 may further comprise end walls 50, 52 connected to the conductive walls 36, 38, 40, 42, 44, 46. The end walls 50, 52 may terminate each end 54, 56 of the cavity 48 so that the waveguide 10 is enclosed. This allows the circuit component 14 and the antenna 16 to be connected to the waveguide 10 through one or more vias 58, 60. The vias 58, 60 may be solid filled or sidewall-coated vias.

[0035] An embedded waveguide 10A constructed in accordance with another embodiment of the invention is shown in FIGS. 4 and 5 and is attached to a discrete antenna 16A. The waveguide 10A may comprise substantially similar components as waveguide 10; thus, the components of waveguide 10A that correspond to similar components in waveguide 10 have an ‘A’ appended to their reference numerals.

[0036] The waveguide 10A includes all the features of waveguide 10 except that instead of having an end wall 52 terminate one of the ends 54A, the waveguide 10A comprises a conductive flange 62A. The flange 62A is connected to the parallel conductive walls 36A, 38A, 40A, 42A, 44A, 46A and is configured to connect to the discrete antenna 16A.

[0037] The flow chart of FIG. 6 depicts the steps of an exemplary method 200 of manufacturing a waveguide. In some alternative implementations, the functions noted in the various blocks may occur out of the order depicted in FIG. 6. For example, two blocks shown in succession in FIG. 6 may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order depending upon the functionality involved. In addition, some steps may be optional.

[0038] Referring to step 201, a portion of a first sheet 64 of dielectric material is metallized to form a metallized strip 66, as depicted in FIG. 7. The first sheet 64 of dielectric material may comprise low temperature cofired ceramic, high temperature cofired ceramic, ultra-low temperature cofired ceramic, laminate printed circuit board material, or other multilayer or additively manufactured microelectronic packaging substrate material. The portion of the first sheet 64 may be metallized using paste comprising conductive materials (such as copper, gold, silver, other metals, etc.), deposition of conductive materials onto the first sheet 64, or the like.

[0039] Referring to step 202, a second sheet 68 of dielectric material is laminated on the first sheet 64. The second sheet 68 may be laminated on the first sheet 64 so that the metal strip 66 is between the first sheet 64 and the second sheet 68 to form a first dielectric layer 70, as depicted in FIG. 8. The second sheet 68 may also comprise low temperature cofired ceramic, high temperature cofired ceramic, ultra-low temperature cofired ceramic, laminate printed circuit board material, or other multilayer or additively manufactured microelectronic packaging substrate material.

[0040] Referring to step 203, a portion of the second sheet 68 may be removed to expose at least a portion of the metallized strip 66. The portion of the second sheet 68 may be removed along a first axis to form a first channel 72, as depicted in FIG. 8. The channel 72 may comprise one or more side walls 74, 76 extending from the metallized strip 66. The portion of the second sheet 68 may be removed using machining, a laser, or the like.

[0041] Referring to step 204, the one or more walls 74, 76 of the first channel 72 are metallized to form one or more metallized walls 78, 80. The metallized walls 78, 80 may lie flatly on, or conform to the surfaces of, the walls 74, 76 of the first channel 72, as depicted in FIG. 9. The walls 74, 76 of the first channel 72 may be metallized using paste comprising conductive materials, deposition of conductive materials onto the walls 74, 76, or the like.

[0042] Referring to step 205, a portion of a third sheet 82 of dielectric material is metallized to form a metallized strip 84, as depicted in FIG. 10. The third sheet 82 of dielectric material may comprise low temperature cofired ceramic, high temperature cofired ceramic, ultra-low temperature cofired ceramic, laminate printed circuit board material, or other multilayer or additively manufactured microelectronic packaging substrate material. The portion of the third sheet 82 may be metallized using paste comprising conductive materials, deposition of conductive materials onto the third sheet 82, or the like.

[0043] Referring to step 206, a fourth sheet 86 of dielectric material is laminated on the third sheet 82. The fourth sheet 86 may be laminated on the third sheet 82 so that the metal strip 84 is between the third sheet 82 and the fourth sheet 86 to form a second dielectric layer 88, as depicted in FIG. 11. The fourth sheet 86 may also comprise low temperature cofired ceramic, high temperature cofired ceramic, ultra-low temperature cofired ceramic, laminate printed circuit board material, or other multilayer or additively manufactured microelectronic packaging substrate material.

[0044] Referring to step 207, a portion of the fourth sheet 86 may be removed to expose at least a portion of the metallized strip 84. The portion of the fourth sheet 86 may be removed along a second axis to form a second channel 90, as depicted in FIG. 11. The channel 90 may comprise one or more side walls 92, 94 extending from the metallized strip 84. The portion of the fourth sheet 86 may be removed using machining, a laser, or the like.

[0045] Referring to step 208, the one or more walls 92, 94 of the second channel 90 are metallized to form one or more metallized walls 96, 98. The metallized walls 96, 98 may lie flatly on, or conform to the surfaces of, the walls 92, 94 of the second channel 90, as depicted in FIG. 12. The walls 92, 94 of the second channel 90 may be metallized using paste comprising conductive materials, deposition of conductive materials onto the walls 92, 94, or the like.

[0046] Referring to step 209, a secondary material 100 may be deposited in the first channel 72 and the second channel 90, as depicted in FIG. 13. The secondary material 100 may comprise fugative material operable to burn off or vaporize when subject to sufficient heat, such as a carbon-based paste or tape material. In some embodiments, such as when the dielectric layers 70, 88 comprise fiber glass or other non-ceramic materials, the secondary material 100 may comprise a fugative material that is removable via acid. In some embodiments, the secondary material 100 may comprise material having predetermined dielectric properties. For example, the secondary material 100 may comprise a dielectric having predetermined dielectric properties for tuning and/or matching an antenna to be attached to the waveguide.

[0047] Referring to step 210, the first dielectric layer 70 is positioned adjacent to the second dielectric layer 88. The layers 70, 88 may be positioned with their respective channels 72, 90 facing one another so that their respective axes are parallel to form a stack 102, as shown in FIG. 14.

[0048] Referring to step 211, the stack 102 is heated, or sintered/cofired, so that the metallized strips 66, 84 and walls 78, 80, 96, 98 bond to form a waveguide 104. In some embodiments, the secondary material 100 burns off to leave an empty cavity 106, as depicted in FIG. 15A. In some embodiments, the secondary material 100 is a dielectric material and remains in the cavity 106, as depicted in FIG. 15B.

[0049] The method 200 may include additional, less, or alternate steps and/or device(s), including those discussed elsewhere herein. For example, the method 200 may include a step of adding end walls to the waveguide, as depicted in FIG. 3A. Alternatively or additionally, the method 200 may include a step of adding a flange to an end of the waveguide, as depicted in FIG. 5. One or more holes may also be bored in the dielectric layers and filled with conductive material to form vias. Sidewalls of the one or more holes may be coated to form sidewall coated vias.

[0050] Although the invention has been described with reference to the embodiments illustrated in the attached drawing figures, it is noted that equivalents may be employed and substitutions made herein without departing from the scope of the invention as recited in the claims.