Chip Resistor

Abstract

To provide a chip resistor in which a resistive element can be surely protected from an external environment and which is also excellent in corrosion resistance, a chip resistor 1 is configured to include an insulating substrate 2, a pair of front electrode 3 provided on opposite end portions of a front surface of the insulating substrate 2, a pair of back electrodes 7 provided on opposite end portions of a back surface of the insulating substrate 2, a resistive element 4 provided to extend onto the two front electrodes 3, a first insulating layer 5 covering the resistive element 4, a second insulating layer 6 made of a resin material to cover the first insulating layer 5, end surface electrodes 8 establishing electrical continuity between the front electrodes 3 and the back electrodes 7, plating layers 9 covering the end surface electrodes 8, etc. Rough surface portions 6a made rougher in surface roughness than any other portion of the second insulating layer 6 are formed at opposite end portions of the second insulating layer 6. End portions of the end surface electrodes 8 and the plating layers 9 are brought into tight contact with the rough surface portions 6a respectively.

Claims

1. A chip resistor comprising: a cuboid-shaped insulating substrate; a pair of front electrodes which are provided on opposite end portions of a front surface of the insulating substrate; a pair of back electrodes which are provided on opposite end portions of a back surface of the insulating substrate; a resistive element which is provided to extend onto the pair of front electrodes; a first insulating layer which is made of a glass material to cover the resistive element; a second insulating layer which is made of a resin material to cover portions of the front electrodes and the first insulating layer; end surface electrodes which are provided to establish electrical continuity between the front electrodes and the back electrodes and which extend beyond boundary positions between the front electrodes and the second insulating layer and up to end portions of the second insulating layer; and plating layers which are provided to cover the end surface electrodes and which extend beyond boundary positions between the end surface electrodes and the second insulating layer and up to the end portions of the second insulating layer, a trimming groove being formed in the resistive element and the first insulating layer so that a resistive value of the chip resistor can be adjusted; wherein: rough surface portions made rougher in surface roughness than any other portion of the second insulating layer are provided at opposite end portions of the second insulating layer positioned on outer sides of the trimming groove; and end portions of the end surface electrodes and the plating layers are in tight contact with the rough surface portions respectively.

2. A chip resistor according to claim 1, wherein: the rough surface portions are formed by blast treatment applied to the second insulating layer.

3. A chip resistor according to claim 1, wherein: auxiliary insulating layers made rougher in surface roughness than the second insulating layer are provided on the opposite end portions of the second insulating layer, and the rough surface portions are formed by the auxiliary insulating layers.

4. A chip resistor according to claim 3, wherein: a resin material of the auxiliary insulating layers contains the same material as a material used for the end surface electrodes.

5. A chip resistor according to claim 4, wherein: the plating layers are formed of the same material as the material contained in the end surface electrodes and the auxiliary insulating layers.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 A sectional view of a chip resistor according to a first embodiment of the invention.

[0017] FIG. 2 Sectional views showing production steps of the chip resistor.

[0018] FIG. 3 Sectional views showing production steps of the chip resistor.

[0019] FIG. 4 A sectional view of a chip resistor according to a second embodiment of the invention.

[0020] FIG. 5 Sectional views showing production steps of the chip resistor.

DESCRIPTION OF EMBODIMENTS

[0021] Embodiments of the invention will be described below with reference to the drawings. As shown in FIG. 1, a chip resistor 1 according to a first embodiment of the invention is mainly constituted by a cuboid-shaped insulating substrate 2, a pair of front electrodes 3, a resistive element 4, a first insulating layer 5, a second insulating layer 6, a pair of back electrodes 7, a pair of end surface electrodes 8, plating layers 9, etc. The pair of front electrodes 3 are provided on longitudinally opposite end portions in an upper surface of the insulating substrate 2. The resistive element 4 shaped like a rectangle is provided to extend onto the front electrodes 3. The first insulating layer 5 covers the resistive element 4. The second insulating layer 6 covers the first insulating layer 5. The pair of back electrodes 7 are provided on longitudinally opposite end portions in a lower surface of the insulating substrate 2. The pair of end surface electrodes 8 are provided on side surfaces of the insulating substrate 2 to establish electrical continuity between the front electrodes 3 and the back electrodes 7 correspondingly and respectively. The plating layers 9 cover the end surface electrodes 8. A trimming groove 10 is formed in the resistive element 4 and the first insulating layer 5. A resistance value of the resistive element 4 is adjusted by the trimming groove 10.

[0022] The insulating substrate 2 is made of ceramics etc. When a large-sized aggregate substrate which will be described later is divided along primary division grooves and secondary division grooves which extend vertically and horizontally, a number of the insulating substrates 2 can be obtained.

[0023] The front electrodes 3 are obtained by screen-printing, drying and sintering an Ag (silver)-based paste material containing 1 to 5 wt % Pd (palladium).

[0024] The resistive element 4 is obtained by screen-printing, drying and sintering a resistive paste of ruthenium oxide etc. Longitudinally opposite end portions of the resistive element 4 overlap with the front electrodes 3.

[0025] The first insulating layer 5 and the second insulating layer 6 form a protective layer having a two-layer structure. Of the protective layer, the first insulating layer 5 is an undercoat layer which covers the resistive element 4 before the trimming groove 10 is formed, and the second insulating layer 6 is an overcoat layer which covers the first insulating layer 5 after the trimming groove 10 is formed. Incidentally, the trimming groove 10 is a slit which is formed into an L-shape, a linear shape or the like by irradiation of laser light. The slit is formed within a region of the resistive element 4 interposed between the pair of front electrodes 3.

[0026] The first insulating layer 5 is obtained by screen-printing, drying and sintering a glass paste. The first insulating layer 5 covers an upper surface of the resistive element 4 and overlaps with end portions of the front electrodes 3.

[0027] The second insulating layer 6 is obtained by screen-printing and thermally curing (baking) an epoxy resin paste or an epoxy resin-based paste containing polyimide, which is excellent in humidity resistance. The second insulating layer 6 covers the first insulating layer 5 and overlaps with the end portions of the front electrodes 3. Opposite end portions of the second insulating layer 6 serve as rough surface portions 6a. The rough surface portions 6a are set to be rougher in surface roughness than any other portion of the second insulating layer 6. That is, the portion of the second insulating layer 6 excluding the rough surface portions 6a has smooth surface roughness with no void or air hole. Call the portion a smooth surface portion 6a. Ra (arithmetic average roughness) of each of the rough surface portions 6a is set to be 1.5 times or more as high as that of the smooth surface portion 6a. Incidentally, as will be described later in detail, the rough surface portion 6a is formed by shot blast such as sand blast applied to a front surface of the second insulating layer 6.

[0028] The back electrodes 7 are obtained by screen-printing, drying and sintering an Ag paste or an Ag—Pd paste containing a small amount of Pd.

[0029] The end surface electrodes 8 are formed by sputtering nickel (Ni)/chromium (Cr) etc. Most parts of the front electrodes 3 and the back electrodes 7 positioned outside the second insulating layer 6 are covered with the end surface electrodes 8. The end surface electrodes 8 extend beyond boundary portions between the front electrodes 3 and the second insulating layer 6 and up to the rough surface portions 6a. Most parts of the rough surface portions 6a excluding their upper portion sides are in tight contact with end portions of the end surface electrodes 8.

[0030] The plating layers are made of Ni plating, Sn plating, etc. The plating layers 9 cover the end surface electrodes 8, the front electrodes 3 and the back electrodes 7.

[0031] Next, a method for producing the chip resistor 1 configured as described above will be described with reference to FIG. 2 and FIGS. 3.

[0032] First, an aggregate substrate 2A in which primary division grooves and secondary division grooves extending in a latticed pattern have been formed is prepared. Front and back surfaces of the aggregate substrate 2A are sectioned into a number of chip formation regions by the primary division grooves and the secondary division grooves. Each of the chip formation regions serves as an insulating substrate 2 corresponding to one chip resistor. Although one chip formation region is representatively shown in FIG. 2 and FIGS. 3, a number of such chip formation regions are actually arrayed in the latticed pattern.

[0033] An Ag paste is screen-printed on the back surface of the aggregate substrate 2A, and then dried. Thus, as shown in FIG. 2(a), a pair of back electrodes 7 facing each other with a predetermined interval therebetween are formed on longitudinally opposite end portions of each chip formation region.

[0034] Next, an Ag—Pd paste is screen-printed on the front surface of the aggregate substrate 2A, and then dried. Thus, as shown in FIG. 2(b), a pair of front electrodes 3 facing each other with a predetermined interval therebetween are formed on longitudinally opposite end portions of each chip formation region. Then, the front electrodes 3 and the back electrodes 7 are sintered simultaneously at a high temperature of about 850° C. Incidentally, the front electrodes 3 and the back electrodes 7 may be sintered separately, or a formation sequence of the front electrodes 3 and the back electrodes 7 may be reversed so as to form the front electrodes 3 prior to the back electrodes 7.

[0035] Next, a resistive paste containing ruthenium oxide etc. is screen-printed on the front surface of the aggregate substrate 2A, and then dried. Thus, a resistive element 4 whose end portions are superimposed on the front electrodes 3 is formed as shown in FIG. 2(c), and then sintered at a high temperature of about 850° C.

[0036] Next, a glass paste is screen-printed on a region covering the resistive element 4, and then dried. Thus, a first insulating layer 5 covering the resistive element 4 and end portions of the front electrodes 3 is formed as shown in FIG. 2(d), and then sintered at a temperature of about 600° C.

[0037] Next, laser light is applied to the resistive element 4 through the first insulating layer 5 while probes not shown are brought into contact with the pair of auxiliary electrodes 5 respectively to measure a resistance value of the resistive element 4. Thus, as a shown in FIG. 2(e), a trimming groove 10 is formed in the first insulating layer 5 and the resistive element 4 to adjust the resistance value of the resistive element 4.

[0038] Next, an epoxy-polyimide resin paste is screen-printed to cover the first insulating layer 5, and then thermally cured (baked) at a temperature of about 200° C. Thus, as shown in FIG. 2(f), a second insulating layer 6 covering the entire first insulating layer 5, the trimming groove 10 formed in the resistive element 4, and the end portions of the front electrodes 3 is formed.

[0039] Next, a masking paste which can be washed away by water etc. is screen-printed on a front surface of the second insulating layer 6, and then dried. Thus, as shown in FIG. 3(a), a masking 11 is formed on the second insulating layer 6 excluding its opposite end portions, that is, a portion covering the trimming groove 10.

[0040] Next, as shown in FIG. 3(b), an abrasive is sprayed by compressed air to apply shot blast to the second insulating layer 6 so as to roughen the front surface of the second insulating layer 6 which is not covered with the masking 11. Then, the masking 11 is cleaned and removed, as shown in FIG. 3 (c). Thus, rough surface portions 6a whose surface have been roughened are formed at opposite end portions of the second insulating layer 6. An upper surface of the second insulating layer 6 which had been covered with the masking 11 becomes a smooth surface portion 6b which is smooth with a dense structure.

[0041] The steps performed so far are batch processing on the aggregate substrate 2A. In a next step, the aggregate substrate 2A is primarily divided into strips along the primary division grooves, so as to obtain strip-shaped substrates 2B each having a width in the longitudinal direction of the chip formation region.

[0042] Ni/Cr is sputtered on divided surfaces of each of the strip-shaped substrates 2B. Thus, as shown in FIG. 3(d), a pair of end surface electrodes 8 establishing electrical continuity between the front electrodes 3 and the back electrodes 7 are formed. On this occasion, the end surface electrodes 8 are formed to extend beyond boundary portions between the front electrodes 3 and the second insulating layer 6 and up to the rough surface portions 6a of the second insulating layer 6. However, the front surfaces of the rough surface portions 6a which have been subjected to blast treatment have uneven surface roughness. Accordingly, tight contact properties between the end surface electrodes 8 and the rough surface portions 6a can be enhanced although the resin material excellent in humidity resistance is used to form the second insulating layer 6.

[0043] Next, the strip-shaped substrate 2B is secondarily divided along the secondary division grooves, so as to obtain single chips (individual pieces) each having an equal size to the chip resistor 1. Then, Ni plating and Sn plating are sequentially applied to the entire end surface electrodes 8 and portions of the back electrodes 7 in each single chip. Thus, as shown in FIG. 3(e), plating layers 9 having a layered structure to cover the end surface electrodes 8 and the back electrodes 7 are formed. Consequently, the chip resistor 1 is completed.

[0044] As described above, in the chip resistor 1 according to the embodiment, the front surface of the second insulating layer 6 covering the portion where the trimming groove 10 is present serves as the smooth surface portion 6b having dense surface roughness. Accordingly, humidity resistance can be secured so that the resistive element 4 can be surely protected from an external environment. In addition, the opposite end portions of the second insulating layer 6 covering the portions from which the trimming groove 10 is absent serve as the rough surface portions 6a whose surfaces have been roughened. The end portions of the end surface electrodes 8 and the plating layers 9 which cover the front electrodes 3 extend up to the rough surface portions 6a. Accordingly, tight contact properties of the end surface electrodes 8 and the plating layers 9 with the second insulating layer 6 are so excellent that corrosion resistance of the front electrodes 3 can be surely prevented from being spoiled although the resin material excellent in humidity resistance is used to form the second insulating layer 6.

[0045] FIG. 4 is a sectional view of a chip resistor 20 according to a second embodiment of the invention. Portions corresponding to those in FIG. 1 are referred to by the same signs respectively.

[0046] The chip resistor 20 according to the second embodiment is different from the chip resistor 1 according to the first embodiment in a point that auxiliary insulating layers 21 are provided on opposite end portions of a second insulating layer 6 and the auxiliary insulating layers 21 are formed as rough surface portions. The remaining configuration of the chip resistor 20 according to the second embodiment is basically the same as that of the chip resistor 1 according to the first embodiment.

[0047] That is, as shown in FIG. 4, the second insulating layer 6 is obtained by screen-printing and thermally curing an epoxy resin paste or an epoxy resin-based paste containing polyimide, which is excellent in humidity resistance. The second insulating layer 6 covers a first insulating layer 5 and overlaps with end portions of front electrodes 3. The auxiliary insulating layers 21 are provided on the opposite end portions of the second insulating layer 6. Surface roughness Ra of the auxiliary insulating layers 21 is set to be 1.5 times or more as high as that of the second insulating layer 6. The auxiliary insulating layers 21 are obtained by screen-printing and thermally curing an epoxy resin paste rougher in surface roughness than the second insulating layer 6, or an epoxy resin paste added with electrically conductive particles of Ni, Cu, etc. whose amount is so small that the auxiliary insulating layers 21 are not electrically conductive.

[0048] End surface electrodes 8 are formed by sputtering Ni/Cu etc. The end surface electrodes 8 extend beyond the front electrodes 3 and up to the middle of the auxiliary insulating layers 21. Here, as long as the additive contained in the resin material of the auxiliary insulating layers 21 is the same as the material used for the end surface electrodes 8, for example, as long as the resin material of the auxiliary insulating layers 21 contains at least one of Ni and Cu when the end surface electrodes 8 are formed by sputtering Ni/Cr, tight contact properties between the end surface electrodes 8 and the auxiliary insulating layers 21 can be extremely excellent.

[0049] Plating layers 9 are made of Ni plating, Sn plating, etc. deposited on the end surface electrodes 8 and portions of back electrodes 7. End portions of the plating layers 9 extend beyond the end surface electrodes 8 and up to the auxiliary insulating layers 21. Here, as long as the plating layers 9 are formed of the same material as the material contained in the end surface electrodes 8 and the auxiliary insulating layers 21, for example, as long as at least Ni plating is applied to form the plating layers 9 when Ni is contained in both the end surface electrodes 8 and the auxiliary insulating layers 21, not only can tight contact properties between the end surface electrodes 8 and the auxiliary insulating layers 21 be enhanced but tight contact properties between the plating layers 9 and the auxiliary insulating layers 21 can be also extremely excellent.

[0050] Next, a method for producing the chip resistor 20 configured as described above will be described with reference to FIG. 5. Incidentally, in the method for producing the chip resistor 20, steps up to formation of a second insulating layer 6 shown in FIGS. 2 (a) to 2(f) are the same as those in the first embodiment. FIG. 5 show steps following that.

[0051] That is, in the method for producing the chip resistor 20 according to the second embodiment, an epoxy resin paste containing a small amount of Ni is screen-printed and thermally cured (baked) at a temperature of about 200° C. in place of shot blast applied to opposite end portions of the second insulating layer 6. Thus, as shown in FIG. 5(a), auxiliary insulating layers (rough surface portions) 21 which are made rougher in surface roughness than the second insulating layer 6 are formed on the opposite end portions of the second insulating layer 6.

[0052] Next, an aggregate substrate 2A is primarily divided so as to obtain strip-shaped substrates 2B. Then, Ni/Cr is sputtered on divided surfaces of each of the strip-shaped substrates 2B. Thus, as shown in FIG. 5(b), a pair of end surface electrodes 8 establishing electrical continuity between front electrodes 3 and back electrodes 7 are formed. On this occasion, the end surface electrodes 8 are formed to extend beyond the front electrodes 3 and up to the auxiliary insulating layers 21. However, the auxiliary insulating layers 21 serve as rough surface portions which are rough in surface roughness. Accordingly, tight contact properties between the end surface electrodes 8 and the auxiliary insulating layers 21 can be enhanced although the resin material excellent in humidity resistance is used to form the second insulating layer 6.

[0053] Next, the strip-shaped substrate 2B is secondarily divided so as to obtain single chips. Then, Ni plating and Sn plating are sequentially applied to the entire end surface electrodes 8 and portions of the back electrodes 7 in each single chip. Thus, as shown in FIG. 5(c), plating layers 9 having a layered structure to cover the end surface electrodes 8 and the back electrodes 7 are formed. Consequently, the chip resistor 20 is completed.

[0054] As described above, in the chip resistor 20 according to the embodiment, the auxiliary insulating layers 21 made rougher in surface roughness than the second insulating layer 6 are provided on the opposite end portions of the second insulating layer 6, and end portions of the end surface electrodes 8 and the plating layers 9 are brought into tight contact with the auxiliary insulating layers 21. Accordingly, tight contact properties of the end surface electrodes 8 and the plating layers 9 with the auxiliary insulating layers 21 are so excellent that corrosion resistance of the front electrodes 3 can be surely prevented from being spoiled although the resin material excellent in humidity resistance is used to form the second insulating layer 6.

[0055] In addition, the auxiliary insulating layers 21 which serve as the rough surface portions can be formed by printing. In addition, since the resin material of the auxiliary insulating layers 21 contains the same material as the material (e.g. Ni) used for the end surface electrodes 8, tight contact properties between the end surface electrodes 8 and the auxiliary insulating layers 21 can be made extremely excellent. Further, since the plating layers 9 are formed of the same material as the material (e.g. Ni) contained in the end surface electrodes 8 and the auxiliary insulating layers 21, not only can tight contact properties between the end surface electrodes 8 and the auxiliary insulating layers 21 be improved, but tight contact properties between the plating layers 9 and the auxiliary insulating layers 21 can be also made extremely excellent.

REFERENCE SIGNS LIST

[0056] 1, 20 chip resistor [0057] 2 insulating substrate [0058] 2A aggregate substrate [0059] 2B strip-shaped substrate [0060] 3 front electrode [0061] 4 resistive element [0062] 5 first insulating layer [0063] 6 second insulating layer [0064] 6a rough surface portion [0065] 6b smooth surface portion [0066] 7 back electrode [0067] 8 end surface electrode [0068] 9 plating layer [0069] 10 trimming groove [0070] 11 masking [0071] 21 auxiliary insulating layer (rough surface portion)