PROCESS FOR FABRICATING RESISTIVE MEMORY CELLS

Abstract

A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

Claims

1.-8. (canceled)

9. A method, comprising: forming a plurality of memory cells including: forming a first conductive layer on a substrate; forming a first plurality of conductive bands on the substrate from the first conductive layer, the first plurality of conductive bands extending in a first direction, the forming the first plurality of conductive bands including etching a first portion of the first conductive layer; forming a dielectric layer on and between each one of the first plurality of conductive bands; forming a second conductive layer on the dielectric layer; and forming a second plurality of conductive bands on the dielectric layer, the second plurality of conductive bands extending in a second direction, the second direction different than the first direction, the forming the second plurality of conductive bands including etching the second conductive layer, the dielectric layer, and a second portion of the first conductive layer.

10. The method of claim 9 wherein the second direction is orthogonal to the first direction.

11. The method of claim 9 wherein forming a plurality of memory cells includes forming a first electrode in the first conductive layer and forming a second electrode in the second conductive layer.

12. The method of claim 11 wherein forming the first plurality of conductive bands includes forming the first plurality of conductive bands with a first pitch and wherein forming the second plurality of conductive bands includes forming the second plurality of conductive bands with a second pitch substantially equal to the first pitch.

13. The method of claim 11 further comprising: forming a plurality of word lines, each one of the plurality of word lines extending in the first direction; and forming a plurality of bit lines, each one of the plurality of bit lines extending in the second direction.

14. The method of claim 9 wherein forming the first plurality of conductive bands includes depositing a first photoresist and patterning the first photoresist corresponding to the first plurality of conductive bands and wherein forming the second plurality of conductive bands includes depositing a second photoresist and patterning the second photoresist corresponding to the second plurality of conductive bands.

15. A method, comprising: forming a plurality of memory cells including: forming a first plurality of trenches in a first conductive layer, each one of the first plurality of trenches extending in a first direction forming a dielectric layer on the first conductive layer and in the first plurality of trenches; forming a second conductive layer on the dielectric layer; and forming a second plurality of trenches in the second conductive layer, the dielectric layer, and the first conductive layer, each one of the second plurality of trenches extending in a second direction different from the first direction.

16. The method of claim 15 wherein forming a plurality of memory cells includes forming a first electrode in the first conductive layer and forming a second electrode in the second conductive layer.

17. The method of claim 15 wherein the second direction is orthogonal to the first direction.

18. The method of claim 16 wherein a width of each one of the first plurality of trenches substantially equals a width of each one of the second plurality of trenches.

19. The method of claim 16 further comprising: coupling one of a plurality of word lines to the first electrode; and coupling one of a plurality of bit lines to the second electrode.

20. The method of claim 16 wherein forming the first plurality of trenches includes depositing a photoresist and patterning the photoresist using photolithography.

21. An integrated circuit comprising: a memory device having a first memory cell and a second memory cell, the memory device including: a first conductive layer including a first electrode pad and a second electrode pad separated from the first electrode pad, the first and second electrode pads each having a a first side on a substrate, the first sides of the each first and second electrode pads each being rectangular; a band covering the first and second electrode pads, the band including a dielectric layer and a second conductive layer on the first and second electrodes, the second conductive layer being a third electrode, the first memory cell including the first electrode, the dielectric layer, and the third electrode, and the second memory cell including the second electrode, the dielectric layer, and the third electrode.

22. The integrated circuit of claim 21 wherein the first and second memory cells define a memory plane within an interconnect portion of the integrated circuit, the memory plane including memory cells extending in orthogonal first and second directions.

23. The integrated circuit of claim 21 wherein the band covers the first and second electrode pads in the first direction.

24. The integrated circuit of claim 22 further comprising: word lines traversing the memory plane in the first direction; bit lines traversing the memory plane in the second direction; first electrically conductive contacts connecting the word lines to the first and second electrodes; and a second electrically conductive contact connecting one of the bit lines to the third electrode.

25. The method of claim 9 wherein the first conductive layer is formed on a surface of the substrate, the etching through a first portion of the first conductive layer including etching to the surface of the substrate, and the etching through a portion of the second conductive layer, a portion of the dielectric layer, and a second portion of the first conductive layer including etching to the surface of the substrate.

26. The method of claim 16 wherein the each one of the first electrodes is a distinct electrode and each one of the second electrodes is shared across multiple cells of the plurality of memory cells.

27. The device of claim 21 wherein the dielectric layer has a first side and a second side opposite the first side, the dielectric layer having a first thickness measured between the first and second sides of the dielectric layer at the first electrode pad and a second thickness measured between the first and second sides of the dielectric layer at a portion of the dielectric layer between the first and second electrodes.

28. The device of claim 27 wherein the second conductive layer has a first side and a second side opposite the first side, the second conductive layer having a first thickness measured between the first and second sides of the second conductive layer at the first electrode pad and a second thickness measured between the first and second sides of the second conductive layer at the portion of the dielectric layer between the first and second electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other advantages and features will become apparent upon examining in detail completely nonlimiting embodiments and methods of implementation, and the appended drawings, in which:

[0023] FIG. 1 illustrates a resist mask used in conventional processes for forming resistive memory;

[0024] FIGS. 2, 4, 6 and 7 show cross-sectional views X and Y of structures obtained in various steps for forming an RRAM resistive-memory memory plane in accordance with an example embodiment, in planes parallel to a first direction X and to a second direction Y that are, for example, respectively longitudinal and traverse (the directions X, Y for example respectively correspond to the future rows and columns of the memory plane PM); and

[0025] FIGS. 3 and 5 are top views of the resist masks deposited on a memory plane during RRAM resistive-memory formation in accordance with the example embodiment, in which the first and second directions X and Y have been shown.

DETAILED DESCRIPTION

[0026] The cross-sectional views X and Y in FIG. 2 show an example BEOL interconnect structure including a metallization level Mi from which capacitive memory cells of the memory plane will be formed.

[0027] The BEOL interconnect portion is generally formed above an electronic circuit fabricated in and on a semiconductor substrate and includes a plurality of successive metallization levels. The resistive memory cells are, for example, formed between two metallization levels Mi and Mi+1. The metallization level Mi is shown very schematically and includes metal tracks forming word lines WL extending in the first direction X.

[0028] In an initial step, first electrically conductive contacts CWL, which may be formed in a conventional way, are connected to the word lines and have been formed in a dielectric layer OX deposited above the metallization level Mi. The surface S of the dielectric OX typically includes the contacts CWL which are planarized, such as by wet chemical-mechanical planarization, for example.

[0029] In in accordance with an example process for forming a RRAM resistive-memory memory plane, a first conductive layer CC1 (which will eventually serve to form the first electrodes BE of the MOM capacitive structures) is deposited on the surface S. The first electrodes BE are the lower electrodes of the MOM capacitive structure, i.e., the electrodes closest the substrate of the integrated circuit. The metal used to form the bottom electrodes BE may be chosen from titanium Ti, titanium nitride TiN, or a noble metal such as platinum Pt or iridium Ir, for example.

[0030] In a following step, a layer of photoresist is deposited on the first layer CC1 and subjected to a conventional photolithography and etching phase to form longitudinal bands of resist RX. FIG. 3 shows the bands of resist RX extending parallel to the direction X and distributed periodically in a direction perpendicular to the direction X. The bands of resist, which are of the same width as one another, are repeated with a regular pitch and are placed facing contacts CWL.

[0031] Next, the exposed portion of the first conductive layer CC1 is etched selectively relative to the resist RX and as far as the surface of the dielectric OX to obtain, after removal of the resist, bands BDX extending in the first direction X of the future memory plane (FIG. 4). During this step, no problem with resist adhesion is encountered. More specifically, the resist pattern takes the form of bands having a contact area which is larger than for a pattern made up of pads, and does not include corners that risk being rounded. The resist is then selectively removed to clear the structure obtained for implementing the subsequent steps of the process.

[0032] FIG. 4 shows a subsequent step of the process, in which a dielectric layer MOX and then a second conductive layer CC2 are deposited. The second conductive layer CC2 will eventually include the second electrodes TE of the capacitive cells CEL, and may also be formed from Ti, TiN or Pt. The second electrodes TE are the upper electrodes of the capacitive cells CEL, i.e., the electrodes furthest from the substrate. The dielectric layer MOX is advantageously a metal oxide, e.g., including titanium oxide TiO.sub.x or hafnium dioxide HfO.sub.2.

[0033] In a following step of the process, a photoresist layer is once again deposited and subjected to a photolithography and etching phase to form transverse bands of resist RY perpendicular to the longitudinal bands RX obtained beforehand. FIG. 5 shows the bands of resist RY on the surface of the structure, including a stack of the dielectric layer MOX and the second conductive layer CC2 on the first conductive layer CC1 and on the surface S of the dielectric layer OX.

[0034] The bands of resist RY extend parallel to the axis Y and are periodically distributed in the direction X. The bands of resist RY are also of the same width as one another, repeated with a regular pitch and placed facing contacts CWL.

[0035] In a next step, the results of which are shown in FIG. 6, the second conductive layer CC2, the dielectric layer MOX and the first conductive layer CC1 are etched in succession and selectively relative to the resist as far as the surface S of the oxide layer OX. Thus, the etching of the first conductive layer CC1 through two perpendicular masks RX, RY results in first electrodes BE of square or rectangular shape, without rounding of the corners.

[0036] The dielectric layer MOX and the second conductive layer CC2 have a configuration in bands BDY, corresponding to the pattern of the mask RY, and form chevron-like shapes the teeth of which facing the first electrodes BE form the second electrodes (or upper electrodes) TE of the memory cells.

[0037] As described below with reference to FIG. 7, the second electrodes TE of the memory cells belonging to a given column will eventually be connected together by a bit line. The aspect ratio of the MOM capacitive cells is thus mainly defined by the shape of the pads forming the first electrodes BE. Since the pads are obtained by etching perpendicular bands, this process allows such an aspect ratio to be preserved for small dimensions.

[0038] As FIG. 7 shows, bit lines BL extending in the transverse direction Y are formed in a conventional way, forming the columns of the memory plane PM. The bit lines are connected to each top electrode TE of a column of the memory plane PM by second contacts CBL.

[0039] The bit lines BL may, for example, be produced in the upper metallization level Mi+1. The second contacts CBL are thus produced between the metallization level Mi+1 and the second electrodes of the capacitive cells CEL. For the sake of clarity, no layer of insulating material, customarily placed between the capacitive structures CEL and between the contacts CBL, has been shown.

[0040] Thus, a memory plane including conductive pads of a square or rectangle shape forming the first electrodes BE has been obtained. A stack of a dielectric layer MOX and a second conductive layer covers the pads BE in the first direction X and forms in the second direction Y conductive bands BDY extending over the pads and between the pads. The second electrodes TE are thus formed by zones of the second bands BDY, vertically facing the pads. Of course, the memory device may also include conventional selection transistors for selecting memory cells, which are not shown here for the sake of simplicity.

[0041] The methods of implementation and embodiments of the invention are not limited to the present description but include other embodiments. For example, a process for producing a memory plane has been detailed, but the invention may also be applied to the production of a single isolated memory cell. Those skilled in the art will be able to adapt the teachings of the present description to implement such an embodiment.