SWITCHING REGULATOR WITH IMPROVED EFFICIENCY AND METHOD THEREOF

Abstract

A switching regulator with constant on time control adopts a timer to time when the system is in discontinuous current mode (DCM). If the DCM lasted for a set time, a power stage in the switching regulator is controlled to be ON for a minimum on time duration, so as to ensure the switching regulator enters sleep mode.

Claims

1. A switching regulator, comprising: a power stage, operable to convert an input voltage into an output voltage; a DCM detector, configured to generate a detect signal in response to a current flowing through the power stage; a timer, operable to start to time if the detect signal indicates the switching regulator is in discontinuous current mode, and to generate a timeout signal when timing out; a minimum on time circuit, configured to generate a minimum on time signal in response to the timeout signal; and a logic & drive circuit, configured to generate a drive signal in response to the timeout signal and the minimum on time signal, to control the operation of the power stage.

2. The switching regulator of claim 1, wherein the power stage is controlled to be ON for a minimum on time duration when the switching regulator is in discontinuous current mode.

3. The switching regulator of claim 1, further comprising: an error amplifier, configured to generate an error amplified signal in response to a voltage reference and a feedback signal indicative of the output voltage; a voltage comparator, configured to generate a comparison signal by comparing the error amplified signal with a ramp signal; and a sleep comparator, configured to generate a sleep signal by comparing the error amplified signal with a sleep reference, the sleep signal being operable to indicate whether the switching regulator enters sleep mode.

4. The switching regulator of claim 3, wherein the logic & drive circuit comprises: a logical OR circuit, configured to generate a set signal by executing OR operation on the comparison signal and the timeout signal; and a RS flip-flop, configured to generate the drive signal in response to the set signal and the minimum on time signal.

5. The switching regulator of claim 1, further comprising: a constant on time circuit, configured to receive the input voltage and the output voltage, to generate a constant on time signal to the logic & drive circuit, to control the operation of the power stage.

6. The switching regulator of claim 1, further comprising: a voltage comparator, configured to generate a comparison signal by comparing a sum of a feedback signal and a ramp signal with a voltage reference, the feedback signal being indicative of the output voltage; and a sleep comparator, configured to generate a sleep signal by comparing the feedback signal with a sleep reference.

7. The switching regulator of claim 6, wherein the logic & drive circuit comprises: a logical OR circuit, configured to generate a set signal by executing OR operation on the comparison signal and the timeout signal; and a RS flip-flop, configured to generate the drive signal in response to the set signal and the minimum on time signal.

8. A control circuit used in a switching regulator, the switching regulator including a power stage configured to convert an input voltage to an output voltage, the control circuit comprising: a DCM detector, configured to generate a detect signal in response to a current flowing through the power stage; a timer, operable to start to time if the detect signal indicates the switching regulator is in discontinuous current mode, and to generate a timeout signal when timing out; a minimum on time circuit, configured to generate a minimum on time signal in response to the timeout signal; and a logic & drive circuit, configured to generate a drive signal in response to the timeout signal and the minimum on time signal, to control the operation of the power stage.

9. The control circuit of claim 8, wherein the logic & drive circuit is configured to turn on the power stage in response to the timeout signal, and is configured to turn off the power stage in response to the minimum on time signal after the power stage has been ON for a minimum on time duration.

10. The control circuit of claim 8, further comprising: an error amplifier, configured to generate an error amplified signal in response to a voltage reference and a feedback signal indicative of the output voltage; a voltage comparator, configured to generate a comparison signal by comparing the error amplified signal with a ramp signal; and a sleep comparator, configured to generate a sleep signal by comparing the error amplified signal with a sleep reference, the sleep signal being operable to indicate whether the switching regulator enters sleep mode.

11. The control circuit of claim 10, wherein the logic & drive circuit comprises: a logical OR circuit, configured to generate a set signal by executing OR operation on the comparison signal and the timeout signal; and a RS flip-flop, configured to generate the drive signal in response to the set signal and the minimum on time signal.

12. The control circuit of claim 8, further comprising: a constant on time circuit, configured to receive the input voltage and the output voltage, to generate a constant on time signal to the logic & drive circuit, to control the operation of the power stage.

13. The control circuit of claim 8, further comprising: a voltage comparator, configured to generate a comparison signal by comparing a sum of a feedback signal and a ramp signal with a voltage reference, the feedback signal being indicative of the output voltage; and a sleep comparator, configured to generate a sleep signal by comparing the feedback signal with a sleep reference.

14. The control circuit of claim 13, wherein the logic & drive circuit comprises: a logical OR circuit, configured to generate a set signal by executing OR operation on the comparison signal and the timeout signal; and a RS flip-flop, configured to generate the drive signal in response to the set signal and the minimum on time signal.

15. A method used in a switching regulator, the switching regulator including a power stage configured to convert an input voltage to an output voltage, the method comprising: detecting whether the switching regulator is in discontinuous current mode; starting to time a preset time duration if the detection indicates the switching regulation is in discontinuous current mode; and controlling the power stage to be ON for a minimum on time when timing out.

16. The method of claim 15, further comprising: detecting whether the switching regulator has entered sleep mode: if the switching regulator has entered sleep mode, disabling most of the circuits in the switching regulator; if not, continuing detecting whether the switching regulator is in discontinuous current mode.

17. The switching regulator of claim 15, wherein the step detecting whether the switching regulator has entered sleep mode comprises: comparing a feedback signal indicative of the output voltage with a sleep reference.

18. The switching regulator of claim 15, wherein the step detecting whether the switching regulator has entered sleep mode comprises: generating an error amplified signal by amplifying and integrating a difference between a feedback signal indicative of the output voltage and a voltage reference; and comparing the error amplified signal with a sleep reference.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 schematically shows a switching regulator 100 in accordance with an embodiment of the present invention.

[0009] FIG. 2 schematically shows a switching regulator 200 in accordance with an embodiment of the present invention.

[0010] FIG. 3 schematically shows a switching regulator 300 in accordance with an embodiment of the present invention.

[0011] FIG. 4 schematically shows the waveforms of the error amplified signal V.sub.EA, the sleep reference V.sub.sleep, the inductor current I.sub.L, the sleep signal SLEEP and the drive signal D.sub.G in FIGS. 2 & 3 in accordance with an embodiment of the present invention.

[0012] FIG. 5 schematically shows a switching regulator 500 in accordance with an embodiment of the present invention.

[0013] FIG. 6 schematically shows a switching regulator 600 in accordance with an embodiment of the present invention.

[0014] FIG. 7 schematically shows a flowchart 700 of a method used in a switching regulator in accordance with an embodiment of the present invention.

[0015] The use of the similar reference label in different drawings indicates the same of like components.

DETAILED DESCRIPTION

[0016] Embodiments of circuits for switching regulator with improved efficiency are described in detail herein. In the following description, some specific details, such as example circuits for these circuit components, are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc.

[0017] The following embodiments and aspects are illustrated in conjunction with circuits and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements.

[0018] FIG. 1 schematically shows a switching regulator 100 in accordance with an embodiment of the present invention. In the example of FIG. 1, the switching regulator 100 comprises: a power stage 101 and a control circuit 120, the power stage 101 including a power switch periodically ON and OFF, to convert an input voltage V.sub.IN into an output voltage V.sub.O; the control circuit 120 comprising: a DCM detector 102, configured to receive a current sensing signal I.sub.S indicative of a current flowing through the power stage 101, to generate a detect signal DCM, the detect signal DCM indicating whether the switching regulator 100 is in discontinuous current mode; a timer 103, operable to start to time if the detect signal DCM indicates the switching regulator 100 is in discontinuous current mode, and to generate a timeout signal T when the timer 103 times out; a minimum on time circuit 104, configured to generate a minimum on time signal (min-on) in response to the timeout signal T; and a logic & drive circuit 105, configured to generate a drive signal D.sub.G in response to the timeout signal T and the minimum on time signal (min-on), to control the operation of the power stage 101.

[0019] In one embodiment, the power stage 101 is controlled to be ON for a minimum on time duration when the switching regulator is in discontinuous current mode: the logic & drive circuit 105 is configured to turn on the power stage 101 in response to the timeout signal T, and configured to turn off the power stage 101 in response to the minimum on time signal (min-on) after the power stage 101 has been ON for the minimum on time duration.

[0020] In real applications, the switching regulator comprises an energy storage component (e.g. an inductor), and the current flowing through the power stage is the same current flowing through the energy storage component, which is typically indicated as the inductor current I.sub.L, as will be shown later in FIG. 4. Thus, the current sense signal I.sub.S also represents the inductor current I.sub.L. The DCM detector 102 compares the current sense signal I.sub.S with a zero reference voltage (e.g. 0.1V) to detect whether the system is in discontinuous current mode.

[0021] In one embodiment, the timer 103 starts to time in response to the detection of the DCM detector 102. The timer 103 is reset when the previous timing is over, and restarts to time when an update detection indicating the system is in discontinuous current mode again.

[0022] If the status of the switching regulator in discontinuous current mode lasted for a preset time duration, the power stage is controlled to be ON for a minimum on time duration. The current flowing through the power stage 101 (i.e. the inductor current) starts to rise during this minimum on time period, and starts to fall after the minimum on time period. When the current flowing through the power stage 101 falls to zero, the system enters discontinuous current mode again. If the system has not entered sleep mode yet, the timer 103 would time again; and the power stage 101 will be ON for the minimum on time duration again after the timer 103 times out. This process repeats: the power stage 101 is ON for the minimum on time when the discontinuous current mode lasts for the preset time duration in each switching cycle, so that a corresponding signal will finally reach the sleep reference, causing the system to successfully enter sleep mode. Accordingly, most of the circuits (e.g. the timer 103, the minimum on time circuit 104, the power stage 101, etc.) are disabled, which reduces the power loss and improves the efficiency. When the system enters sleep mode, the timer 103 will not time; and the power stage 101 will not be turned on until the system exits sleep mode.

[0023] FIG. 2 schematically shows a switching regulator 200 in accordance with an embodiment of the present invention. In the example of FIG. 2, the control circuit 120 comprises: the DCM detector 102, the timer 103, the minimum on time circuit 104 and the logic & drive circuit 105 as in FIG. 1, and the control circuit 120 further comprises: an error amplifier (EA) 106, configured to receive a voltage reference V.sub.REF and a feedback signal V.sub.FB indicative of the output voltage V.sub.O, to generate an error amplified signal V.sub.EA by amplifying and integrating a difference between the feedback signal V.sub.FB and the voltage reference V.sub.REF; a voltage comparator 107, configured to receive the error amplified signal V.sub.EA and a ramp signal V.sub.ramp, and to generate a comparison signal PWM by comparing the error amplified signal V.sub.EA with the ramp signal V.sub.ramp; and a sleep comparator 108, configured to receive the error amplified signal V.sub.EA and a sleep reference V.sub.sleep, and to generate a sleep signal SLEEP by comparing the error amplified signal V.sub.EA with the sleep reference V.sub.sleep, the sleep signal SLEEP operable to indicate whether the switching regulator enters sleep mode. The comparison signal PWM, the sleep signal SLEEP and the minimum on time signal (min-on) are configured to control the power stage 101 by way of the logic & drive circuit 105.

[0024] FIG. 2 also schematically shows a circuit configuration of the logic & drive circuit 105 in accordance with an embodiment of the present invention. In the example FIG. 2, the logic & drive circuit 105 comprises: a logical OR circuit (i.e. a first logical OR unit) 51, configured to receive the comparison signal PWM and the timeout signal T, to generate a set signal by executing OR operation on the comparison signal PWM and the timeout signal T; and a RS flip-flop 52, having a set input terminal S, a reset input terminal R and an output terminal Q, wherein the set input terminal S is configured to receive the set signal, the reset input terminal R is configured to receive the minimum on time signal (min-on), and the RS flip-flop 52 is configured to generate the drive signal D.sub.G in response to the set signal and the minimum on time signal (min-on), to control the operation of the power stage 101.

[0025] FIG. 3 schematically shows a switching regulator 300 in accordance with an embodiment of the present invention. The switching regulator 300 in FIG. 3 is similar to the switching regulator 200 in FIG. 2, with a difference that in the example of FIG. 3, the control circuit 120 of the switching regulator 300 further comprises: a constant on time circuit 109, configured to receive the input voltage V.sub.IN and the output voltage V.sub.O, to generate a constant on time signal COT to the logic & drive circuit 105, to control the operation of the power stage 101. The logic & drive circuit 105 further comprises: a logical OR circuit (i.e. a second logical OR unit) 53, configured to receive the minimum on time signal (min-on) and the constant on time signal COT, to generate a reset signal by executing OR operation on the minimum on time signal (min-on) and the constant on time signal COT, wherein the reset signal is then delivered to the reset input terminal of the RS flip-flop 52, to control the on time duration of the power stage 101.

[0026] When the switching regulators 200 and 300 are in operation, the feedback signal V.sub.FB is delivered to the error amplifier 106 to generate the error amplified signal V.sub.EA. If the load is in normal condition (e.g. the load current is inside a set range), the error amplified signal V.sub.EA is higher than the sleep reference V.sub.sleep, so the sleep signal SLEEP indicates that the system operates normally. If the inductor current is in CCM (continuous current mode), the detection of the DCM detector 102 would indicate that the system is not in discontinuous current mode. Accordingly, the timer 103 would not start to time, and the minimum on time circuit 104 takes no action. When the power stage 101 is turned off, the output voltage V.sub.O (i.e. the feedback signal V.sub.FB) decreases, and the error amplified signal V.sub.EA increases. When the error amplified signal V.sub.EA increases to the ramp signal V.sub.ramp, the comparison signal PWM turns to high, which sets the drive signal D.sub.G by way of the logical OR circuit 51. As a result, the power stage 101 is turned on. At the same time, the constant on time circuit 109 outputs the constant on time signal COT, so as to turn off the power stage 101 after the power stage 101 has been ON for a fixed on time period. Above process repeats, so as to regulate the output voltage V.sub.O to the desired voltage level.

[0027] If the load starts to decrease, causing the system to enter discontinuous current mode, the DCM detector 102 outputs the detect signal DCM to the timer 103. Then the timer 103 starts to time. When the discontinuous current mode condition lasted for the preset time duration, the power stage 101 is controlled to be ON for the minimum on time duration. During this minimum on time period, the inductor current rises until this time period ends. Then the inductor current starts to fall. When the inductor current falls to zero, the system enters discontinuous current mode again. If the error amplified signal V.sub.EA is still higher than the sleep reference V.sub.sleep at this time point, the system will not enter sleep mode. So the power stage 101 would be again turned on for the minimum on time duration. The process repeats until the error amplified signal V.sub.EA goes lower than the sleep reference V.sub.sleep. Then the sleep comparator 108 generates the sleep signal SLEEP to indicate the system enters sleep mode.

[0028] FIG. 4 schematically shows the waveforms of the error amplified signal V.sub.EA, the sleep reference V.sub.sleep, the inductor current I.sub.L, the sleep signal SLEEP and the drive signal D.sub.G in FIGS. 2 & 3 in accordance with an embodiment of the present invention. As shown in FIG. 4, the error amplified signal V.sub.EA has decreased to the sleep reference V.sub.sleep when the power stage 101 is ON for the minimum on time for successive two switching cycles. As a result, the sleep signal SLEEP jumps to high, which ensures the system enters sleep mode successfully. Accordingly, most of the circuits are disabled, the power loss is reduced and the efficiency is improved.

[0029] In the examples of FIG. 2 and FIG. 3, the feedback signal V.sub.FB is first converted to the error amplified signal V.sub.EA, and then the error amplified signal V.sub.EA is compared to the sleep reference V.sub.sleep (the sleep reference would have a relatively low value in such case), to detect whether the system is in discontinuous current mode and whether the system enters sleep mode. However, one skilled in the art should realize that the feedback loop may contain no error amplifier, and the feedback signal V.sub.FB may be compared to the sleep reference V.sub.sleep directly (the sleep reference would have a relatively high value in such case), to detect whether the system is in discontinuous current mode and whether the system enters sleep mode, which will be further discussed in the examples of FIG. 5 and FIG. 6.

[0030] FIG. 5 schematically shows a switching regulator 500 in accordance with an embodiment of the present invention. In the example of FIG. 5, the control circuit 120 comprises: the DCM detector 102, the timer 103, the minimum on time circuit 104 and the logic & drive circuit 105 as in FIG. 1, and the control circuit 120 further comprises: a voltage comparator 110, configured to receive a feedback signal V.sub.FB indicative of the output voltage V.sub.O, a voltage reference V.sub.REF and a ramp signal V.sub.ramp, to generate a comparison signal PWM by comparing a sum of the feedback signal V.sub.FB and the ramp signal V.sub.ramp with the voltage reference V.sub.REF; and a sleep comparator 111, configured to receive the feedback signal V.sub.FB and a sleep reference V.sub.sleep, to generate a sleep signal SLEEP by comparing the feedback signal V.sub.FB with the sleep reference V.sub.sleep. The comparison signal PWM, the sleep signal SLEEP and the minimum on time signal (min-on) are operable to control the power stage 101 by way of the logic & drive circuit 105, to convert the input voltage to the output voltage.

[0031] FIG. 6 schematically shows a switching regulator 600 in accordance with an embodiment of the present invention. The switching regulator 600 in FIG. 6 is similar to the switching regulator 500 in FIG. 5, with a difference that in the example of FIG. 6, the control circuit 120 of the switching regulator 600 further comprises: a constant on time circuit 109, configured to receive the input voltage V.sub.IN and the output voltage V.sub.O, to generate a constant on time signal COT to the logic & drive circuit 105, and to control the operation of the power stage 101. The logic & drive circuit 105 further comprises: a logical OR circuit (i.e. a second logical OR unit) 53, configured to receive the minimum on time signal (min-on) and the constant on time signal COT, to generate a reset signal by executing OR operation on the minimum on time signal (min-on) and the constant on time signal COT, wherein the reset signal is then delivered to the reset input terminal of the RS flip-flop 52, to control the on time duration of the power stage 101.

[0032] When the switching regulators 500 and 600 are in operation, the feedback signal V.sub.FB is directly compared with the sleep reference V.sub.sleep and the voltage reference V.sub.REF. If the load is in normal condition, the feedback signal V.sub.FB is lower than the sleep reference V.sub.sleep, so the sleep signal SLEEP indicates that the system operates normally. If the inductor current is in CCM, the detection of the DCM detector 102 would indicate that the system is not in discontinuous current mode. Accordingly, the timer 103 would not start to time, and the minimum on time circuit 104 takes no action. When the power stage 101 is turned off, the output voltage V.sub.O (i.e. the feedback signal V.sub.FB) decreases. When the sum of the feedback signal V.sub.FB and the ramp signal V.sub.ramp decreases to the voltage reference V.sub.REF, the comparison signal PWM turns to high, which sets the drive signal D.sub.G by way of the logical OR circuit 51. As a result, the power stage 101 is turned on. At the same time, the constant on time circuit 109 outputs the constant on time signal COT, so as to turn off the power stage 101 after the power stage 101 is ON for a fixed on time period. Above process repeats, so as to regulate the output voltage V.sub.O to the desired voltage level.

[0033] If the load starts to decrease, causing the system to enter discontinuous current mode, the DCM detector 102 outputs the detect signal DCM to the timer 103. Then the timer 103 starts to time. When the discontinuous current mode lasts for the preset time duration, the power stage 101 is controlled to be ON for the minimum on time duration. During this minimum on time period, the inductor current rises until this time period ends. Then the inductor current starts to fall. When the inductor current falls to zero, the system enters discontinuous current mode again. If the feedback signal V.sub.FB is still lower than the sleep reference V.sub.sleep at this time point, the system will not enter sleep mode. So the power stage 101 would be again turned on for the minimum on time duration. The process repeats until the feedback signal V.sub.FB goes higher than the sleep reference V.sub.sleep. Then the sleep comparator 111 generates the sleep signal SLEEP to indicate the system enters sleep mode. Accordingly, most of the circuits are disabled, the power loss is reduced and the efficiency is improved.

[0034] FIG. 7 schematically shows a flowchart 700 of a method used in a switching regulator in accordance with an embodiment of the present invention. The switching regulator including a power stage configured to convert an input voltage to an output voltage, the method comprises:

[0035] Step 701, detecting whether the switching regulator is in DCM (discontinuous current mode), if the detection indicates the switching regulator is in DCM, going to step 702, if not, continuing detecting whether the switching regulator is in DCM.

[0036] Step 702, starting to time a preset time duration in response to the detection. And

[0037] Step 703, controlling the power stage to be ON for a minimum on time when timing out.

[0038] In one embodiment, the method further comprising: step 704, detecting whether the switching regulator has entered sleep mode: if the switching regulator has entered sleep mode, going to step 705; if not, going back to step 701: continuing detecting whether the switching regulator is in DCM. And

[0039] Step 705, disabling most of the circuits in the switching regulator.

[0040] In one embodiment, the step detecting whether the switching regulator has entered sleep mode comprises: comparing a feedback signal indicative of the output voltage with a sleep reference.

[0041] In one embodiment, the step detecting whether the switching regulator has entered sleep mode comprises: generating an error amplified signal by amplifying and integrating a difference between a feedback signal indicative of the output voltage and a voltage reference; and comparing the error amplified signal with a sleep reference.

[0042] Several embodiments of the foregoing switching regulator provide improved efficiency compared to conventional technique discussed above. Unlike the conventional technique, several embodiments of the foregoing switching regulator monitor a current flowing through the power stage to detect whether the system is in discontinuous current mode. If the system is in discontinuous current mode, the power stage is controlled to be ON for a minimum on time duration in each switching cycle until the system enters sleep mode. So several embodiments of the foregoing switching regulator ensure the system successfully enters sleep mode even adopting constant on time control.

[0043] It is to be understood in these letters patent that the meaning of “A” is coupled to “B” is that either A and B are connected to each other as described below, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B.

[0044] This written description uses examples to disclose the invention, including the best mode, and also to enable a person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art.