UNIPOLAR RESISTIVE MEMORY

Abstract

A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.

Claims

1. A memory circuit comprising a plurality of elementary cells arranged in rows and in columns, each cell comprising: a programmable resistive element having a first end connected to a first node of the cell; and a control transistor having a first conduction node connected to a second end of the resistive element, a second conduction node connected to a second node of the cell, and a control node connected to a third node of the cell, wherein, in each row, the cells in the row have their first nodes connected to a same first row control conductive track and have their third nodes connected to a same second row control conductive track, and, in each column, the cells have their second nodes connected to a same column control conductive track, the memory circuit further comprising a control circuit capable of implementing operations of setting and resetting elementary cells of the memory according to a unipolar operating mode, the control circuit being capable of, during a step of setting or resetting a cell: applying a first voltage to the conductive track controlling the column comprising the cell to be programmed; applying a second voltage to the first conductive track controlling the row comprising the cell to be programmed; applying a third voltage to the second conductive track controlling the row comprising the cell to be programmed, the third voltage being capable of turning on the control transistor of the cell to be programmed; and applying a fourth voltage to the conductive tracks controlling columns which do not comprise the cell to be programmed, the fourth voltage being capable of turning off the control transistors in the cells comprised both in said columns and in the row comprising the cell to be programmed.

2. The memory circuit of claim 1, wherein, in each cell, the control transistor is an N-channel MOS transistor.

3. The memory circuit of claim 2, wherein the second and third voltages are greater than the first voltage, and the fourth voltage is greater than the third voltage minus the threshold voltage of the control transistor.

4. The memory circuit of claim 2, wherein the fourth voltage is in the range from the third voltage minus the threshold voltage of the control transistor to the second voltage.

5. The memory circuit of claim 2, wherein the fourth voltage is smaller than the second voltage.

6. The memory circuit of claim 1, wherein, in each cell, the control transistor is a P-channel MOS transistor.

7. The memory circuit of claim 6, wherein the second and third voltages are smaller than the first voltage, and the fourth voltage is smaller than the third voltage plus the threshold voltage of the control transistor.

8. The memory circuit of claim 6, wherein the fourth voltage is in the range from the second voltage to the third voltage plus the threshold voltage of the control transistor.

9. The memory circuit of claim 6, wherein the fourth voltage is greater than the second voltage.

10. The memory circuit of claim 1, wherein the control circuit is further capable of, during a phase of programming the cell, applying a fifth voltage to the first conductive tracks controlling rows which do not comprise the cell to be programmed, the difference between the first and fifth voltages being, in absolute value, smaller than or equal to a nominal maximum voltage specified for the cell control transistors.

11. The memory circuit of claim 10, wherein the fifth voltage is greater than the first voltage or smaller than the first voltage.

12. The memory circuit of claim 10 or 11, wherein the fifth voltage has a level intermediate between the first and second voltages.

13. The memory circuit of claim 10, wherein the fourth and fifth voltages are substantially equal.

14. The memory circuit of claim 1, wherein the third and fourth voltages are substantially equal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is an electric diagram of an example of an elementary cell of a resistive memory;

[0018] FIG. 2 is a timing diagram illustrating an example of a method for controlling the cell of FIG. 1;

[0019] FIG. 3 is an electric diagram of a resistive memory comprising a plurality of elementary cells of the type described in relation with FIG. 1;

[0020] FIG. 4 is an electric diagram of another embodiment of a resistive memory; and

[0021] FIG. 5 is an electric diagram of another embodiment of a resistive memory.

DETAILED DESCRIPTION

[0022] The same elements have been designated with the same reference numerals in the different drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the control circuits arranged at the periphery of a resistive memory to apply appropriate control signals to the elementary cells of the memory have not been detailed, the forming of such control circuits being within the abilities of those skilled in the art based on the functional indications described in the present disclosure. Unless otherwise specified, expressions “approximately”, “substantially”, and “in the order of” mean to within 10%, preferably to within 5%. In the present disclosure, term “connected” is used to designate a direct electric connection, with no intermediate electronic component, for example, by means of one or a plurality of conductive tracks or conductive wires, and term “coupled” or term “linked” is used to designate either an electric connection which may be direct (then meaning “connected”) or indirect (that is, via one or a plurality of intermediate components).

[0023] FIG. 1 is an electric diagram illustrating an example of an elementary cell 100 of a resistive memory. In this example, cell 100 comprises a single resistive storage element 101, for example, of PCM type, and a single control transistor 103. Resistive element 101 is compatible with a unipolar operation, that is, it is capable of being set or reset by application of voltages of same polarity between its electrodes. It should be noted that the programmable resistive elements adapted to a unipolar operating mode generally have a preferred direction of application of the programming voltage. Thus, the electrodes of a programmable resistive element of a unipolar memory are most often differentiated, one of the electrodes, called negative electrode or cathode, being intended to receive the low potential of the voltage for programming the element, and the other electrode, called positive electrode or anode, being intended to receive the high potential of the programming voltage. In the shown example, the negative electrode of resistive element 101 is designated with a − sign, and the positive electrode of resistive element 101 is designated with a + sign. The positive electrode (+) of element 101 is coupled to a first control node VBL of the cell, and the negative electrode (−) of element 101 is coupled to a first conduction node of transistor 103, the second conduction node of transistor 103 being coupled to a second control node VAL of the cell. Cell 100 further comprises a third control node WL coupled to the gate of transistor 103. In this example, transistor 103 is an N-channel MOS transistor.

[0024] FIG. 2 is a timing diagram illustrating an example of a method of controlling the cell of FIG. 1. More specifically, FIG. 2 shows the time variation of the voltages applied to control nodes VAL, WL, and VBL of cell 100 during cell set and reset phases.

[0025] In a phase of setting (SET) cell 100, node VAL, corresponding to the source of transistor 103, is set to a low reference node or ground VREFL, for example, a voltage in the order of 0 V, and a programming voltage pulse of high level as compared with reference voltage VREFL is applied to node VBL (initially at reference voltage VREFL). During the entire set phase, control transistor 103 of the cell is kept on by application of a high voltage level VCMDH (referenced to ground) to node WL.

[0026] During a phase (RESET) of resetting cell 100, similar voltages are applied to nodes VAL, VBL, and WL of cell 100, the main difference being the shape of the high-level programming voltage pulse applied to node VBL. More particularly, in the example of FIG. 2, the slope of the falling edge of the voltage pulse applied to node VBL during reset phases is greater than the slope of the falling edge of the voltage pulse applied to this same node VBL during set phases. Further, in this example, the maximum value of the voltage pulse applied to node VBL during reset phases is greater than the maximum value of the voltage pulse applied to this same node VBL during set phases. VH here designates the maximum voltage level (referenced to ground) applied to node VBL during cell set and reset phases. In practice, level VCMDH may be lower than level VH. As an illustration, levels VH and VCMDH may be respectively in the order of 2.5 V and in the order of 1.8 V (in the case where the reference voltage is at 0 V, it being understood that the described operation may be obtained by shifting all voltage levels upwards or downwards).

[0027] FIG. 3 is an electric diagram of a resistive memory comprising a plurality of elementary cells 100.sub.ij of the type described in relation with FIG. 1. Cells 100.sub.ij are arranged in an array of m rows and n columns, m and n being integers greater than 1, i and j being indexes respectively designating the rank of the row and the rank of the column to which each cell belongs, i being an integer in the range from 1 to m and j being an integer in the range from 1 to n. Cells 100.sub.ij are for example identical or similar. In each row of rank i of the array, the n cells 100.sub.ij of the row have their control nodes VAL connected to a same first row control conductive track VAL.sub.i, and have their control nodes WL connected to a same second row control conductive track WL.sub.i. In each column of rank j of the array, the m cells 100.sub.ij of the column have their control nodes VBL connected to a same column control conductive track VBL.sub.j. The memory of FIG. 3 further comprises a control circuit 201 capable of controlling the voltages applied to control tracks VAL.sub.i, WL.sub.i and VBL.sub.j of the memory to implement operations of setting or of resetting elementary cells of the memory according to a unipolar operating mode of the type described in relation with FIG. 2.

[0028] The operation of the memory of FIG. 3, implemented by control circuit 201, is the following. During a phase of setting or resetting a cell 100.sub.ij of the array (cell 100.sub.11 in the shown example), conductive track VAL.sub.i of the row containing the cell is set to low reference voltage VREFL, and a high-level programming voltage pulse, for example, of level VH, is applied to conductive track VBL.sub.j (initially at reference voltage VREFL) of the column containing the cell. During this entire set or reset phase, control transistor 103 of the cell is kept on by application of a high voltage level VCMDH to the conductive track WL.sub.i of the row containing the cell. To avoid an unwanted switching of a resistive storage element in another cell of the array, conductive tracks VAL.sub.i and WL.sub.i of the other rows of the array and conductive tracks VBL.sub.j of the other columns of the array may be maintained at reference voltage VREFL during the entire set or reset phase.

[0029] A problem raised by this operating mode is the relatively high stress undergone by control transistors 103 of the unprogrammed elementary cells of the row and of the column comprising the programmed cell. Indeed, during a phase of setting or of resetting a cell 100.sub.ij, each of the cells of the column of rank j, except for cell 100.sub.ij, has its control transistor 103 controlled to the off state, and is applied a voltage of level VH between its nodes VBL and VAL. In the case of MOS transistors, this results in an accelerated aging and in a risk of breakdown of the spacers of the non-activated transistors 103 of the column. Further, in each of the cells of the row of rank i except for cell 100.sub.ij, the cell control transistor 103 is applied a voltage of level VCMDH on its gate, and a substantially zero voltage between its conduction nodes. In the case of MOS transistors, this results in an accelerated aging and in a risk of breakdown of the gate oxide of the non-activated transistors 103 of the row. To avoid a premature degradation of transistors 103, the latter may be sized to resist the above-mentioned stress, but this has a cost in terms of semiconductor surface area occupied by the transistors, and is a limitation to the increase of the memory density.

[0030] Another problem posed by the above-described operating mode is that it results in the flowing of relatively high parasitic leakage currents in the memory. In particular, during a phase of setting or resetting a cell 100.sub.ij, a relatively high programming current flows from conductive track VAL.sub.i to conductive track VBL.sub.i, through cell 100.sub.ij. Under the effect of this current, and due to the intrinsic resistivity of conductive track VAL.sub.i, a potential gradient appears on conductive track VAL.sub.i. Thus, in each of the cells of the row of rank i, the voltage on node VAL of the cell may take a value slightly greater than the reference voltage applied at the end of conductive track VAL.sub.i. Given that a turn-on control voltage of level VCMDH is applied to control nodes WL of each of the cells in the row, relatively high parasitic currents may flow through transistors 103 of the non-activated cells of the row. Further, in each of the non-activated cells of the column comprising cell 100.sub.ij, leakage currents may appear due to the relatively high source-drain voltage applied to control transistors 103.

[0031] FIG. 4 is an electric diagram of an embodiment of a resistive memory. The memory of FIG. 4 comprises a plurality of elementary cell 200.sub.ij, for example, identical or similar. Elementary cells 200.sub.ij comprise the same elements as elementary cells 100.sub.ij of the memory of FIG. 3, arranged differently. In particular, in each elementary cell 200.sub.ij of the memory of FIG. 4, the series association of resistive element 101 and of transistor 103 is reversed between control nodes VAL and VBL of the cell with respect to the configuration described in relation with FIGS. 1 and 3. Thus, in the memory of FIG. 4, in each elementary cell 200.sub.ij, the positive electrode (+) of element 101 is coupled to control node VAL of the cell, and the negative electrode (−) of element 101 is coupled to a first conduction node of transistor 103, the second conduction node of transistor 103 being coupled to control node VBL of the cell. In the same way as in the configuration of FIGS. 1 and 3, third control node WL of the cell is connected to the gate of transistor 103.

[0032] Elementary cells 200.sub.ij of the memory of FIG. 4 are arranged in an array of m rows and n columns, similarly or identically to what has been described in relation with FIG. 3. In particular, in each row of rank i of the array, the n cells 200.sub.ij of the row have their control nodes VAL connected to a same first row control conductive track VAL.sub.i and have their control nodes WL connected to a same second row control conductive track WL.sub.i, and, in each column of rank j of the array, the m cells 200.sub.ij of the column have their control nodes VBL connected to a same column control conductive track VBL.sub.j. The memory of FIG. 4 further comprises a control circuit 301 capable of controlling the voltages applied to control tracks VAL.sub.i, WL.sub.i and VBL.sub.j of the memory to implement operations of setting or of resetting cells of the memory according to a unipolar operating mode.

[0033] The operation of the memory of FIG. 4, implemented by control circuit 301, is the following. During a phase of setting or resetting a cell 200.sub.ij of the array (cell 200.sub.11 in the shown example), the conductive track VBL.sub.j of the column containing the cell is set to reference voltage VREFL, and a high-level programming voltage pulse, for example, of level VH, is applied to conductive track VAL.sub.i (initially at reference voltage VREFL) of the row containing the cell. During this entire set or reset phase, control transistor 103 of the cell is kept on by application of a high voltage level VCMDH to the conductive track WL.sub.i of the row containing the cell.

[0034] Further, all along the set or reset phase, to avoid an unwanted switching of a resistive storage element in another cell of the array, the conductive tracks VBL.sub.j of the other columns of the array may be maintained at a high-level voltage (that is, greater than VREFL) VINT1H, the conductive tracks VAL.sub.i of the other rows of the array may be maintained at a high-level voltage (that is, greater than VREFL) VINT2H, and the conductive tracks WL.sub.i of the other rows of the array may be maintained at reference voltage VREFL.

[0035] Level VINT1H may be selected to ensure that the transistors 103 of the non-activated cells of the row comprising the programmed cell 200.sub.ij are off, while limiting to an acceptable level the source-drain voltage seen by these transistors, for example, to a level lower than or equal to the nominal drain-source voltage specified for these transistors. In particular, level VINT1H is selected to be greater than VCMDH-VTH, where VTH is the threshold voltage of transistors 103, so that the gate-source voltage of the transistors 103 of the non-activated cells in the row is smaller than threshold voltage VTH of transistors 103. Level VINT1H is for example substantially equal to level VCMDH. As a variation, level VINT1H is in the range from VCMDH-VTH to VH.

[0036] Level VINT2H may be selected to limit to an acceptable level the drain-source voltage of transistors 103 of the other rows in the array, for example, to a level smaller than or equal to the nominal drain source voltage specified for these transistors. As an example, level VINT2H is lower than level VH. Level VINT2H is for example substantially equal to level VINT1H, for example, in the order of VCMDH.

[0037] As compared with the configuration of FIG. 3, an advantage of the embodiment of FIG. 4 is that the transistors 103 of the unprogrammed cells of the row comprising the programmed cell are submitted to no significant stress, either at the level of their gate oxide (transistors 103 off), or at the level of their spacers (drain-source voltage smaller than VH). Further, in the embodiment of FIG. 4, the parasitic currents in transistors 103 of the unprogrammed cells of the row comprising the programmed cell can be made nonexistent or negligible.

[0038] Another advantage of the embodiment of FIG. 4 is that the transistors 103 of the unprogrammed cells of the column comprising the programmed cell see a decreased drain-source voltage as compared with the configuration of FIG. 3, whereby the stress and the leakage currents are decreased.

[0039] Thus, in the embodiment of FIG. 4, only the programmed cell is likely to be submitted to significant stress. In particular, only the programmed cell is likely to see between its terminals a voltage of level VH. This results, for identical sizings of transistors 103, in an increased lifetime and reliability of the memory as compared with the configuration of FIG. 3. Further, the decrease of parasitic leakage currents enables to limit the electric power consumption as compared with the configuration of FIG. 3.

[0040] FIG. 5 is an electric diagram of another embodiment of a resistive memory. The embodiment of FIG. 5 differs from the embodiment of FIG. 4 in that, in the embodiment of FIG. 5, the control transistors of the elementary cells of the memory are P-channel MOS transistors.

[0041] The memory of FIG. 5 comprises a plurality of elementary cell 300.sub.ij, for example, identical or similar. In this example, each elementary cell 300.sub.ij comprises a single resistive storage element 101 of the type described in relation with FIGS. 1, 3, and 4, and a single control transistor 105. In this example, transistor 105 is a P-channel MOS transistor. The negative electrode (−) of element 101 is coupled to a first control node VAL of the cell, and the positive electrode (+) of element 101 is connected to a first conduction node of transistor 105, the second conduction node of transistor 105 being connected to a second control node VBL of the cell. Each elementary cell 300.sub.ij further comprises a third control node WL connected to the gate of transistor 105.

[0042] Elementary cells 300.sub.ij of the memory of FIG. 5 are arranged in an array of m rows and n columns, similarly or identically to what has been described in relation with FIGS. 3 and 4. In particular, in each row of rank i of the array, the n cells 300.sub.ij of the row have their control nodes VAL connected to a same first row control conductive track VAL.sub.i and have their control nodes WL connected to a same second row control conductive track WL.sub.i, and, in each column of rank j of the array, the m cells 300.sub.ij of the column have their control nodes VBL connected to a same column control conductive track VBL.sub.j. The memory of FIG. 5 further comprises a control circuit 401 capable of controlling the voltages applied to control tracks VAL.sub.i, WL.sub.i and VBL.sub.j of the memory to implement operations of setting or resetting cells of the memory according to a unipolar operating mode.

[0043] The operation of the memory of FIG. 5, implemented by control circuit 401, is the following. During a phase of setting or resetting of a cell 300.sub.ij of the array (cell 300.sub.11 in the shown example), conductive track VBL.sub.j of the column containing the cell is set to a high reference voltage (that is, greater than low reference voltage VREFL) VREFH, for example, of level VH, and a low-level programming voltage pulse, that is, smaller than high reference voltage VREFH, is applied to conductive track VAL.sub.i (initially at high reference voltage VREFH) of the row containing the cell. The level and the shape of the low-level programming voltage pulse applied to track VAL.sub.i are selected according to the state to which the cell is desired to be programmed. As an example, by analogy with the embodiment of FIG. 2, if the level of high reference voltage VREFH is equal to VH, the level, that is, the minimum value, of the low-level programming voltage pulse applied to track VAL.sub.i, may be in the order of low reference voltage VREFL in the case of a reset operation, or greater than low reference voltage VREFL in the case of a set operation. During the entire set or reset phase, control transistor 105 of the cell is kept on by application of a low voltage level (that is, smaller than VREFH) VCMDL to the conductive track WL.sub.i of the row containing the cell.

[0044] Further, all along the set or reset phase, to avoid an unwanted switching of a resistive storage element in another cell of the array, the conductive tracks VBL of the other columns of the array may be maintained at a low-level voltage (smaller than VREFH) VINT1L, the conductive tracks VAL.sub.i of the other rows of the array may be maintained at a low-level voltage (smaller than VREFH) VINT2L, and the conductive tracks WL.sub.i of the other rows of the array may be maintained at reference voltage VREFH.

[0045] Level VINT1L may be selected to ensure that transistors 105 of the non-activated cells of the row comprising the programmed cell 300.sub.ij are off, while limiting to an acceptable level the source-drain voltage seen by these transistors, for example, to a level lower than or equal to the nominal drain-source voltage specified for these transistors. In particular, level VINT1L is selected to be smaller than VCMDL+VTH, where VTH is the threshold voltage of transistors 105, so that the source-gate voltage of transistors 105 of the non-activated cells in the row is smaller than threshold voltage VTH of transistors 105. Level VINT1L is for example substantially equal to level VCMDL. As a variation, level VINT1L is in the range from VCMDL+VTH to VREFL.

[0046] Level VINT2L may be selected to limit to an acceptable level the drain-source voltage of transistors 105 of the other rows in the array, for example, to a level smaller than or equal to the nominal drain source voltage specified for these transistors. As an example, level VINT2L is greater than level VREFL. Level VINT2L is for example substantially equal to level VINT1L, for example, in the order of VCMDL.

[0047] Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the described embodiments are not limited to the above-mentioned examples where the basic programmable resistive element of the memory is of PCM type. More generally, the described embodiments may be adapted to any type of programmable resistive element compatible with a unipolar operation, for example, programmable resistive elements of unipolar OxRAM type, as well as all the resistive elements where the polarity of the programming current does not matter, for example, the resistive elements where the programming is performed by Joule effect.

[0048] Further, the described embodiments are not limited to the above-described specific case where the electrodes of the basic programmable resistive element of the memory are differentiated (anode/cathode). The above-described embodiments are also compatible with symmetrical or “non-polar” programmable resistive elements.

[0049] Further, although only examples of control methods where a single elementary cell of the memory is programmed have been described hereabove, the above-described embodiments are compatible with an operation where a plurality of elementary cells of a same row or of a same column are simultaneously programmable. As an example, in the embodiment of FIG. 4, to simultaneously program a plurality of cells of a same column, a plurality of high-voltage programming voltage pulses may be simultaneously applied to the conductive tracks VAL.sub.i controlling the rows comprising the cells to be programmed. To simultaneously program a plurality of cells of a same row, the row control conductive line VAL.sub.i may be maintained at a high reference voltage VREFH, for example, of level VH, for the entire programming phase, and low-level programming voltage pulses, that is, smaller than VREFH, may be simultaneously applied to the conductive tracks VBL.sub.j (initially at level VREFH or at level VINT1) controlling the columns comprising the cells to be programmed.

[0050] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.