VOLTAGE REGULATOR WITH ADAPTIVE BIAS NETWORK

Abstract

A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate providing an output voltage includes a first input connected to a supply voltage and a second input connected to the error amplifier output. A feedback network generating the feedback voltage includes a first terminal connected to the output of the pass gate and a second terminal connected to the second input of the error amplifier. An adaptive bias network providing the adaptive bias current includes a first transistor connected to the bias terminal of the error amplifier, a second transistor connected to the first transistor as a current mirror, and a third transistor connected in parallel with the pass gate.

Claims

1. A low drop-out (LDO) voltage regulator comprising: an error amplifier configured to generate an amplified error voltage, the error amplifier having a first input terminal for receiving a reference voltage, a second input terminal for receiving a feedback voltage, a current bias terminal for receiving an adaptive bias current, and an output terminal; a pass gate configured to provide an output voltage to at least one external component, the pass gate having a first input terminal, a second input terminal and an output terminal, the first input terminal of the pass gate being connected to a supply voltage and the second input terminal being connected to the output terminal of the error amplifier; a voltage feedback network configured to generate the feedback voltage, the voltage feedback network having a first terminal connected to the output terminal of the pass gate and a second terminal connected to the second input terminal of the error amplifier; and an adaptive bias network configured to provide the adaptive bias current to the error amplifier, the adaptive bias network having a first transistor, a second transistor, and a third transistor, the first transistor connected to the current bias terminal of the error amplifier, the second transistor connected to the first transistor as a current mirror, and the third transistor connected in parallel with the pass gate.

2. The LDO voltage regulator of claim 1, wherein the adaptive bias current through the first transistor is proportional to a current through the second transistor, a current through the third transistor is proportional to an output load current, and a current through the error amplifier scales proportionally with the output load current.

3. The LDO voltage regulator of claim 1, further comprising an auxiliary bias network connected to the current bias terminal of the error amplifier to prevent bistable operation.

4. The LDO voltage regulator of claim 3, wherein the auxiliary bias network comprises a resistor, a fourth transistor, and a fifth transistor, the resistor having a first terminal connected to the supply voltage and a second terminal connected to the fourth transistor, the fourth transistor connected to the fifth transistor as a current mirror, and the fifth transistor connected to the current bias terminal of the error amplifier.

5. The LDO voltage regulator of claim 1, wherein the error amplifier includes a diode-connected transistor connected to the output terminal of the error amplifier that is configured to have a size selected to enhance bandwidth of the error amplifier.

6. The LDO voltage regulator of claim 1, wherein the adaptive bias network includes a resistor-capacitor network configured to provide stability to the LDO voltage regulator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.

[0009] FIG. 1 is a block diagram of an example embodiment of an LDO voltage regulator.

[0010] FIG. 2 is a circuit diagram of the example embodiment of FIG. 1.

[0011] FIG. 3 illustrates an example plot of regulated voltage offset versus load current.

[0012] FIG. 4 illustrates an example plot of voltage gain versus frequency.

[0013] FIG. 5 illustrates an example plot of loop phase versus frequency.

DETAILED DESCRIPTION

[0014] A description of example embodiments of the invention follows.

[0015] FIG. 1 is a block diagram of an example embodiment of an LDO voltage regulator 100. The LDO regulator 100 steps-down an input supply voltage, V.sub.DD, to a smaller regulated output voltage, V.sub.REG through pass gate transistor 104 to provide a regulated voltage to one or more external components (not shown). The LDO voltage regulator 100 includes an error amplifier 102 with bandwidth (BW) enhancement 108, pass gate transistor 104, a resistor-based feedback network 106, and current biasing with an auxiliary bias network 110 and main adaptive bias network 112.

[0016] The regulated output V.sub.REG has load current I.sub.L and load capacitance C.sub.L which affect the stability of the regulator. The regulated output V.sub.REG is also fed back around to the pass gate transistor 104 through the resistor-based voltage feedback network 106, and the error amplifier 102. Assuming a large loop gain, then the regulated output voltage is generally given by:

[00001]$V_{\mathrm{REG}}=\frac{V_{\mathrm{FB}}}{\beta }=\frac{V_{\mathrm{REF}}}{\beta }=V_{\mathrm{REF}}.Math.\frac{R_1+R_2}{R_2}$

[0017] FIG. 2 is a circuit diagram 200 of the example embodiment of FIG. 1. The input supply voltage V.sub.DD passes through pass gate transistor P 204 to the regulated output V.sub.REG. The regulated output voltage also includes voltage feedback network 206, including R.sub.1 and R.sub.2, load capacitance C.sub.L, and load current I.sub.L.

[0018] Transistor pair G.sub.1, G.sub.2, transistor pair B.sub.1, B.sub.2, and transistors C, and P are PMOS transistors which have their respective source terminals connected to supply voltage V.sub.DD. The remaining transistors F, E, pair N.sub.1, N.sub.2, A, and D are NMOS transistors.

[0019] Error amplifier 208 includes transistor pair N.sub.1, N.sub.2, transistor pair B.sub.1, B.sub.2, and transistor pair G.sub.1, G.sub.2. Reference voltage V.sub.REF connects to the gate terminal of transistor N.sub.2. Feedback voltage V.sub.FB is fed back from feedback network 206 to the gate terminal of transistor N.sub.1. The drain terminal of transistor N.sub.1 is connected to the drain and gate terminals of transistors B.sub.1 and G.sub.1. The drain terminal of transistor N.sub.2 is connected to the drain terminals of transistors B.sub.2 and G.sub.2 and the gate terminal of transistor G.sub.2 which provides the output for the error amplifier 202.

[0020] Pass gate transistor P 204 outputs V.sub.REG at its drain terminal. The gate terminal of transistor P is connected to the respective gate terminals of transistors C and G.sub.2 and the drain terminals of B.sub.2, G.sub.2, and N.sub.2.

[0021] A resistive divider is employed as the feedback network 206. The resistive divider includes resistor R.sub.1 and resistor R.sub.2 connected in series. The resistors R.sub.1, R.sub.2 can scale down the output voltage V.sub.REG according to different values of resistors R.sub.1, R.sub.2 and feed a voltage V.sub.FB lower than V.sub.REG back to the gate terminal of the transistor N.sub.1.

[0022] Transistors C, D, and A form an adaptive bias network 212 that increases DC loop gain and saves power. Transistor A provides the error amplifier 202 with most of its bias current through a common mode connection to node 214 connecting the source terminals of transistor pair N.sub.1, N.sub.2. The bias current connects to a current mirror (diode-connected transistor D), so that the current through transistor A is proportional to the current through transistor D. The respective source terminals of transistors A and D are connected to ground. The drain terminal of transistor D is connected to the drain terminal of transistor C. Transistor C is connected in parallel with the pass gate transistor P at node V.sub.BP. As a result, the current through transistor C is proportional to the output load current I.sub.L as it varies in time. Because the current through C is proportional to I.sub.L and the current through A is proportional to D, the current through the error amplifier 202 scales proportionally with load current. This makes the design more efficient than the conventional topology under varying loads.

[0023] Another challenge in regulator design is stability. The nets V.sub.BP and V.sub.REG both add pole frequencies to the transfer function. Either one pole or the other must dominate for a stable system, however. For regulators supplying a voltage to a PLL, maximizing the output load capacitance reduces the amount of ripple on V.sub.REG. Thus, it is preferable that the pole frequency at V.sub.REG dominate. One method of improving stability is reducing the gain of the error amplifier 202 by adding diode-connected transistor G.sub.2 to the output terminal 216 of the error amplifier 202 as BW enhancement 208. By changing the ratio for transistor G.sub.1, G.sub.2 to B.sub.1, B.sub.2, the circuit designer can tune the gain, and the pole can be pushed out to a higher frequency, providing bandwidth enhancement. At the same time, the output pole becomes dominate and stability is ensured. A second diode-connected transistor G.sub.1 is added to the left side of the error amplifier 202 for matching so that the total size of the transistors on the left and right sides of the error amplifier 202 are the same.

[0024] The resistor-capacitor (RC) network consisting of R.sub.B and C.sub.B provides stability to the adaptive bias network 212. The network 212 adds a positive feedback loop with a high bandwidth because the net V.sub.A between transistors C and D does not have a large capacitance unlike the net V.sub.REG. Adding the RC network R.sub.B,C.sub.B introduces a pole and zero to the network 212 to provide stability in the overall system.

[0025] The LDO voltage regulator 200 includes an auxiliary bias network 210 that functions to prevent bistable operation and ensure startup. The auxiliary bias network 210 includes resistor R.sub.F connected at one end to V.sub.DD, which provides current through the current mirror of transistor F to transistor E. The drain terminal of transistor F connects to the other end of resistor R.sub.F. The source terminals of transistors F and E are connected to ground. The drain terminal of transistor E is connected to node 214 connecting the source terminals of transistor pair N.sub.1, N.sub.2 of the error amplifier 202. The auxiliary bias current is small because it does not need to be large to ensure that the circuit powers-up. Additionally, a small auxiliary current does not significantly affect the operation of the adaptive bias network 212.

[0026] FIG. 3 shows the regulated voltage offset versus the output load current for two different LDO regulator topologies. The first LDO regulator topology, indicated by the dashed line, uses a constant bias current like those found in conventional voltage regulators. Over a large range in current loads, the regulated voltage varies by approximately 12%. The second LDO regulator topology, indicated by the solid line, uses the adaptive bias current approach described in connection with the present disclosure, such that the regulated voltage now only varies by approximately 2%.

[0027] FIG. 4 illustrates an example plot of voltage gain versus frequency. In particular, the plot shows the magnitude response of the voltage regulator 200 between several different nets. The dotted line shows the voltage gain of the pass gate transistor 204, V.sub.REG/N.sub.BP. The pass gate transistor 204 is an amplifier with a single pole frequency. The dashed line depicts the voltage gain of the error amplifier 202, V.sub.BP/V.sub.REF, and includes the effect of the adaptive bias network 212. Unlike a traditional error amplifier, which has a single pole frequency, the error amplifier 202 has two pole frequencies and one zero frequency. The high frequency pole is created by transistor pair G, which provides bandwidth extension and stability. The transistor pair G also decreases the DC gain of the error amplifier 202, which contributes to the large regulated voltage offset of the dashed line with constant bias current in FIG. 3. The addition of the pole and zero frequency by the RC network R.sub.B,C.sub.B in the adaptive bias network 212 allows the voltage regulator 200 to increase the DC gain of the error amplifier 202 and reduce the regulated voltage offset in FIG. 3.

[0028] Turning again to FIG. 4, the overall loop gain of the voltage regulator 200 is given by the solid line, V.sub.FB/V.sub.REF. This overall loop gain corresponds to the mathematical summation of the pass gate, error amplifier, and resistor divider voltage gains and represents the overall magnitude response that can be used for stability analysis. A diamond 402 represents the frequency at which the gain crosses 0 dB, also called the gain-bandwidth product (GBP).

[0029] FIG. 5 illustrates an example plot of loop phase versus frequency for the voltage regulator 200. Because the corresponding diamond 502 is >−120° (i.e. the dashed line), the system is considered stable.

[0030] Those skilled in the art will appreciate that there are other alternatives to the MOS transistors for the embodiments disclosed herein. Other type and other combination of transistors can be employed to implement the functions of the error amplifier 202, the auxiliary bias network 210, the main adapative bias network 212, and the pass gate 204 without departing from the spirit of the present disclosure.

[0031] While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.