Optoelectronic semiconductor chip and method for the production thereof

Abstract

A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer having at least one n-doped semiconductor layer. An activation step suitable for electrically activating the p-doped region is effected before or during the formation of the covering layer. An optoelectronic semiconductor chip which can be produced by the method is additionally specified.

Claims

1. A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system, comprising the steps of: forming a semiconductor section with at least one p-doped region, and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer being free of p-doped semiconductor material and having at least one n-doped semiconductor layer, wherein an activation step separate from the forming of the p-doped region and suitable for electrically activating the p-doped region is effected before the formation of the covering layer.

2. The method as claimed in claim 1, wherein the n-doped semiconductor layer is formed with a thickness of >20 nm.

3. The method as claimed in claim 1, wherein the activation step is effected before the n-doped semiconductor layer is formed.

4. The method as claimed in claim 1, wherein forming the n-doped semiconductor layer comprises molecular beam epitaxy.

5. The method as claimed in claim 1, wherein forming the n-doped semiconductor layer comprises metal organic vapor phase epitaxy, using nitrogen sources which do not produce any free hydrogen radicals during the growth.

6. The method as claimed in claim 1, wherein the covering layer is formed in such a way that a spacer layer with nominally undoped semiconductor material is arranged between the n-doped semiconductor layer and the semiconductor section.

7. The method as claimed in claim 1, wherein forming the covering layer comprises forming a current spreading layer with a transparent, electrically conductive oxide and the activation step is effected before the current spreading layer is formed.

8. The method as claimed in claim 7, wherein forming the covering layer comprises epitaxial growth of semiconductor material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic side view of an optoelectronic semiconductor chip in accordance with the first exemplary embodiment,

(2) FIG. 2 shows a schematic side view of an optoelectronic semiconductor chip in accordance with the second exemplary embodiment,

(3) FIG. 3 shows a schematic side view of an optoelectronic semiconductor chip in accordance with the third exemplary embodiment,

(4) FIG. 4 shows a schematic side view of an optoelectronic semiconductor chip in accordance with the fourth exemplary embodiment,

(5) FIG. 5 shows a schematic side view of an optoelectronic semiconductor chip in accordance with the fifth exemplary embodiment,

(6) FIG. 6 shows a schematic side view of an optoelectronic semiconductor chip in accordance with the sixth exemplary embodiment,

(7) FIG. 7 shows a schematic side view of an incomplete luminescence diode chip in accordance with a seventh exemplary embodiment during a method stage of a first exemplary embodiment of the method,

(8) FIG. 8 shows a temperature-time diagram for illustrating the temperature profile during the method in accordance with the first exemplary embodiment,

(9) FIG. 9 shows a schematic side view of the complete optoelectronic semiconductor chip in accordance with the seventh exemplary embodiment, and

(10) FIGS. 10 to 12 show diagrams for illustrating the forward voltage U.sub.f as a function of the thickness of layers of the covering layer during activation for optoelectronic semiconductor chips in accordance with different embodiments.

DETAILED DESCRIPTION OF THE DRAWINGS

(11) In the exemplary embodiments and the figures, identical or identically acting constituent parts are in each case provided with the same reference symbols. The elements illustrated and also the size relationships of the elements among one another should not necessarily be regarded as true to scale. Moreover, some details of the figures are illustrated with an exaggerated size in order to afford a better understanding.

(12) The semiconductor chip illustrated in FIG. 1 has a semiconductor section 2 and a covering layer 3. The covering layer 3 is disposed downstream of the semiconductor section 2 in the growth direction 7. The semiconductor section 2 contains a p-doped layer 21 and also an active layer 4. The active layer 4 has at least one active region suitable for generating electromagnetic radiation. The p-doped layer 21 is a barrier layer for the active region of the active layer 4. The p-doped layer 21 is part of a p-doped region of the semiconductor section 2. Part of the active layer 4 is likewise p-doped.

(13) The covering layer 3 has a nominally undoped spacer layer 31 and also an n-doped semiconductor layer 32. The n-doped semiconductor layer 32 is disposed downstream of the nominally undoped layer 31 in the growth direction 7.

(14) The semiconductor chip 1 illustrated in FIG. 1 terminates with the covering layer in the growth direction, that is to say that the covering layer or the n-doped layer 32 of the covering layer 3 is an outer layer. The semiconductor chip 1 can be electrically conductively contact-connected for example by means of a metallic contact material, but this is not illustrated in FIG. 1. Moreover, the semiconductor chip 1 in accordance with the exemplary embodiment illustrated in FIG. 1 can comprise further layers and regions that are not illustrated in FIG. 1. Thus, it is possible for the semiconductor chip 1 to have a substrate which is arranged on a side of the semiconductor section 2 which is remote from the covering layer 3.

(15) The semiconductor chips 1 illustrated in the rest of the figures can also have in each case a growth substrate which is disposed upstream of the illustrated part of the semiconductor chip 1 in the growth direction 7. A growth substrate 6 of the semiconductor chip 1 is illustrated in the case of the exemplary embodiment illustrated in FIG. 9. Substrates used can be n-doped or p-doped electrically conductive substrates based on, for example, GaN, SiC or Si(111). However, it is also possible, in principle, for an electrically nonconductive substrate, for example based on sapphire and/or AlN, to be used.

(16) A growth substrate is required for forming semiconductor layers of the semiconductor chip 1. The semiconductor layers are formed by means of epitaxial growth, that is to say of epitaxy. It is possible, for example, for the growth substrate to be thinned or completely removed. The semiconductor chip 1 can then be fixed on a carrier for example by its surface which faces in the growth direction 7. Such a carrier, which is not illustrated in any of the figures, does not change anything about the growth direction 7 of the semiconductor chip. The growth direction runs from a side of the semiconductor chip 1 on which a growth substrate is arranged or was arranged to a side on which the covering layer is arranged. By way of example, semiconductor materials from the III-V semiconductor material system In.sub.yGa.sub.1-x-yAl.sub.xN are grown “Ga-face up”. The carrier can be adapted better, with regard to its coefficient of thermal expansion, to the grown layers than an original growth substrate.

(17) The semiconductor layers of the semiconductor chip 1 are preferably all based on In.sub.yGa.sub.1-x-yAl.sub.xN where 0≦x≦1, 0≦y≦1 and x+y≦1. Silicon, for example, is suitable as an n-type dopant. Magnesium, for example, is used as a p-type dopant.

(18) The active layer 4 contains for example a conventional pn junction, a double heterostructure, a single quantum well structure (SQW structure) or a multiple quantum well structure (MQW structure). The active layer preferably contains a multiple quantum well structure. Structures of this type are known to the person skilled in the art and are therefore not explained in any greater detail at this juncture.

(19) While in the case of the semiconductor chip 1 illustrated in FIG. 1, the active layer 4 is arranged on a side of the semiconductor section 2 which faces the covering layer 3, this is not the case in the semiconductor chip 1 illustrated in FIG. 2. Here, the active layer 4 is arranged on a side of the semiconductor section 2 which is remote from the covering layer 3. In growth direction 7, proceeding from the active layer 4, the semiconductor section 2 of the semiconductor chip 1 additionally has a nominally undoped spacer layer 22 and a p-doped layer 21.

(20) The covering layer 3 adjoins the semiconductor section 2 in the growth direction. It comprises for example a single n-doped semiconductor layer 32. As an alternative, the covering layer can also have a plurality of different layers.

(21) The semiconductor chip 1 described with reference to FIG. 1 has an inverted polarity compared with conventional semiconductor chips based on a nitride semiconductor system. That is to say that in conventional semiconductor chips, the covering layer would generally not have an n-doped semiconductor layer, but instead a p-doped semiconductor layer. Likewise, in a conventional semiconductor chip, an n-doped layer would be formed instead of the p-doped layer 21.

(22) It was established that an inverted polarity of the semiconductor chip can lead to a significant improvement of the internal quantum efficiency. In conventional semiconductor chips, the internal quantum efficiency decreases greatly as the density of the current being pressed into the semiconductor chip increases. By contrast, what can be achieved in the case of a semiconductor chip having inverted polarity is that the internal quantum efficiency is significantly less dependent on the intensity of the impressed current. Ideally, the internal quantum efficiency of the semiconductor chip is virtually independent of the current density.

(23) By contrast, in terms of its construction the semiconductor chip 1 illustrated in FIG. 2 essentially corresponds to a conventional semiconductor chip having customary polarity. It contains in growth direction 7 in succession an n-doped layer 5, an active layer 4 and a p-doped layer 21. A nominally undoped spacer layer 22, for example, can be arranged between the active layer and the p-doped layer 21.

(24) While conventional semiconductor chips generally terminate with a p-doped layer in the growth direction 7, however, the semiconductor chip illustrated in FIG. 2 has the covering layer 3 with the n-doped semiconductor layer 32. An improved current spreading can be realized by means of the covering layer 3 compared with conventional semiconductor chips. p-doped semiconductor materials based on a nitride semiconductor system have a poorer transverse conductivity than n-doped layers based on such a material system. The thickness of the n-doped semiconductor layer 32 is 120 nm, for example. As a result, alongside the improved current spreading, in addition an improved coupling out of electromagnetic radiation from the semiconductor chip can also be obtained. The n-doped semiconductor layer therefore also functions for example as an advantageous coupling-out layer. In the case of a semiconductor chip which emits blue light, the thickness of the n-doped semiconductor layer 32 is approximately 140 nm, for example. In the case of a semiconductor chip which emits green light, the thickness of the n-doped semiconductor layer 32 is approximately 150 nm, for example.

(25) The semiconductor chips 1 illustrated in FIGS. 3 and 4 correspond, in terms of their polarity, to the semiconductor chip 1 explained previously with reference to FIG. 1. In contrast to the semiconductor chip illustrated with reference to FIG. 1, a current spreading layer 34 is additionally contained in the covering layer 3 in the case of the semiconductor chips illustrated in FIGS. 3 and 4. The current spreading layer 34 has a transparent, electrically conductive oxide (TCO) or it essentially comprises a TCO.

(26) Materials based on, for example, tin oxide, indium oxide, indium tin oxide or zinc oxide are suitable as TCO. The current spreading layer 34 essentially comprises indium tin oxide, for example. It has e.g. a thickness of 500 nm. Current spreading layers of this type can be applied particularly well on n-doped semiconductor layers.

(27) The n-doped semiconductor layer 32 can be formed with a significantly smaller thickness in the case of the semiconductor chips 1 illustrated in FIGS. 3 and 4 than in the case of the semiconductor chip illustrated in FIG. 1, in order to realize a comparable or even better current spreading. The thickness of the n-doped semiconductor layer 32 is for example only between 5 and 15 nm; for example, the thickness is approximately 10 nm.

(28) In the case of the semiconductor chip 1 illustrated in FIG. 4, in contrast to the semiconductor chip illustrated in FIG. 3, current barriers 35 are integrated in the covering layer 3. A current barrier 35 can be formed for example at least one of the following positions: between the active layer 4 and the nominally undoped spacer layer 31; between the spacer layer 31 and the n-doped semiconductor layer 32; between the n-doped semiconductor layer 32 and the current spreading layer 34. Any desired combinations are possible, in principle, with regard to the position or the number of current barriers.

(29) The current barriers 35 have for example an electrically insulating material such as silicon dioxide, for instance. During the production of the semiconductor chip, e.g. a thin insulation layer is applied over the area on a semiconductor layer. The insulation layer is subsequently patterned, that is to say that it is partially removed again. This can be done by means of a lithographic process.

(30) A desired current distribution in the semiconductor chip can be realized in a targeted manner by means of the current barriers. During operation of the semiconductor chip, the current density is significantly reduced in regions which are laterally shaded by a current barrier. The current carrying and the generation of electromagnetic radiation can thus largely be restricted to regions from which the generated light can be coupled out from the semiconductor. By way of example, light cannot be coupled out at surface regions which are covered with a largely radiation-opaque material, for example a metal.

(31) The semiconductor chips illustrated in FIGS. 5 and 6 have essentially the construction of the semiconductor chip 1 described previously with reference to FIG. 2. One difference is that the covering layer 3 additionally has a current spreading layer 34. The current spreading layer 34 can be constituted analogously to the current spreading layer 34 described previously in connection with FIGS. 3 and 4.

(32) Analogously to the semiconductor chip illustrated with reference to FIG. 4, the semiconductor chip illustrated in FIG. 6 also has at least one current barrier 35 in the covering layer. Preferably, a plurality of current barriers are contained. Current barriers can be arranged between the p-doped semiconductor layer 21 and the nominally undoped spacer layer 32 and/or between the spacer layer 32 and the n-doped semiconductor layer 34. The current barriers 35 can be produced and constituted analogously to the current barriers described previously in connection with FIG. 4.

(33) FIG. 7 illustrates an incomplete semiconductor chip during a method stage of an exemplary embodiment of the method. The incomplete semiconductor chip has in growth direction 7 in succession a growth substrate 6, a buffer layer 61, an n-doped semiconductor layer 5, a tunnel contact 51, a semiconductor section 2, a spacer layer 31 and also an n-doped semiconductor layer 32.

(34) The semiconductor section 2 has in the growth direction a p-doped semiconductor layer 21, a spacer layer 22 and also an active layer 4. The n-doped semiconductor layer 32 is incomplete, that is to say that the epitaxial growth of the n-doped semiconductor layer 32 was interrupted.

(35) An activation step is carried out during the interruption. The interruption is effected while the n-doped semiconductor layer 32 still has a small thickness of less than or equal to 20 nm. By way of example, the n-doped semiconductor layer 32 has a thickness of approximately 5 nm at the point in time of the interruption. As an alternative, the interruption can also be effected before the formation of the n-doped semiconductor layer 32 has been begun. By way of example, the interruption can advantageously be effected after the active layer 4 has been formed and before the formation of the spacer layer 31 is begun.

(36) The activation step has for example a time period of 6 to 15 minutes. The activation step typically lasts approximately 8 minutes. The activation is carried out for example at a temperature of between 500° C. and 800° C. inclusive. This can be effected at a constant temperature. As an alternative, however, it is also possible to vary the temperature during the activation.

(37) FIG. 8 illustrates by way of example a temperature profile during the growth of the semiconductor layers for the semiconductor chip illustrated in FIGS. 7 and 9. A temperature of at least approximately 750° C. and at most approximately 950° C. or approximately 970° C. prevails during the epitaxial growth of the semiconductor layers.

(38) The activation of the p-doped regions of grown semiconductor layers is effected during a time period 8. During said time period 8, the temperature is reduced, starting from approximately 800° C., to approximately 500° C. and is subsequently increased again to approximately 800° C. The increasing and reducing of the temperature are effected continuously, for example. They can also be effected in stepwise fashion. As an alternative, the temperature can also remain constant at least during part of the time period 8. After the time period 8, epitaxial growth of semiconductor layers is continued.

(39) As an alternative, it is also possible to carry out the activation step only after the conclusion of the epitaxial growth. This is preferably the case when the covering layer 3 is intended to be formed with a current spreading layer with TCO. The activation is then effected before the formation of the current spreading layer with TCO.

(40) The epitaxial growth of the n-doped semiconductor layer is effected e.g. by means of molecular beam epitaxy (MBE). This is an epitaxy method in which generally no free hydrogen radicals are contained in the growth atmosphere. MBE methods for growing nitride semiconductor materials are known to the person skilled in the art.

(41) As an alternative, forming the n-doped semiconductor layer 32 comprises metal organic vapor phase epitaxy (MOVPE), e.g. the n-doped semiconductor layer 32 is grown epitaxially by means of MOVPE. For this purpose, e.g. dimethylhydrazine is advantageously used as a nitrogen source. This produces essentially no free hydrogen radicals during the growth. Free hydrogen radicals should be avoided since they are suitable for at least partly reversing the activation of the p-doped regions.

(42) The semiconductor chip 1 illustrated in incomplete form in FIG. 7 is represented schematically in a completed form in FIG. 9. After the activation step, the n-doped semiconductor layer 32 is formed further up to a thickness of, for example, approximately 120 nm. As an alternative, the n-doped layer 32 is formed with a thickness of 300 nm or more.

(43) An n.sup.+-doped semiconductor layer 33 is disposed downstream of the n-doped semiconductor layer 32 in growth direction 7. Said semiconductor layer 33 has a significantly higher dopant concentration than the n-doped semiconductor layer 32. By way of example, the doping concentration for the n.sup.+-doped semiconductor layer 33 is at least 10.sup.20 cm.sup.−3. The n.sup.+-doped semiconductor layer 33 has a thickness of 5 nm, for example.

(44) The n-doped semiconductor layer 5, the p-doped semiconductor layer 21 and the n-doped semiconductor layer 32 are for example all based on GaN or essentially comprise GaN. The n.sup.+-doped semiconductor layer 33 is based for example on InGaN or essentially comprises a material of this type. It goes without saying that suitable dopants are implemented in each case. Silicon, for example, is suitable as an n-type dopant, and magnesium, for example, is suitable as a p-type dopant.

(45) The p-doped semiconductor layer 21 preferably has a thickness of between 50 nm and 500 nm; by way of example, the thickness is approximately 100 nm. The p-doped semiconductor layer 21 serves as a p-type barrier layer for the active region of the active layer 4.

(46) A tunnel contact 51 succeeds the n-conducting semiconductor layer 5 as seen in growth direction 7. The tunnel contact 51 is preferably a highly doped n-p tunnel junction. In this case, the n-doped side of the tunnel contact 51 faces the n-conducting semiconductor layer 5. The p-doped side is remote from the n-conducting semiconductor layer 5. On its side facing the n-conducting semiconductor layer 5, the tunnel contact 51 comprises a highly n-doped In.sub.yGa.sub.1-x-yAl.sub.xN layer where 0≦x≦1, 0≦y≦1 and x+y≦1 or an n-doped In.sub.yGa.sub.1-x-yAl.sub.xN superlattice where 0≦x≦1, 0≦y≦1 and x+y≦1. Silicon, for example, is suitable as an n-type dopant. The doping concentration is preferably at least 10.sup.19, particularly preferably at least 10.sup.20. The highly n-doped layer is preferably at most 20 nm thick.

(47) On the side remote from the n-conducting semiconductor layer 5, the tunnel contact 51 comprises for example a highly p-doped In.sub.yGa.sub.1-x-yAl.sub.xN layer where 0≦x≦1, 0≦y≦1 and x+y≦1 or a highly p-doped In.sub.yGa.sub.1-x-yAl.sub.xN superlattice where 0≦x≦1, 0≦y≦1 and x+y≦1. A possible p-type dopant is magnesium in this case. The doping concentration is preferably at least 10.sup.19, particularly preferably at least 10.sup.20. The highly p-doped layer is preferably at most 20 nm thick.

(48) In this exemplary embodiment, preferably, an n-conducting substrate serves as growth substrate 6. Possible n-conducting substrates are in this case: n-GaN, n-SiC, n-Si(111). However, it is also possible for an electrically nonconductive substrate such as sapphire, for example, to be used.

(49) In this case, the growth substrate 6 can have a slight disorientation, which can prove to be advantageous with regard to the crystal quality of the growing layers. The disorientation of the growth substrate 6 is preferably between 0.2° and 0.5°, for example 0.3°. Such a disorientation can lead to significantly smoother layers with reduced island growth and reduced roughness. The roughness of the growing layers can therefore be significantly reduced.

(50) A buffer layer 61 follows the growth substrate 6 as seen in growth direction 7. Said buffer layer is based on a suitable nitride semiconductor material, for example AlN.

(51) FIG. 10 plots the forward voltage for various semiconductor chips which are essentially constructed like the semiconductor chip 1 described previously with reference to FIG. 1. The forward voltage U.sub.f is plotted as a function of the thickness d of the nominally undoped spacer layer 31. It was measured with an electric current of approximately 20 mA being applied to the semiconductor chips. Referring to FIG. 1, during the measurements use was made of semiconductor chips whose n-doped semiconductor layer 32 is highly doped, that is to say that it has a doping concentration of more than 10.sup.19 cm.sup.−3. In the case of the semiconductor chips, the activation step for activating the p-doped regions was not carried out until after all the semiconductor layers had been completely formed.

(52) In the case of the three measurement results 91 arranged along the straight line, the n-doped semiconductor layer has a thickness of approximately 5 nm. It is evident that the resulting forward voltage U.sub.f depends linearly on the thickness of the spacer layer 31. In the case of the semiconductor chip whose measurement produced the measurement point 92, the activation step was carried out before the formation of the n-doped semiconductor layer 32. It was surprisingly possible to establish that, by means of this measure, the forward voltage U.sub.f can be significantly reduced compared with the other semiconductor chips. Although the nominally undoped spacer layer 31 had a thickness of approximately 15 nm when carrying out the activation step, a forward voltage U.sub.f of less than 4.5V could be realized overall.

(53) FIG. 11 likewise illustrates measurement results from the measurement of semiconductor chips of the type as illustrated in FIG. 1. The resulting forward voltage U.sub.f is plotted as a function of the thickness of the n-doped semiconductor layer 32. The activation step was effected in each case only after the n-doped semiconductor layer 32 had been completely formed.

(54) It can be discerned that the resulting forward voltage U.sub.f, up to thicknesses of approximately 40 nm, is very greatly dependent on the thickness of the n-doped semiconductor layer 32. If, during the activation step, an n-conducting semiconductor layer 32 having a thickness of approximately 40 nm is formed in the covering layer, the resulting forward voltage U.sub.f is more than 8 V. Such a high forward voltage U.sub.f is disadvantageous for commercial applications.

(55) FIG. 12 illustrates the results of measurements similar to those in FIG. 11. One difference is that the measurements are carried out on semiconductor chips 1 embodied in the manner as described previously with reference to FIG. 2. In FIG. 12, too, it can be discerned that the resulting forward voltage U.sub.f is greatly dependent on the thickness of the n-doped semiconductor layer 32 which was present during the activation step.

(56) By contrast, forward voltages of less than 4.5 V, preferably of less than 4 V can be realized with the method described.

(57) In one embodiment, the semiconductor chip generally has in order: a first n-doped layer, a p-doped layer, an active layer with active zone, a second n-doped layer. In each case even further layers can be arranged between the layers specified and also before or after the outer layers. The respective layers can also be composed in each case of a plurality of sub layers. The semiconductor section with a p-doped region comprises the p-doped layer. The active layer can contain for example n-type dopants and/or p-type dopants e.g. Si and/or Mg. Either the first or the second n-doped layer is disposed downstream of the p-doped layer in the growth direction and thus part of the covering layer.

(58) The first n-doped layer has, for example, a thickness of greater than or equal to 100 nm, but the thickness can also be smaller in other embodiments. The n-doped layer can also be a TCO layer. The p-doped layer has for example a thickness of greater than or equal to 50 nm.

(59) The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.