Display systems

Abstract

We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.

Claims

1. A method of reducing artefacts in an image displayed by an active matrix non-volatile electro-optic display and non-volatile electro-optic display driver, the non-volatile electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the non-volatile electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the non-volatile electro-optic display driver, pixels of the non-volatile electro-optic display having a common pixel electrode, the method comprising: disconnecting said common pixel electrode from a common pixel electrode power supply such that said common pixel electrode is floating; controlling a common backplane power supply to clamp said common backplane connection to a first defined voltage level, wherein said first defined voltage level is a zero volts level; and after said disconnecting and said controlling, driving the non-volatile electro-optic display with a null frame during a power-down procedure of the display, wherein the non-volatile electro-optic display is driven with the null frame whilst the common pixel electrode is floating and the common backplane connection is clamped to the first defined voltage level, and wherein said null frame comprises a frame of data values defining no change in a displayed colour or brightness level.

2. A method as claimed in claim 1 wherein each active matrix pixel driver comprises a driver transistor, coupled to said storage capacitor and having a control input coupled to a pixel select line, the method further comprising clamping said pixel select lines of said active matrix pixel drivers to a second defined voltage level prior to said driving with said null frame.

3. A method as claimed in claim 2 further comprising clamping one or both of said common backplane connection and a said pixel select line to a third defined voltage level, lower than at least one of said first and second voltage levels, subsequent to said clamping to said respective first or second defined voltage level; and wherein said second defined voltage level is a zero volts level.

4. A method as claimed in claim 1 wherein, after said driving with a null frame, a voltage level on said common pixel electrodes changes towards that of a background colour of said non-volatile electro-optic display.

5. A method as claimed in claim 1 wherein each active matrix pixel driver comprises a driver transistor, coupled to said storage capacitor and having a control input coupled to a pixel select line, and wherein said driving with a null frame comprises selecting a plurality of said pixel select lines simultaneously; and where alternate ones of said pixel select lines are selected simultaneously.

6. A method as claimed in claim 1 further comprising driving said non-volatile electro-optic display with a second null frame.

7. A method as claimed in claim 1 further comprising using a power-up procedure to compensate for a tendency of said non-volatile electro-optic display to change away from a background colour during repeated null frame driving; and displaying a preconditioning null frame during said power up procedure.

8. A method as recited in claim 1 wherein said active matrix pixel drivers of said non-volatile electro-optic display driver comprise organic or solution-processed thin film transistors; and wherein said non-volatile electro-optic display is an electrophoretic display.

9. An active matrix non-volatile electro-optic display driver, the non-volatile electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the non-volatile electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the non-volatile electro-optic display driver, pixels of the non-volatile electro-optic display having a common pixel electrode, the non-volatile electro-optic display driver further comprising a system to disconnect said common pixel electrode from a common pixel electrode power supply such that said common pixel electrode is floating; control a common backplane power supply to clamp said common backplane connection to a first defined voltage level, wherein said first defined voltage level is a zero volts level; and after said disconnect and said control, drive the non-volatile electro-optic display with a null frame during a power-down procedure of the display, wherein the non-volatile electro-optic display is driven with the null frame whilst the common pixel electrode is floating and the common backplane connection is clamped to the first defined voltage level, and wherein said null frame comprises a frame of data values defining no change in a displayed colour or brightness level.

10. A display driver as recited in claim 9 wherein said active matrix pixel drivers of said non-volatile electro-optic display driver comprise organic or solution-processed thin film transistors; and wherein said non-volatile electro-optic display is an electrophoretic display.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying figures in which:

(2) FIGS. 1a and 1b show, respectively, a vertical cross-section (along a staggered line) through a portion of an active matrix backplane showing a second example active matrix pixel driver circuit including a multi-layer transistor structure and pixel capacitor, with an off-set the top pixel electrode configuration for reduced kickback, and the structure of FIG. 1a from above;

(3) FIG. 2 shows an example of a pixel driver circuit on a flexible plastic backplane, in combination with a pixel of an electrophoretic display;

(4) FIG. 3 shows a block diagram of an electronic device including an active matrix electro-optic display and driver;

(5) FIG. 4 shows examples of non-leaky and leaky pixel driver circuits illustrating the effect of a leaky pixel on the voltage applied to the electro-optic display media;

(6) FIG. 5 shows variation of the TPCOM (pixel plane common electrode) voltage of FIG. 4 during power-up display update, and power-down, illustrating a negative voltage tail;

(7) FIG. 6 illustrates darkening of display edges due to a combination of the negative voltage tail and the presence of leaky pixels;

(8) FIG. 7 shows a block diagram of an electro-optic display and driver configured to implement a modified power-down procedure to reduce the negative voltage tail FIG. 5;

(9) FIG. 8 illustrates a variation of the TPCOM voltage during power-up, display update, and power-down when employing the modified power-down procedure, illustrating a positive voltage tail;

(10) FIG. 9 illustrates the appearance of the display after power-down using the modified power-down procedure;

(11) FIG. 10 illustrates an addressing scheme for rapid implementation of the modified power-down procedure; and

(12) FIG. 11 shows curves of voltage against time for TPCOM, a backplane common voltage (BPCOM) and a positive gateline supply (VGPOS) illustrating partial clamping of BPCOM before display of a null frame in a further modified power-down/power-up procedure for the display/driver combination of FIG. 7.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(13) Referring to FIG. 2, this shows an example of a pixel driver circuit 500 fabricated using solution deposition techniques on a flexible plastic backplane, in combination with a pixel 550 of an electrophoretic display. In FIG. 2 the portion to the right hand of the dashed line constitutes the electrophoretic display and the portion to the left side of the dashed line, the active matrix backplane; these are sandwiched together to make an active matrix display.

(14) The pixel driver circuit of FIG. 2 comprises a thin film transistor 502 having a gate connection 504 which is connected to a pixel select line of the display. When activated a voltage on pixel data (VDAT) line 506 is coupled to one plate of storage capacitor Cst 508, the other plate of which is connected to a backplane common connection 510. The junction between transistor 502 and storage capacitor 508 also provides a pixel drive line 512 which is connected to the electrophoretic display pixel 550. Pixel 550 may be modelled as a high value resistor, for example of order 800MΩ, in parallel with a small capacitor, for example less than 1 pF. A second connection of the electrophoretic display pixel is connected to the common or top pixel electrode, TPCOM 552.

(15) In operation, when the pixel select line 504 is activated the voltage on line 506 is applied between the pixel drive line 512 and TPCOM 552, and is also stored on capacitor 508. A typical voltage range for line 506 is between −16 volts (white) and +16 volts (black). FIG. 2 illustrates an example gate drive waveform on the pixel select line going between +28 volts and −42 volts, that is approximately a 70 volt swing. When the gate voltage returns from its negative value to its positive value, deselecting transistor 502, parasitic capacitance illustrated by capacitor 514 couples a proportion of this voltage to the pixel drive line 512. For organic/solution-deposited devices on a plastic substrate the parasitic capacitance is relatively large and a (gate kickback) voltage of order 10 volts may be coupled to the pixel drive line. This is a substantial proportion of the black-white voltage range.

(16) When driving an electrophoretic display pixel, because of the relatively slow response of such displays a single pixel may be written to perhaps every 20-30 ms, to maintain a drive to the pixel. In a practical device there is some leakage due to resistance between the TPCOM plane 552 and one or both of the gate voltage power supplies (this leakage resistance is not shown in FIG. 2). Also, in general, the TPCOM plane 552 will be coupled, at least indirectly to the backplane 510.

(17) Due to the relatively slow update rate of an electrophoretic display to speed the display up only a small region of the display may be updated: Often, for example when typing, only a small region of the display changes. The remainder of the display is written with a null frame, that is with a voltage on line 506 of zero volts, which for an electrophoretic display corresponds to no-change in the displayed “colour”. However if the voltage actually experienced by the pixel is not zero, there is a gradual drift towards either black or white. The visibility of such drift imposes tight constraints on accurately controlling the pixel voltage. The difficulty of this is exacerbated in electronic paper displays with plastic backplanes because the characteristics of the display and the performance of the driver circuitry also depend upon temperature, ageing, humidity and the like.

(18) FIG. 3 shows a block diagram of an example electronic device, here an electronic document reader 1000, including an active matrix electro-optic display and driver, in this example including a gate kickback voltage adjustment system 1020.

(19) The electronic document reader 1000 comprises a controller 1002 including a processor, working memory and programme memory, coupled to a user interface 1004. The controller 1002 is also coupled to an active matrix backplane and electrophoretic display 1007 by a display interface 1006, to send electronic document data to the display and, optionally, to receive touch-sense data from the display (where a touch sensor is provided for the display). The control electronics also includes non-volatile memory 1008, for example Flash memory, for storing data for one or more documents for display and, optionally, other data such as user bookmark locations and the like. An external wired or wireless interface 1010, for example USB and/or Bluetooth™, is provided for interfacing with a computer such as a laptop 1014, PDA, or mobile or ‘smart’ phone to receive document data and, optionally, to provide data such as user bookmark data. A rechargeable battery 1012 or other rechargeable power source is connected to interface 1010 for recharging, and provides a power supply to the control electronics and display.

(20) The power supply to the display/interface system 1018 (shown enclosed by a dashed line) includes positive and negative gate voltage supplies Vg POS, Vg NEG and a Common Voltage supply Vcom. In FIG. 3 Vg POS and Vg NEG are provided by respective gate voltage power supplies 1022, 1024. In embodiments the difference between Vg POS and Vg NEG, Vgswing, can be relatively large, for example ˜70 volts. The gate kickback voltage adjustment system 1020 comprises a digital-to-analogue converter (DAC) 1026 with an output driving a buffer 1028 which in turn provides voltage V(TPCOM) 552 to display/interface system 1018. The DAC 1026 has a digital input 1026b, for example from controller 1002, and a reference input 1026a and is configured to generate an output voltage which depends on the digital input value scaled by a signal level (voltage) on the reference input 1026a.

(21) The digital input may be set by controller 1002 at an approximately correct value and then adjusted by adjusting the voltage (or current) on the reference input 1026a. In some embodiments this adjustment may be calculated or, alternatively, it may be set at manufacture (of the display or e-reader), by adjusting one or both of the digital input value and the reference level to optimise the visual appearance of the display or to minimise (or null) a measured gate kickback voltage. In embodiments the value of the digital input and/or reference determined in this way may be stored in the non-volatile memory 1008. In an example embodiment the DAC reference level was ˜1 volt and the value of Vcom was ˜10.5 volts.

(22) Suppression of Spurious Display Effects

(23) During power-down of the backplane voltage supplies, care must be taken not to drive the electro-optical media in a manner which would result in degradation or corruption of the displayed image. This is particularly important when pixels of the electro-optical media are driven by organic TFTs rather than amorphous silicon TFTs, due to the higher voltages employed for driving. Capacitive couplings of the gatelines and the backplane common electrode (BPCOM) with the pixel electrodes are considerably higher with organic TFTs, with a consequent greater risk of driving the media. In the previous example the display medium is a voltage driven display medium that gets darker when a positive voltage is applied to the pixel electrode (preferenced to TPCOM) on the backplane.

(24) To address this, at the end of an update of the display, and before power-down, that is when the voltage across the display media is zero volts, the top plane common electrode (TPCOM) may be electrically disconnected from its voltage supply by means of an electrical switch, for example a MOSFET, TPCOM switch 554 in FIG. 4. This enables the voltage of TPCOM to freely track the voltage of the pixel electrodes during power-down without causing a substantial potential difference to appear across the media.

(25) FIG. 4 shows a pair of active matrix pixel driver circuits 500a, b, each of the type shown in FIG. 2 (and in which like elements are indicated by like reference numerals). Active matrix pixel 500b is leaky as compared with pixel 500a and shows three different types of leakage resistance which may be present, Rsd 556 representing source-drain leakage across the driver transistor, Rgd 558 representing gate-drain leakage through the driver transistor and Rst 560 representing leakage through storage capacitor 508. In the illustrated example the pixel electrode of the normal pixel 500a is at a voltage V.sub.1 of approximately −5 volts and TPCOM is at approximately the same voltage so that there is a null drive on this pixel. However leaky pixel 500b has a pixel electrode at a voltage V.sub.2 of approximately zero volts due to leakage through one or more of Rsd, Rgd and Rst, and thus the pixel electrode is positive with respect to TPCOM and the media is driven towards the black. This is a problem since the image background is typically white. The ringed portions of FIG. 6 illustrate this problem, in particular the darkening of the display edge after power-down of the display, due to high leakage pixels around edges of the display.

(26) FIG. 5 shows an example oscilloscope trace 570 of the voltage on the top plane common electrode TPCOM (line 552a of FIG. 4) from power-up 572a, through a display update 572b, to power down 572c with an unmodified drive scheme. During the update 572b, TPCOM is driven to a set voltage, in this example 10 volts. On power-down, the capacitive coupling to the gatelines, in combination with BPCOM being clamped to zero volts, causes the pixel electrodes to see a negative voltage, with a voltage variation given by, approximately:

(27) $\Delta V_{\mathrm{pixel}}=\Delta V_{\mathrm{gate}}\frac{C_{\mathrm{gd}}}{C_{\mathrm{gd}}+C_{\mathrm{st}}}+\Delta V_{\mathrm{BPCOM}}\frac{C_{\mathrm{st}}}{C_{\mathrm{gd}}+C_{\mathrm{st}}}$

(28) The TPCOM voltage is an average determined by coupling from the individual pixel electrodes.

(29) In an a-Si backplane the BPCOM voltage may be kept at 0V. However embodiments of the display driver implemented using a solution-deposited/organic backplane hold BPCOM at a voltage different to 0V, in embodiments a voltage substantially equal to the TPCOM voltage. This suppresses a parasitic TFT in the particular stack employed and improves display uniformity (in particular Black NFD uniformity). Therefore in embodiments of the display driver BPCOM is clamped at the end of the update, and this (also) contributes to the appearance of a negative voltage on the pixel electrodes, which causes the blackening of the leaky pixels.

(30) Ideally the voltages of the pixel electrodes, V.sub.1 and V.sub.2 in FIG. 4, should always be the same during power-down. Since the gatelines and BPCOM are driven in parallel, this ideal should be achieved if the individual pixels/drivers are identical. However in practice due to a range of reasons such as light exposure, heat exposure, bias stress, and pixel defects, some pixel electrodes may become leaky during the operation and lifetime of the product: thus the leakage resistance between a pixel electrode and its data line and/or BPCOM and/or its dateline can reduce and, in general, this effect will be non-uniform across pixels. A leaky pixel or region of leaky pixels will have a more positive voltage across the display media, that is the pixel electrode voltage will be closer to zero volts because of the increased leakage to the datalines, gatelines or BPCOM as compared with normal, non-leaky pixels. Curve 574 of FIG. 5 illustrates, schematically, the potential difference between high leakage peak pixels (curve 574) and standard pixels (curve 570). The effect of the leakage is to cause the leaky pixels to drive the media towards black at power-down, and this tends to be readily visible on a white background, as shown in FIG. 6.

(31) In embodiments of the invention we address the above problem by driving a null frame after (i) TPCOM is disconnected from its voltage supply by switch 554; and (ii) the gatelines and BPCOM are clamped to zero volts. (As described later, however, optionally the clamping to zero volts may be performed only after the null frame). The result of this procedure is that the voltage of non-leaky pixel electrodes is pushed back positive, together with the TPCOM voltage. (Referring to voltages in FIG. 4, the non-leaky pixel electrodes are pulled towards zero volts which, in turn, pulls TPCOM towards zero volts, that is in a positive direction). The effect of this is shown in the TPCOM trace 580 of FIG. 8, which shows that following driving this null frame the TPCOM voltage exhibits a positive tail 580a, which drives the leaky pixels towards white. In embodiments the TPCOM voltage need not be driven positive since there is benefit in merely reducing the negative voltage tail of TPCOM shown in FIG. 5 to bring TPCOM closer to zero volts. However because the image background is typically white, a slightly positive voltage tail is also acceptable: because of the white background of typical images, no noticeable difference is visible after power-down, making this an effective procedure for suppressing the dark image regions due to high leakage pixels. FIG. 9 shows the same display as FIG. 6, but employing this modified power-down procedure. As can be seen, the dark pixels around the edges of the display are no longer present.

(32) In embodiments of the modified procedure, because of the dielectric absorption or remnant voltage of the media, the TPCOM voltage and the pixel voltage(s) may differ (the difference decaying to zero volts during power-down), but nonetheless the aforementioned advantages are still provided.

(33) Referring now to FIG. 7 this shows a block diagram of an electro-optic display and driver configured to implement an embodiment of the above described power-down procedure. (The system of FIG. 7 may also be employed to implement a modified power-up procedure as described later, additionally or alternatively to the power-down procedure). Like elements to those previously described with reference to FIG. 3 are indicated by like reference numerals; a gate kickback compensation system will also generally be present but is not shown, for clarity.

(34) Thus the device 1100 of FIG. 7 incorporates a TPCOM supply 552 as previously described together with a TPCOM switch 554, and a BPCOM supply 510. A controller controls switch 554 and also BPCOM supply 510 in order to be able to clamp the BPCOM supply to zero volts. In FIG. 7 the gate (select) and datalines are shown explicitly, and the controller 1102 provides a further control output to the display interface 1006 to clamp the gate (select) lines. In embodiments a further BPCOM reference supply 1104 is provided, again under control of controller 1102, to implement a further modified power-down/power-up procedure in which there is partial clamping of BPCOM before the null frame.

(35) Since the TPCOM voltage increases during the null frame drive the pixels corresponding to the first gatelines to be addressed are driven more (blacker) than the pixels corresponding to the last gatelines to be addressed. The faster the media response, the more evident this fade effect is. The fade affect can be addressed and, in embodiments partially or wholly suppressed by increasing the speed of the null frame, thus reducing the time for the electrical unbalance across the panel to affect the optical state of the display. One approach to increasing the speed of display of the null frame is to address (select) multiple gate lines simultaneously rather than, one at a time. When doing this the number of lines driven simultaneously may be selected so as not to exceed the current limit of the gatedrive circuitry. Where an offset top pixel arrangement is employed, for example as described in US2011/0101361 (incorporated by reference), the datelines should be addressed in the same direction (overlap direction) as normal and preferably in a “combed” sequence where adjacent gatelines are not selected simultaneously. FIG. 10 shows an example set of dateline drive waveforms for such a combed sequence in which 12 lines are addressed at the same time to perform a fast null (in FIG. 10 a low state of a gateline corresponds to the gate (transistor) being open). if such a procedure is not employed then the TPCOM voltage can increase too much and turn on the drive TFT.

(36) We have described embodiments of a modified power-down procedure for a combination of an electro-optic display and flexible organic TFT backplane. However similar techniques can be employed when powering-up a display/backplane combination. In particular driving a preconditioning null frame in a substantially similar manner. The skilled person will appreciate that the arrangement of FIG. 7 may similarly, therefore, be employed to implement such approaches.

(37) If the TPCOM voltage is too high at the end of the power-down sequence, during the next power-up, when capacity of couplings to gatelines and BPCOM take the pixel electrodes and TPCOM to a more positive voltage, the TPCOM voltage can exceed the voltage range of switch 554 which keeps the TPCOM electrode disconnected from its voltage supply. In the circumstances the TPCOM voltage may be clipped to the maximum voltage of the TPCOM switch while the voltage of the pixel electrodes is still free to increase according to the capacity of coupling with the gatelines and BPCOM, and thus the display can then be driven towards the black. Although this is not a problem when an update follows power-up, this can be a problem during repeated null frame drive, for example during a keyboard mode for the device where most of the pixels are not updated after power-up (the device may be powered-up at each key stroke). In such a case the cumulative effect of each power-up can darken the displayed image.

(38) This problem can be addressed by clamping BPCOM to a small (reduced) positive voltage before the null frame and clamping BPCOM to zero volts only after the null frame. In this way the TPCOM voltage can be kept closer to zero volts. FIG. 11 illustrates the variation of TPCOM, BPCOM, and (positive) gateline voltage VGPOS in an embodiment of this approach. In the context of the device of FIG. 7 this may be implemented by providing a BPCOM reference voltage level 1104. This strategy provides a further benefit in helping to increase the minimum TPCOM voltage during power-down, relaxing the requirements on the voltage range of the TPCOM switch 554.

(39) A modified power-up sequence may be employed to mitigate spurious display effects caused by the modified power-down sequence, but the fast null frame display during power-up may also be used independently of the modified power-down procedure to address other problems.

(40) During repeated null frame updates where only some pixels are updated it is desirable to employ a rapid preconditioning null frame to suppress the fade effect across a display, for example by driving multiple gatelines together as explained previously. If the TPCOM voltage at the beginning of the preconditioning null frame is higher than the gate kickback voltage the pixels corresponding to the first gatelines to be addressed will be lighter (i.e. there will be a potential fade effect) if the speed of the preconditioning null frame is too low.

(41) Although we have described some preferred embodiments of improved power-down and power-up techniques for an electronic paper display in combination with an organic TFT backplane, there are other techniques which may be employed additionally or independently to mitigate undesired display effects. For example a different technique to address the problem of leaky pixels is to maintain the BPCOM (backplane common) voltage at zero volts, although this can lead to poor updates as parasitic transistors may be turned on.

(42) With reference to FIG. 11, clamping BPCOM (backplane common voltage) from its initial value (10 volts in the Figure) to zero volts only after display of the null frame is also effective. Again referring to FIG. 11, the roles of the VGPOS and BPCOM lines may be exchanged.

(43) In a still further approach which may be employed additionally or alternatively to the above described techniques, the maximum TPCOM voltage may be lowered during power-up by introducing an extra null frame between the enable of VGPOS (or BPCOM) and BPCOM (or VGPOS). That is, whether or not an intermediate reference level is employed for clamping BPCOM or a gateline supply, an additional null frame may be employed between enabling one and the other of these.

(44) Embodiments and Variations of Some Preferred Implementations

(45) To summarise, listed below are steps in some preferred implementations of the above described techniques. The skilled person will recognise that these may be implemented in hardware (for example dedicated circuit(s) or an ASIC) or in software, or in a combination of the two, for example as part of a controller for the active matrix backplane.

(46) Step 1:

(47) The power down sequence is modified by introducing a “post-conditioning” null frame after the clamping of VGPOS and VGNEG to 0V.

(48) TABLE-US-00001 Power down sequence before Step 1: Power down sequence after Step 1: Vbpcom set to 0 V or Vtpcom or Vbpcom set to 0 V or Vtpcom or another voltage during update another voltage during update Float TPCOM Float TPCOM Clamp Vgpos and Vbpcom Clamp Vgpos and Vbpcom Drive 1 null frame Clamp other supplies Clamp other supplies
Step 2:

(49) The speed of the pre-conditioning and post-conditioning null frames can be optimized by addressing multiple gate lines at a time. This helps to suppress display non uniformities caused by the null frame while TPCOM is floating.

(50) The skilled person will appreciate that the potential applications of the techniques in this step are more general: It provides a strategy to update the pixel electrodes faster—with both TPCOM floating or not floating—provided that the pixels addressed in parallel along each source line need to be updated with the same data.

(51) Step 3:

(52) In presence of an off-set top pixel, it is preferable to address the gate lines in a combed sequence and, preferably, in the same direction as when driving of such a backplane without selecting multiple gate lines simultaneously (FIG. 10).

(53) Step 4:

(54) Once introduced the post-conditioning null frame, BPCOM can be clamped after the null frame rather than before. This helps to keep V(TPCOM) closer to 0V (FIG. 11).

(55) TABLE-US-00002 Power down sequence before Step 4: Power down sequence after Step 4: Vbpcom set to 0 V or Vtpcom or Vbpcom set to 0 V or Vtpcom or another voltage during update another voltage during update Float TPCOM Float TPCOM Clamp Vgpos and Vbpcom Clamp Vgpos Drive 1 null frame Drive 1 null frame Clamp BPCOM Clamp other supplies Clamp other supplies
Step 5

(56) Rather than being clamped only after the null frame, BPCOM can be partially clamped to a voltage closer to 0V before the null frame.

(57) TABLE-US-00003 Power down sequence before Step 5: Power down sequence after Step 5: Vbpcom set to 0 V or Vtpcom or Vbpcom set to 0 V or Vtpcom or another voltage during update another voltage during update Float TPCOM Float TPCOM Clamp Vgpos Clamp Vgpos and partially clamp BPCOM to a voltage closer to 0 V Drive 1 null frame Drive 1 null frame Clamp BPCOM Clamp BPCOM Clamp other supplies Clamp other supplies
Step 6

(58) Another way to lower the maximum V(TPCOM) during power up is to introduce an extra null frame between the enable of VGPOS and BPCOM—when the BPCOM voltage is different from 0V during the update.

(59) TABLE-US-00004 Power up sequence before Step 6: Power up sequence after Step 6: Enable all voltage supplies except Enable all voltage supplies except VGPOS VGPOS (connected to gate lines), (connected to gate lines) and VBP_COM VBP_COM (connected to common (connected to common electrode), and electrode), and VTP_COM, with source VTP_COM, with source lines kept at 0 V lines kept at 0 V Open top-plane COM switch to isolate the Open top-plane COM switch to isolate the display top VTP_COM supply. display top VTP_COM supply. Enable HV supplies VGPOS, VTP_COM, Enable HV supplies VGPOS, VTP_COM VBP_COM Write one preconditioning null frame to the display. Enable HV supply VBP_COM Write one preconditioning null frame to Write one preconditioning null frame to the the display display Close the top-plane COM switch Close the top-plane COM switch Write image update data to the display Write image update data to the display system system
Step 7

(60) In steps 4, 5 and 6 above the roles of BPCOM and VGPOS can be exchanged.

(61) Although we have described some example embodiments with reference to a monochrome display the skilled person will appreciate that the techniques are equally applicable to a colour display where, broadly speaking, references to darker/whiter should be taken to refer to a darker/lighter colour.

(62) We have described a pixel driver circuit with p-type transistors but n-type driver transistors may alternatively be employed. Substantially the same considerations apply although the sign of the gate voltages and relative capacitive couplings change. In particular the colour change problem we have described can occur during power-down when the TPCOM voltage goes to negative.

(63) No doubt many other affective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.