Device and method for synchronizing a high frequency power signal and an external reference signal

Abstract

The invention relates to a device for synchronizing a periodic high frequency power signal (18) and an external reference signal (10). The device comprises a phase control circuit (100) and a digital oscillator circuit (130). The digital oscillator circuit (130) is connected to the phase control circuit (100). The digital oscillator circuit (130) comprises means for generating the periodic high frequency power signal (18) dependent on the control signal from the phase control circuit. The phase control circuit (100) is configured to determine a phase difference of the periodic high frequency power signal (18) and the external reference signal (10).

Claims

1. A device for synchronizing a frequency signal (18) and an external reference signal (10), comprising: a phase control circuit (100, 200), a digital oscillator circuit (130, 230), which is connected to the phase control circuit (100, 200), and wherein the digital oscillator circuit (130, 230) comprises means for generating the frequency signal (18) dependent on a control signal from the phase control circuit (100, 200), wherein the phase control circuit (100, 200) is configured to determine a phase difference of the frequency signal (18) and the external reference signal (10), an analog-to-digital converter (120), which is connected to the digital oscillator circuit (130), wherein the analog-to-digital converter (120) comprises an output, which comprises a digital control signal (13), the digital oscillator circuit (130) further comprises a signal processing circuit (140), which is connected to the analog-to-digital converter (120), and wherein the signal processing circuit (140) is configured to regulate a frequency tuning word (15) dependent on a value of the digital control signal (13), wherein the value of the digital control signal (13) is in relation to a preset reference value range of the digital control signal (13), and wherein the phase control circuit (100) comprises a phase detector (100a), which comprises means for determining the phase difference of the frequency signal (18) and the external reference signal (10).

2. The device according to claim 1, wherein the signal processing circuit (140) comprises an activation circuit (145) for activating a frequency tuning word, wherein the activation circuit (145) is activated in case the value of the digital control signal (13) is outside a pre-set reference value range, wherein the pre-set reference value range of the digital control signal (13) is pre-set between 0.1 to 0.9.

3. The device according to claim 2, wherein the pre-set reference value range of the digital control signal (13) is pre-set 0.25 to 0.75 of the pre-set reference value.

4. The device according to claim 1, further comprising a loop filter (110) connected between the phase detector (100a) and the analog-to-digital converter (120).

5. The device according to claim 1: wherein the digital oscillator circuit (130, 230) further comprises a digital-to-analog converter (160, 260), which is connected to the digital oscillator circuit (130, 230), and an output of the digital-to-analog converter (160, 260) has the frequency signal (18).

6. The device according to claim 5, wherein the digital oscillator circuit (130, 230) and the digital-to-analog converter (160, 260) are located on a dedicated chip or are separated.

7. The device according to claim 1, wherein the digital oscillator circuit (130, 230) is a direct digital synthesizer circuit.

8. The device according to claim 1: wherein the generated frequency signal (18) has a frequency equal or smaller than 100 MHz.

9. The device according to claim 8, wherein the generated frequency signal (18) has a frequency between 400 KHz and 100 MHz.

10. The device according to claim 1: wherein the frequency signal (18) is a square-, triangular-, or sinusoidal signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be described below with reference to different exemplary embodiments explained in detail in the following drawings.

(2) FIG. 1a depicts a schematic diagram of an embodiment of the invention;

(3) FIG. 1b depicts schematically a further embodiment of the invention; and

(4) FIG. 2 depicts schematically a further embodiment of the invention.

DETAILED DESCRIPTION OF THE ENABLING EMBODIMENTS

(5) FIG. 1a depicts a schematic diagram of an embodiment of the invention comprising a phase control circuit 100 and a digital oscillator circuit 130. The output of the digital oscillator circuit 130 has a periodic high frequency power signal 18. The digital oscillator circuit 130 is connected to the phase control circuit 100 and comprises means for generating the periodic high frequency power signal 18, which is dependent on the control signal 13 from the phase control circuit 100.

(6) The phase control circuit 100 has one output and two inputs. The output has the control signal 13. One input has an external reference signal 10 and the other input has the periodic high frequency power signal 18. The signal 18 is looped back from the output of the circuit 130. Such a loop is generally called a feedback or control loop or a phase locked loop (PLL).

(7) Generally, a phase locked loop (PLL) is a control loop that synchronizes an oscillator in frequency and phase with an input signal. If the two signals are synchronized, the phase shift between the two is a fixed value. If there is a phase shift between the two signals that does not correspond to the fixed value, the oscillator is re-adjusted until the phase shift again corresponds to this value.

(8) As shown in FIG. 1a the PLL consists of a phase control circuit 100 and a digital oscillator circuit 130. The schematic diagram in FIG. 1a shows how these circuits or elements are connected in order to form a PLL.

(9) FIG. 1b depicts schematically a further embodiment of the invention comprising the phase control circuit 100 and the digital oscillator circuit 130. The phase control circuit 100 comprises a phase detector 100a. The device further comprises an optional loop filter 110 and an analog-to digital converter 120. The digital oscillator circuit 130 comprises a signal processing circuit 140, a direct digital synthesizer circuit 150 and a digital-to analog-converter 160. The schematic diagram in FIG. 1b shows how these elements are connected in order to form a PLL.

(10) The phase detector 100a compares the two input signals 10, 18, for example an external reference signal 10 and a high frequency power signal 18. The signal 18 is generated by the digital oscillator circuit 130 and looped back to one of the inputs of the phase detector 100a.

(11) Based on the comparison of the two signals 10, 18, the phase detector 100a produces an error signal 11. The signal 13 is proportional to the phase difference of the two signals 10, 18. The phase difference is performed by a combination of flip-flop components of the phase detector 100a. Optionally, the error signal 11 can further be low-pass filtered using a so called loop filter 110. The error signal 11 is used to drive the digital oscillator circuit 130, which creates the output signal 18. This output 18 is fed back to one of the inputs of the phase detector, producing a feedback loop or a so called phase locked loop (PLL). As an option, the generated high frequency power signal 18 can be fed back through an optional divider of the phase control circuit 100 (not shown in FIG. 1b).

(12) For example, if the output phase of the generated signal 18 drifts, the error signal 11 will increase, driving the signal 18 of the digital oscillator 130 in the opposite direction so as to reduce the error. Thus, the output phase of the generated high frequency power signal 18 is locked to the phase at the other input signal, which is the reference signal 10.

(13) As shown in FIG. 1b a loop filter 110 or PLL loop filter 110 is connected between the phase detector 100a and the analog-to-digital converter 120. The loop filter optionally can be configured as a low pass filter.

(14) One function of the loop filter 110 is to determine disturbances, such as changes in the reference frequency or phase. Further, when specifying a loop filter the following points should be considered like the range over which the loop can achieve lock (pull-in range, lock range or capture range) or how fast the loop achieves lock time, lock-up time or settling time. Depending on the application, this may require one or more of the following: a simple proportion like gain or attenuation, an integral like a low pass filter and/or a derivative like high pass filter.

(15) The second function of the loop filter 110 is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output, that is then applied to one of the inputs of the oscillator circuit 130.

(16) The analog-to-digital converter 120 (ADC) converts a continuous-time and continuous-amplitude analog signal 12 to a digital control signal 13, which can be discrete-time and/or discrete-amplitude. The conversion involves quantization of the input, which can cause some amount of error or noise. Further, instead of continuously performing the conversion, an ADC 120 optionally converts periodically, sampling the input, limiting the allowable bandwidth of the input signal. The ADC 120 is characterized by its bandwidth and signal-to-noise ratio (SNR). The bandwidth of an ADC is given by its sampling rate.

(17) The direct digital synthesizer circuit 150 generates a periodical signal y(t) 16, which for example is sinusoidal. The circuit 150 comprises two parts. One part is for example an angle counter. This counter generates the angle θy(t) of the signal y(t). It is essentially a counter that counts in the range of 0 to 2π. On each clock cycle, the circuit 150 increments its counter by an amount equal to the value of the loop filter output. That is, θy(t)=θy(t−1)+εloop(t). Thus the loop filter output represents the change in the digital oscillator output's angle and can be written as εloop(t)=Δθy(t).

(18) Once the PLL has converged, the ideal loop filter output will be εloop(t)=Δθy(t)=Δθx=2πfxdΔt where Δt represents the amount of time between samples. In other words, once the PLL has converged, the rate of change of the locally generated angle θy (t) will equal the rate of the change of the received signal angle θx (t).

(19) The circuit 150 comprises as a second part the digital signal generator, which is a sine lookup table that outputs the sine or cosine of its input signal. By connecting the output of the angle counter to the digital signal generator, the circuit 150 is able to generate the output signal y(t)=cos(θy(t)). In practice, the loop filter integrator is often pre-loaded with an estimate of Δθx(t) so that the locally generated signal y(t) starts out near the frequency of x(t).

(20) The DDS circuit 150 as shown in FIG. 1a is a combination of a phase-accumulator with following addition of a phase-offset and a sine-lookup-table (LUT) (not shown in FIG. 1a). The amplitude of the signal can be controlled via a multiplication of a (varying) factor with the output of the sine-LUT.

(21) The digital oscillator circuit 130 further comprises a signal processing circuit 140, which is connected to the digital-to-analog converter 120 and the direct digital synthesizer circuit 150. The signal processing circuit 140 comprises an activation circuit 145 for activating a frequency tuning word 15 (FTW).

(22) The activation circuit 145 comprises logical components 145a, 145b and 145c, which are used for activating a coarse tuning of the frequency tuning word 15. These logical components may include one or more adding components, one or more differentiator components, one or more integrator components, “Tresh & Activate components” or any other logical component or number of logical components.

(23) In case the loop filter 110 clips at GND/VCC the regulation of the frequency tuning word would be inactive. To avoid this effect a certain level or reference value can be specified and also configured or pre-set as a reference value in the ADC 120. If a certain value or level of the reference value at the ADC output is reached an Integrator 145c is activated. This pulls a “coarse FTW” 14b at an adding component 146 to a value in relation to the pre-set reference value so that the tuning of the “fine FTW” 14a can work in a safe area.

(24) The signal processing circuit 140, especially the activation circuit 145, activates a more or less precise tuning dependent on the deviation regarding a preset reference value or reference ADC value or maximum ADC value. The deviation can be specified by a range between a low and a maximum level of the preset reference value or maximum value of the ADC output.

(25) The activation circuit 145 is activated in case the actual value 13 at the output of the ADC or the digital control signal 13 is outside a pre-set range regarding the reference value. For example, if the actual value 13 is below or above this range the coarse tuning is activated by the activation circuit 145. For example, the range can be defined as between 0.1 of the preset reference value or preset maximum ADC value as a first activation level and 0.9 of the preset reference value or preset maximum reference value as a second activation level. Optionally, the range is specified between 0.25 of the preset reference value or preset maximum ADC value as a first activation level and 0.75 of the preset reference value or preset maximum reference value as a second activation level.

(26) The activation of the coarse tuning is dependent on the digital control signal 13 of the ADC 120 or the ADC value 13, which is transmitted from of the analog-to-digital converter 120 to the input of the digital oscillator circuit 130.

(27) Optionally, the device may comprise a divider (not shown), which is usually located in the feedback path of the PLL. As an example, the divider (dividing by 4 or any other natural division factor) can be used to generate a fraction or a multiple of the generated signal 18 or the reference signal 10.

(28) As shown in FIG. 1b the device also comprises a digital-to-analog converter 160. The digital-to-analog converter 160 (DAC) is an element that converts a digital signal into an analog signal, for example a high frequency power signal 18. A DAC 160 converts an abstract number into a physical quantity e.g., a voltage. In particular, DACs are often used to convert finite-precision time series data to a continually varying physical signal.

(29) An ideal DAC converts the abstract numbers into a conceptual sequence of impulses that are then processed by a reconstruction filter using some form of interpolation to fill in data between the impulses. A conventional practical DAC converts the numbers into a piecewise constant function made up of a sequence of rectangular functions that is modeled with the zero-order hold.

(30) FIG. 2 depicts schematically a further embodiment of the invention comprising the phase control circuit 200 and the digital oscillator circuit 230. The phase control circuit 200 comprises a first counter 201 and a second counter 202. The digital oscillator circuit 230 comprises a signal processing circuit 240, a direct digital synthesizer circuit 250 and a digital-to analog-converter 260. The schematic diagram in FIG. 2 shows how these elements are connected in order to form a PLL.

(31) The direct digital synthesizer circuit 250 in FIG. 2 corresponds to the direct digital synthesizer circuit 150 in FIG. 1b. The same applies to the digital-to-analog converter 160, 260 in FIG. 1b and FIG. 2.

(32) The function of the direct digital synthesizer circuit 250 is explained as follows: The circuit 250 comprises a phase accumulator and a sine look up table (LUT) (Both not shown), optionally further or other digital components can be used. The accumulator itself first outputs a number p of the word width P at its output, which corresponds to the current phase of the waveform on the circle. In general, P<N is selected. This is followed by mapping the number p to the desired sample w of the waveform with the word width W. The waveform is digitally stored in a memory with 2P samples. The current value p forms the address for this memory and is thus mapped to the desired waveform. The waveform can be arbitrary, but mostly the sine or cosine form is used.

(33) The resulting sampled values must then be converted to the desired waveform using a digital-to-analog converter 260 of the word width W. Depending on the number (P) and word width (W) of the sampled values, a very pure signal spectrum can be created.

(34) The phase control circuit 200 compares the two input signals 10, 18, for example an external reference signal 10 and a high frequency power signal 18. The signal 18 is generated by the digital oscillator circuit 230 and looped back to one of the inputs of the phase control circuit 200.

(35) Different to the phase control circuit 100 in FIG. 1b the phase control circuit 200 shown in FIG. 2 comprises two counters 201, 202 for comparing the phase difference of the two signals 10, 18. Each counter is configured to count frequency and phase The phase difference is determined by calculating the counting difference of the two counters 201, 202 by using means 241, 242 and 243 of the signal processing circuit 240.

(36) The external reference signal 10 and the looped backed high frequency power signal 18 are fed to the differentiator component 241.

(37) The first counter 201 and the second counter 202 each divide the frequency of the signals by a natural division factor and so each counter allows the generation of fraction/multiples of the input signals.

(38) The differentiator 241 and the flip-flop 243 calculate the actual difference of the two counters 201, 202 at the rising edge of the clock signal selected by the Multiplexer 242. A phase and/or frequency lock is achieved, in case the difference of the two counters 201, 202 is constant.

(39) It should be expressly noted that one subject matter of invention can be advantageously combined with another subject matter of the above aspects of the invention and/or with features shown in the drawings, namely either individually or in any combination cumulatively.

LIST OF REFERENCE SIGNS

(40) 10 External reference signal 11 PWM-signal 13 Digital control signal, ADC value 14a Fine Frequency Tuning Word 14b Coarse Frequency Tuning Word 15 Frequency tuning word 16 Digital signal 17 Clock signal 18 High frequency power signal 19 Output signal (RF Out) 100 Phase control circuit 100a Phase detector 110 Loop filter 120 Analog-to-digital converter 130 Digital oscillator circuit 140 Signal processing circuit 141 Filter component 142 Gain Component 145 Activation circuit 145a Tresh & Activate component 145b Differentiator component 145c Integrator 146 Adding component, Adder 150 Direct digital synthesizer circuit 160 Digital-to-analog converter 200 Phase control circuit 201 First counter 202 Second Counter 240 Signal processing circuit 241 Differentiator 242 Multiplexer 243 Flip-Flop 250 direct digital synthesizer circuit 260 Digital-to-analog converter