Method for reducing influence of remote reference power noise on signal quality

Abstract

A method for reducing influence of a remote reference power noise on signal quality is provided. A remote reference power plane connected to a power module is identified according to a schematic diagram of signal design, and a noised power plane is determined. A position of the noised power plane is found in a PCB, and whether the noised power plane is remote referenced by a high-speed signal is judged. Placement positions and number of connection capacitors are determined according to a layout and routing position of the high-speed signal and a width of the noised power plane. Two capacitors with fixed capacitance values are placed at the placement positions of the connection capacitors. Connection capacitors are added to a position of a noised remote reference power plane of a signal line for connecting the power plane and the ground.

Claims

1. A method for reducing influence of a remote reference power noise on signal quality of a printed circuit board (PCB), the method comprising steps of: providing the PCB comprising at least one power plane connected to a power source and a power chip; identifying a remote reference power plane connected to the power source according to a schematic diagram of signal design, determining a noised power plane, finding a position of the noised power plane in the PCB, and judging whether the noised power plane is remote referenced by a high-speed signal; determining positions and a number of capacitors according to a layout and routing position of the high-speed signal and a width of the noised power plane; and placing two capacitors with fixed capacitance values at the positions of the capacitors, wherein the determining the noised power plane comprises measuring a voltage amplitude or a voltage oscillation where a voltage oscillates in a power plane directly connected to the power chip by an oscilloscope, and wherein the determining of the noise power plane is based on: an oscillating voltage of the voltage oscillation being greater than 10% of a voltage of the power chip, the voltage amplitude jumping and a rising edge rate being greater than 0.3 V/ns, or the voltage oscillation occurring during conversion and an oscillation frequency being between 100 kHz and 1 GHz.

2. The method according to claim 1, wherein the determining the noised power plane is based on the oscillating voltage being greater than 10% of the voltage of the power chip.

3. The method according to claim 1, wherein the determining the noised power plane is based on the voltage amplitude lumping and the rising edge rate being greater than 0.3 V/ns.

4. The method according to claim 1, wherein the determining the positions and the number of capacitors according to the layout and routing position of the high-speed signal and the width of the noised power plane comprises: placing, according to determined positions of a high-speed signal line and a remote reference plane, the capacitors on layer L1 within a range of 80 mils perpendicular to a farthest end of the high-speed signal line, and placing a pair of the capacitors per 300 mils according to the width of the noised power plane, the capacitors being configured to connect the noised power plane and a ground.

5. The method according to claim 4, further comprising: placing the capacitors beside the high-speed signal line, locating the capacitors on the layer L1 for connecting the remote reference power plane and the ground, locating the high-speed signal line on layer L7, locating the ground on layer L6, and locating the remote reference power plane on layer L8.

6. The method according to claim 1, wherein the two capacitors have fixed capacitance values of 0.01 μF and 0.1 μF, respectively.

7. The method according to claim 1, wherein the determining the noised power plane is based on the voltage oscillation occurring during conversion and the oscillation frequency being between 100 kHz and 1 GHz.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a schematic diagram of reducing influence of a remote reference plane in the conventional art.

(2) FIG. 2 illustrates a schematic diagram of signal design according to Embodiment 1 of the present application.

(3) FIG. 3 illustrates a waveform diagram of noise in voltage amplitude jumping in Embodiment 1 of the present application.

(4) FIG. 4 illustrates a schematic diagram of reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application.

(5) FIG. 5 illustrates a schematic diagram of a simulation result for reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application.

(6) FIG. 6 illustrates a flow chart of a method for reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application.

(7) FIG. 7 illustrates a schematic diagram of a system for reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application.

DETAILED DESCRIPTION OF THE INVENTION

(8) The technical solutions in the embodiments of the present application will now be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. It is apparent that the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without involving any inventive effort may fall within the protection scope of the present application.

(9) In the description of the present application, it should be understood that orientation or positional relationships indicated by the terms “longitudinal”, “transverse”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, etc. are orientation or positional relationships shown in the drawings, are merely for convenience in describing the present application, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the present application.

Embodiment 1

(10) Embodiment 1 of the present application proposes a method and system for reducing influence of a remote reference power noise on signal quality. In the method, a remote reference power plane connected to a power module is firstly identified according to a schematic diagram of signal design, a noised power plane is then determined, and a position and name of the noised power plane are recorded. Then, the position of the noised power plane is found in a PCB, and whether the noised power plane is remote referenced by a high-speed signal is judged.

(11) Then, placement positions and number of connection capacitors are judged according to a layout and routing position of the high-speed signal and a width of the noised power plane.

(12) Finally, two capacitors with fixed capacitance values are placed at the placement positions of the connection capacitors.

(13) FIG. 2 illustrates a schematic diagram of signal design according to Embodiment 1 of the present application. A PCB has a power plane with a large voltage, such as 12V and 5V. Power planes directly connected to a power chip are voltage in (VIN), phase and ground (GND) respectively. GND is GND connected to Q2 in the figure. As a power supply switches all the time, there will be some oscillation of voltage around the circle in the figure.

(14) An oscilloscope with a bandwidth of 10 GHz is selected for measurement at a voltage oscillation in the schematic diagram. If an oscillating voltage is greater than 10% of a switch power chip voltage, a noised power plane is determined.

(15) FIG. 3 illustrates a waveform diagram of noise in voltage amplitude jumping in Embodiment 1 of the present application. If a voltage amplitude jumps and a rising edge rate is greater than 0.3 V/ns, a noised power plane is determined. If there is a voltage oscillation during conversion and an oscillation frequency is within a range of 100 kHz to 1 GHz, it is considered that there is noise.

(16) FIG. 4 illustrates a schematic diagram of reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application. A signal layer has a pair of differential signals, the ground is referenced at a near end, power plane 1 is remote referenced, power plane 1 has a large noise, and the remote reference plane also include power planes such as power plane 2 and power plane 3. A connection capacitor is added to a position of the remote reference power plane 1 of a signal line for connecting power plane 1 and the ground. Most of a power noise is filtered out through the connection capacitor, so that the influence thereof on signals is reduced. The connection capacitors are placed beside the high-speed signal line, the connection capacitors are located on layer L1 for connecting the remote reference power plane and the ground, the high-speed signal line is located on layer L7, the ground layer is located on layer L6, and the remote reference power plane is located on layer L8.

(17) The method for judging placement positions and number of connection capacitors according to a layout and routing position of the high-speed signal and a width of the noised power plane includes: placing, according to determined positions of a high-speed signal line and a remote reference plane, in order to ensure the quality of the high-speed signal line, connection capacitors on layer L1 within a range of 80 mils perpendicular to the farthest end of the high-speed signal line, determining placement positions and number according to the layout and routing position of the high-speed signal and the width of the noised power plane, and placing a pair of connection capacitors per 300 mils according to the width of the noised power plane. The connection capacitors are configured to connect the noised power plane and the ground. A pad of the capacitor should be within 80 mils from the furthest reference plane of the signal line to enhance a noise filtering effect. When the distance to the remote reference noise power plane of the signal line is about 1,200 mils, a total of four 300 mils, four pairs of capacitors are placed, and the capacitors are positioned about in the middle of each 300 mil.

(18) FIG. 5 illustrates a schematic diagram of a simulation result for reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application. A solid line A is a waveform of initial design when there is no noise on power plane 1, a dashed line A which deviates more is a waveform when there is a large noise on power plane 1 and a connection capacitor is not added, and a dashed line B which is closer to the solid line is a waveform when there is a large noise on power plane 1 and a connection capacitor is added. It can be seen that the waveform of a signal is greatly improved after the connection capacitor is added, and the influence on the signal quality is greatly reduced.

(19) After the placement positions and number of connection capacitors are determined, a combination of capacitors of 0.01 μF and 0.1 μF is placed fixedly at each position for testing. If the distance between power plane 1 and power plane 2 is very close, power plane 1 has a large noise, but the noise is inevitable due to adjacency. At this moment, it is possible to add capacitors of 0.01 μF and 0.1 μF at the position where power plane 1 and power plane 2 are adjacent, so as to reduce the interference therebetween.

(20) FIG. 6 illustrates a flow chart of a method for reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application.

(21) In step S601, a remote reference power plane connected to a power module is firstly identified according to a schematic diagram of signal design, a noised power plane is determined, and a position and name of the noised power plane are recorded. Then, the position of the noised power plane is found in a PCB, and whether the noised power plane is remote referenced by a high-speed signal is judged.

(22) In step S602, placement positions and number of connection capacitors are judged according to a layout and routing position of the high-speed signal and a width of the noised power plane.

(23) In step S603, two capacitors with fixed capacitance values are placed at the placement positions of the connection capacitors.

(24) Based on the method for reducing the influence of the remote reference power noise on the signal quality proposed by the present application, a system for reducing influence of a remote reference power noise on signal quality is also proposed. FIG. 7 illustrates a schematic diagram of a system for reducing influence of a remote reference power noise on signal quality according to Embodiment 1 of the present application. The system includes an identification and judgment module, a determination module and a placement module.

(25) The identification and judgment module is configured to identify a remote reference power plane connected to a power module according to a schematic diagram of signal design, determine a noised power plane, find a position of the noised power plane in a PCB, and judge whether the noised power plane is remote referenced by a high-speed signal.

(26) The determination module is configured to determine placement positions and number of connection capacitors according to a layout and routing position of the high-speed signal and a width of the noised power plane.

(27) The placement module is configured to place two capacitors with fixed capacitance values at the placement positions of the connection capacitors.

(28) The identification and judgment module includes an identification module and a judgment module.

(29) The identification module is configured to identify a remote reference power plane connected to a power module according to a schematic diagram of signal design, and determine a noised power plane.

(30) The judgment module is configured to find a position of the noised power plane in a PCB, and judge whether the noised power plane is remote referenced by a high-speed signal.

(31) The determination module includes a first determination module and a second determination module.

(32) The first determination module is configured to place, according to determined positions of a high-speed signal line and a remote reference plane, in order to ensure the quality of the high-speed signal line, connection capacitors on layer L1 within a range of 80 mils perpendicular to the farthest end of the high-speed signal line.

(33) The second determination module is configured to place a pair of connection capacitors per 300 mils according to the width of the noised power plane. The connection capacitors are configured to connect the noised power plane and the ground.

(34) The above content is merely an example and description for the structure of the present application. Those skilled in the art make various modifications or additions or similar substitutions to the specific embodiments described, which should all fall within the protection scope of the present application as long as they do not deviate from the structure of the present application or beyond the scope defined by the claims.