Method and a device for measuring parameters of an analog signal

Abstract

A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.D) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D) on the basis of the values of the sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D) and the delays introduced by the delay elements (21, 22, 23).

Claims

1. A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); providing a Field Programmable Gate Array (FPGA) system comprising differential buffers with outputs connected to a number of sequences of delay elements, wherein each of the sequences of delay elements contains a plurality of delay elements, the number of sequences of delay elements corresponding to the number of the preset voltage thresholds; inputting, to an input of each differential buffer, one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.S) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); reading, by means of vector generators, assigned separately to each of the sequences and connected to a common clock signal (CLK), current values of output signals of each of the plurality of the delay elements in the particular sequence at the same moment for all vector generators and providing these values as sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D), each of the sequence output vectors comprising a sequence of values read at the individual outputs of each of the plurality of the delay elements; and for each of the sequences of delay elements, determining a time at which the analog signal (S) crosses the preset voltage threshold on the basis of the values of the sequence output vector for that sequence of delay elements and the delays introduced by each of the plurality of the delay elements of that sequence of delay elements.

2. The method according to claim 1, wherein each of the sequences of delay elements comprises a carry chain of FPGA summator elements.

3. The method according to claim 1, wherein the differential buffers are low voltage differential signal (LVDS) buffers of the FPGA system.

4. A system for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the system comprising: a splitter configured to split the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); a Field Programmable Gate Array (FPGA) system, comprising differential buffers with outputs connected to a number of sequences of delay elements, wherein each of the sequences of delay elements contains a plurality of delay elements, the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); wherein to the input of each buffer there is connected one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.D) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); wherein to each of the sequences there are connected vector generators connected to a common clock signal (CLK); and wherein each of the vector generators is configured to read current values of output signals of each of the plurality of the delay elements in the particular sequence at the same moment for all vector generators and to provide these values as a sequence output vector (W.sub.A, W.sub.B, W.sub.C, W.sub.D), wherein the sequence output vector comprises a sequence of values read at the individual outputs of each of the plurality of the delay elements.

5. The system according to claim 4, wherein each of the sequences of delay elements comprises a carry chain of FPGA summator elements.

6. The system according to claim 4, wherein the differential buffers are low voltage differential signal (LVDS) buffers of the FPGA system.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) Example embodiments are presented on a drawing wherein:

(2) FIG. 1 presents an outline of the system;

(3) FIG. 2 presents an outline of output vector generation;

(4) FIG. 3 presents an outline of the process of combining the temporal parameters from interim signals.

DETAILED DESCRIPTION

(5) The presented solution is based on an FPGA system due to the fact that typical FPGA systems are in a standard way equipped with differential inputs (such as low voltage differential signal (LVDS) buffers) and permit reprogramming of logical connections within the system. The presence of a carry chain facilitating fast communication between neighboring logic cells (chain elements) was also made use of.

(6) The system as presented in FIG. 1 is used for the measurement of analog signal parameters consisting in determination of times at which the analog signal S crosses the preset voltage thresholds. In the presented example embodiment, the system is designed to measure the times at which the signal S crosses four voltage thresholds: V.sub.A, V.sub.B, V.sub.C, V.sub.D.

(7) The measured analog signal S is split in splitter 5 into interim signals S.sub.A, S.sub.B, S.sub.C, S.sub.D in a number corresponding to the number of preset thresholds.

(8) Interim signals S.sub.A, S.sub.B, S.sub.C, S.sub.D are delivered to the FPGA system 10 at the inputs of differential buffers, for example LVDS buffers 11A, 11B, 11C, 11D. Reference voltages V.sub.A, V.sub.B, V.sub.C, V.sub.D are delivered to the remaining inputs of each buffer. Buffer outputs are connected to sequences 20A, 20B, 20C, 20D of delay elements 21, 22, 23. The number of delay elements depends on the configuration of a particular system and is preferably not lower than the ratio of the mean duration of the measured pulse and the delay introduced by a single delay element. Carry chains used in a standard way as summator elements in FPGA systems may be used as the sequences of delay elements, with every chain element in the configuration acting as a delay line.

(9) Vector generators 31A, 31B, 31C, 31D are assigned separately to each of the sequences 20A, 20B, 20C, 20D and connected to a common clock signal CLK. Said generators are designed so as to read the current values of the output signals of each delay element 21, 22, 23 in the particular sequence 20A, 20B, 20C, 20D at the same moment for all generators, as illustrated by means of example in FIG. 2. The readout moment may be determined by a particular slope of the clock signal. In the example embodiment illustrated in FIG. 2, the output signal S.sub.D2 of the delay element 22 is delayed in relation to the output signal S.sub.D1 by the delay value specific to that delay element, while the output signal S.sub.D3 of the delay element 23 is delayed in relation to S.sub.D2 by a multiple of the delay depending on the number of delay elements between elements 22 and 23. When read at the increasing slope of the CLK signal, values of S.sub.D1 and S.sub.D2 are equal to 1 and the value of S.sub.D3 is equal to 0.

(10) Values read at the outputs of individual delay elements 21, 22, 23 are delivered at the generator output as the sequence output vectors W.sub.A, W.sub.B, W.sub.C, W.sub.D—in the example presented in FIG. 2, the sequence output vector would have the value of 11 . . . 0 where “ . . . ” represents values read from the delay elements located between elements 22 and 23.

(11) Knowing the time of occurrence of the increasing slope of the time signal and the delays introduced by individual delay elements, one can calculate the moment at which a particular interim signal is switched with the accuracy equal to the delay introduced by a single delay element.

(12) For instance, if the sequence of delay elements comprises ten elements, the sequence output vector W=1111000000 would imply that the interim signal value is switched from 0 to 1 at the moment corresponding to the moment of measurement minus four times the delay of a single element. Likewise, the sequence output vector W=0001111111 would imply that the interim signal value is switched from 1 to 0 at the moment corresponding to the moment of measurement minus three times the delay of a single element. The value of the delay of a single element is usually much lower than the clock frequency. For instance, in the Lattice ECMP3 FPGA system, the delay introduced by individual elements of the carry chain may be as low as ˜10 ps regardless of the operating frequency of the FPGA system.

(13) Therefore, the system facilitates the measurement of the temporal parameters of each of the interim signals with the accuracy equal to the delay of an individual element. Due to the fact that individual generators are connected to a common clock, the measurements of temporal parameters of the interim signals are perfectly synchronized. It is therefore possible to precisely determine the time course of the entire signal S with the accuracy dependent on the number of preset thresholds and the delay value of a single delay element. An example information being combined from individual threshold values is presented in FIG. 3.

(14) Leading edge or constant fraction discriminators may be designed depending on the preset voltage threshold values and the number of thresholds.

(15) Therefore, the system facilitates very accurate determination of the time courses of pulses generated at converters in TOF-PET scanners.

(16) While the technical solutions presented herein have been depicted, described, and defined with reference to particular preferred embodiment(s), such references and examples of implementation in the foregoing specification do not imply any limitation on the invention. Various modifications and changes may be made thereto without departing from the scope of the technical solutions presented. The presented embodiments are given as example only, and are not exhaustive of the scope of the technical solutions presented herein. Accordingly, the scope of protection is not limited to the preferred embodiments described in the specification, but is only limited by the claims that follow.