Method and apparatus for current sensing and measurement

Abstract

A method and apparatus for current sensing and measurement employs two cascaded MOSFET current mirrors, wherein the mirrored current leaving the first current mirror is fed to the input of the second current mirror. Each current mirror contains a high current MOSFET and a low current MOSFET, connected source-to-source and gate-to-gate. The MOSFETs are matched so that drain-to-source current flowing in the high current MOSFET is proportional to the drain-to-source current flowing in the low current MOSFET. The ratio of high current to low current for each current mirror is M, where M is 100 or less. Voltage biasing networks are employed to maintain constant drain-to-source voltages for both MOSFETs in each current mirror.

Claims

1. A current sensing and measurement apparatus comprising: a first current mirror having an input terminal, a high current output terminal, and a mirrored current output terminal; a second current mirror having an input terminal, a high current output terminal, and a mirrored current output terminal; a third current mirror having an input terminal, a high current output terminal, and a mirrored current output terminal, wherein the first current mirror, the second current mirror, and the third current mirror comprise n MOSFET current mirrors, each of which has a gain M.sub.n, and wherein the mirrored current output terminal of the first current mirror is connected to the input terminal of the second current mirror, and the mirrored current output terminal of the second current mirror is connected to the input terminal of the third current mirror; and a series connection of n−1 MOSFETS coupled to the high current output terminals of adjacent current mirrors, whereby a current I.sub.in to be measured is provided by the n−1.sup.th MOSFET.

2. A current sensing and measurement apparatus as recited in claim 1 wherein, for each adjacent current mirror, a mirrored current output terminal of a current mirror is coupled to an input terminal of a subsequent current mirror.

3. A current sensing and measurement apparatus as recited in claim 2 wherein, to a first order approximation, a gain factor Gn of the n current mirrors is approximately equal to the product of the individual gains Mn of the n current mirrors.

4. A current sensing and measurement apparatus as recited in claim 3 further comprising a regulator MOSFET coupled to a mirrored current output terminal of the n.sup.th current mirror, whereby a mirrored current output I.sub.m is provided.

5. A current sensing and measurement apparatus as recited in claim 3 wherein I.sub.m˜I.sub.in/G.sub.n.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Several example embodiments will now be described with reference to the drawings, wherein like components are provided with like reference numerals. The example embodiments are intended to illustrate, but not to limit, the invention. The drawings include the following figures:

(2) FIG. 1 is a schematic diagram of a typical voltage-based current measurement circuit;

(3) FIG. 2 is a schematic diagram of a typical current-based current measurement circuit incorporating bipolar transistors;

(4) FIG. 3 is a schematic diagram of a prior art current-based measurement circuit incorporating MOSFET technology;

(5) FIG. 4 is a schematic diagram of a current sensing and measurement apparatus incorporating two cascaded MOSFET current mirrors;

(6) FIG. 5 is a schematic diagram of a current sensing and measurement apparatus incorporating “n” cascaded MOSFET current mirrors; and

(7) FIG. 6 is a schematic diagram of a current sensing and measurement apparatus incorporating two cascaded MOSFET current mirrors.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(8) FIGS. 1-3 were discussed with reference to the prior art. FIG. 4 is a schematic diagram of a current sensing and measurement apparatus 400 incorporating two cascaded MOSFET current mirrors 402 and 404.

(9) Current mirror 402 includes a MOSFET 403a and a MOSFET 403b, connected gate-to-gate and source-to-source. Current mirror 402 input terminal is connected to the two source terminals of MOSFET 403a and MOSFET 403b. Current mirror 402 has a high current output terminal connected to the drain connection of high current MOSFET 403b, and a mirrored current output terminal connected to the drain of low current MOSFET 403a. The gain factor M.sub.1 is the ratio of the high current output at the drain of MOSFET 403b to the mirrored current output at the drain of MOSFET 403a. A voltage bias or control may be applied to the common gate connection of MOSFET 403a and MOSFET 403b.

(10) Current mirror 404 includes a MOSFET 405a and a MOSFET 405b. Current mirror 404 input terminal is connected to the source terminals of MOSFET 405a and MOSFET 405b. Current mirror 404 has a high current output terminal connected to the drain connection of high current MOSFET 405b, and a mirrored current output terminal connected to the drain of low current MOSFET 405a. The gain factor M.sub.2 is the ratio of the high current output at the drain of MOSFET 405b to the mirrored current output at the drain of MOSFET 405a. A voltage bias or control may be applied to the common gate connection of MOSFET 405a and MOSFET 405b.

(11) Since the mirrored current leaving current mirror 402 is fed to second current mirror 404, the mirrored current I.sub.m, leaving current mirror 404 will be reduced by approximately the product of both current mirror gains, or about M.sub.1×M.sub.2, compared to the current to be measured (I.sub.in). The gain factor is given by:
I.sub.m=I.sub.in(M.sub.1*M.sub.2+M.sub.1+M.sub.2); typically M.sub.1*M.sub.2>>M.sub.1+M.sub.2

(12) Since both M.sub.1 and M.sub.2 are much less than M for the single stage current mirror of FIG. 3 (for an equivalent overall gain), the accuracies of M.sub.1 and M.sub.2 are significantly better than that of M. As an example, a gain value M of 1000 may typically have a precision of 8-10%. For an overall gain of 1000, the dual stage cascaded current mirrors would require M.sub.1=M.sub.2=√M˜32. At lower M.sub.1 and M.sub.2 values the current measurement accuracy can attain precisions of 1-2% or better.

(13) Returning to FIG. 4, MOSFET 406 provides a current path for the measured current leaving the first current mirror 402. It also maintains a voltage drop across the drain-to-source for MOSFET 405a and MOSFET 405b in the second current mirror 404. MOSFET 408 is part of a regulator that maintains the drain-to-source voltages for MOSFET 405a and MOSFET 405b at the same level and serves a similar function as MOSFET 306 of FIG. 3.

(14) The principles illustrated by the dual stage cascaded current mirrors of FIG. 4 can be extended to any number of additional stages. The actual number of stages one may wish to employ will be determined more by practical matters such as circuit complexity, voltage drop, power dissipation, and diminishing returns with respect to overall current measurement accuracy. However, it may be evident that two stages provide sufficient accuracy for many applications, since there is a significant improvement in measurement accuracy between M factors of 1000 or greater and M factors on the order of 50-100.

(15) FIG. 5 is a schematic diagram of a current sensing and measurement apparatus 500 incorporating “n” cascaded MOSFET current mirrors. A first stage current mirror 502, having a MOSFET 510a and a MOSFET 510b and a current gain factor of M.sub.1, provides its mirror current to second stage current mirror 504. Second stage current mirror 504, incorporating a MOSFET 512a and a MOSFET 512b, has a gain factor of M.sub.2 and provides its mirror current to third stage current mirror 506. Third stage current mirror 506 is composed of MOSFET 514a and MOSFET 514b, having a current gain factor of M.sub.3. The pattern continues to the n.sup.th stage current mirror 508, composed of MOSFET 516a and MOSFET 516b, with a gain factor of M.sub.n. MOSFETs 518, 520, and 522 provide current return paths for measurement currents leaving each of the stages, while also providing voltage regulation to keep the appropriate current mirror drain-to-source voltages at a suitable level. MOSFET 506 serves a similar purpose as MOSFET 408 of FIG. 4. To a first order approximation, the gain factor of all n stages will be approximately the product of all the individual stage gains, so that each stage can provide a relatively low gain for improved overall system accuracy.

(16) FIG. 6 is a schematic diagram of a current sensing and measurement apparatus 600 incorporating two cascaded MOSFET current mirrors and which operates in a similar manner to current sensing and measurement apparatus 400 of FIG. 4. Components of current sensing and measurement apparatus 600 that are analogous to components of current sensing and measurement apparatus 400 will use the same reference numbers and will not be discussed again in detail for the sake of brevity.

(17) Bias regulation of a current mirror 402 of FIG. 6 is provided by an operational amplifier (“op-amp”) 602 and a bias control regulator 610 (which serves as a voltage source). Assuming op-amp 602 is ideal, and V.sub.os1 is zero, op-amp 602 will provide a gate voltage to MOSFET 403a and MOSFET 403b such that the drain voltage of MOSFET 403b (the high current output of current mirror 402) is equal to the bias control voltage from regulator 610 at the inverting input of op-amp 602. For real op-amps, V.sub.os1 will be finite but in the order of a millivolt or less for high quality amplifiers.

(18) Bias regulation of a current mirror 404 of FIG. 6 is provided by an op-amp 606 and a bias control regulator 612. By adjustment of the voltage drop across a MOSFET 406 of FIG. 6, an op-amp 606 maintains the voltage at its non inverting terminal, which is also the drain voltage of a MOSFET 405b in current mirror 404 (the high current output of current mirror 404), equal to the voltage at its inverting terminal (within any error offset voltage V.sub.os3). A voltage at the inverting terminal of op-amp 606 is also the output voltage of bias regulator 612.

(19) In the current sensing and measurement apparatus of FIG. 6, the drain-to-source voltage of the MOSFETs in current mirror 402 is determined by difference between V.sub.cc and the bias voltage from regulator 610, and the drain-to-source voltage of the MOSFETs in current mirror 404 is determined by the difference between the bias voltage from regulator 610 and the bias voltage from regulator 612.

(20) To maintain high current measurement accuracy, it is important to keep the drain-to-source voltages for both MOSFETs in the current mirror at the same potential. The biasing circuits above keep the drain-to-source voltages of the high current MOSFET in each pair fixed (e.g. MOSFET 403b and MOSFET 405b). The remaining two amplifiers keep the drain voltages of both MOSFETs in each mirror at the same potential. The net effect of these two regulation systems is to keep the drain-to-source voltages of each MOSFET in a current mirror regulated at a constant voltage. Op-amp 604 keeps the potential at its inverting input, connected to the drain of MOSFET 403a, equal to (within the error of bias offset voltage V.sub.os2) the voltage of its non-inverting input, connected to the drain of MOSFET 403b. It does so by altering the voltage applied to the gates of the MOSFET 405a and MOSFET 405b in current mirror 404. In like manner, op-amp 608 controls the drain voltages of MOSFET 405a and MOSFET 405b in current mirror 404. The drain of MOSFET 405b is connected to the non-inverting input of op-amp 608, the drain of MOSFET 405a being connected to the inverting input. Op-amp 608 alters the gate voltage of MOSFET 408, which directly impacts the drain voltage of MOSFET 405a until it is equal to the drain voltage of MOSFET 405b. In an example embodiment of the circuitry shown in FIG. 6, M.sub.1=40; M.sub.2=100; total gain is 1/4140; current accuracy is 1% over a dynamic range of 5 decades, from 40 micro-amps to 4 amperes.

(21) Although various embodiments have been described using specific terms and devices, such description is for illustrative purposes only. The words used are words of description rather than of limitation. For example, it is to be understood that the term “MOSFET” is use generically herein to include various types of field effect transistors (FETs), e.g. IGFETs and MISFETs and equivalents thereof. It is to be understood that changes and variations may be made by those of ordinary skill in the art without departing from the spirit or the scope of various inventions supported by the written disclosure and the drawings. In addition, it should be understood that aspects of various other embodiments may be interchanged either in whole or in part. It is therefore intended that the claims be interpreted in accordance with the true spirit and scope of the invention without limitation or estoppel.