Class-E outphasing power amplifier with efficiency and output power enhancement circuits and method

Abstract

An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF drive signal (S.sub.1(t)). A first reactive element (C.sub.A-1) is coupled between the first conductor and a second conductor (30-1). A second reactive element (L.sub.A-1) is coupled between the second conductor and a third conductor (32-1). A second class-E power amplifier (17-1) includes an output coupled to a fourth conductor (31-2) and an input coupled to a second RF drive signal (S.sub.2(t)), a third reactive element (C.sub.A-3) coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load (R). An efficiency enhancement circuit (L.sub.EEC-1) is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits (20-1,2) are coupled to the first and fourth conductors, respectively.

Claims

1. An outphasing amplifier comprising: a first class-E power amplifier having an output at a node where a choke inductor is coupled with a first switching device, the output being coupled to a first conductor and an input coupled to a first RF drive signal, a first reactive circuit element coupled between the first conductor and a second conductor and a second reactive circuit element coupled between the second conductor and a third conductor; and a second class-E power amplifier having an output at a node where a choke inductor is coupled with a second switching device, the output being coupled to a fourth conductor and an input coupled to a second RF drive signal, a third reactive circuit element coupled between the fourth conductor and the second conductor, the third conductor being coupled to a first terminal of a load, outputs of the first and second class-E power amplifiers being combined by means of the first, second, and third reactive elements to produce an output current to the load; and a first efficiency enhancement circuitry directly connected between the first and fourth conductors for causing power efficiency improvement at back-off power levels.

2. The outphasing amplifier of claim 1 wherein the first efficiency enhancement circuitry includes an inductor coupled between the first and fourth conductors.

3. An outphasing amplifier comprising: a first class-E power amplifier having an output at a node where a choke inductor is coupled with a first switching device, the output being coupled to a first conductor and an input coupled to a first RF drive signal, a first reactive circuit element coupled between the first conductor and a second conductor and a second reactive circuit element coupled between the second conductor and a third conductor; and a second class-E power amplifier having an output at a node where a choke inductor is coupled with a second switching device, the output being coupled to a fourth conductor and an input coupled to a second RF drive signal, a third reactive circuit element coupled between the fourth conductor and the second conductor, the third conductor being coupled to a first terminal of a load, outputs of the first and second class-E power amplifiers being combined by means of the first, second, and third reactive elements to produce an output current to the load; and a first power enhancement circuitry coupled between the first conductor and a fifth conductor and second power enhancement circuitry coupled between the fourth conductor and an eighth conductor wherein the power enhancement circuitry is configured to add a third harmonic of the carrier frequency.

4. The outphasing amplifier of claim 3 wherein each of the first power enhancement circuitry and second power enhancement circuitry includes a first inductor and a first capacitor coupled in series.

5. The outphasing amplifier of claim 4, wherein the first inductor and the first capacitor operate to add a harmonic signal to the output of a corresponding class-E power amplifier to shape the output of that class-E power amplifier across all phase angles between the first and second RF drive signals so as to increase the peak output power that can be safely delivered by the outphasing amplifier to the load.

6. The outphasing amplifier of claim 4, wherein at least one of the capacitors is tunable.

7. A method for providing an outphasing power amplifier including a first class-E power amplifier having an output at a node where a choke inductor is coupled with a first switching device, the output being coupled to a first conductor and an input coupled to a first RF drive signal and a second class-E power amplifier having an output at a node where a choke inductor is coupled with a second switching device, the output being coupled to a fourth conductor and an input coupled to a second RF drive signal, the method comprising combining output signals produced by the first and second power amplifiers by: coupling a first reactive circuit element between the first conductor and a second conductor; coupling a second reactive circuit element between the second conductor and a third conductor; and coupling a third reactive circuit element between the fourth conductor and the second conductor, to produce an output current to a load; and coupling first efficiency enhancement circuitry between the first and fourth conductors to cause power efficiency improvement.

8. A method for providing an outphasing power amplifier including a first class-E power amplifier having an output at a node where a choke inductor is coupled with a first switching device, the output being coupled to a first conductor and an input coupled to a first RF drive signal and a second class-E power amplifier having an output at a node where a choke inductor is coupled with a second switching device, the output being coupled to a fourth conductor and an input coupled to a second RF drive signal, the method comprising combining output signals produced by the first and second power amplifiers by: coupling a first reactive circuit element between the first conductor and a second conductor; coupling a second reactive circuit element between the second conductor and a third conductor; and coupling a third reactive circuit element between the fourth conductor and the second conductor, to produce an output current to a load; and coupling first power enhancement circuitry between the first conductor and a fifth conductor and coupling second power enhancement circuitry between the fourth conductor and an eighth conductor to add a harmonic signal to the output of a corresponding class-E power amplifier to shape the output voltage of that class-E power amplifier across all phase angles between the first and second RF drive signals so as to increase the peak output power that can be safely delivered by the outphasing amplifier to the load.

9. The method of claim 8 wherein each of the first power enhancement circuitry and second power enhancement circuitry includes a first inductor and a tunable first capacitor coupled in series, the method including adjusting the tunable first capacitors to adjust the frequency of the harmonic signal.

10. An outphasing amplifier comprising: a first class-E power amplifier having an output coupled to a first conductor and an input coupled to a first RF drive signal and a second class-E power amplifier having an output coupled to a fourth conductor and an input coupled to a second RF drive signal; means for combining output signals produced by the first and second class-E power amplifiers by coupling the first reactive circuit element between the first conductor and a second conductor, coupling a second reactive circuit element between the second conductor and a third conductor, and coupling a third reactive circuit element between the fourth conductor and the second conductor, to produce an output current to a load; means for providing power efficiency improvement outphasing power amplifier at back-off power levels by coupling first efficiency enhancement circuitry between the first and fourth conductors; and means for increasing the peak output power that can be safely delivered by the outphasing amplifier to the load by coupling first power enhancement circuitry between the first conductor and a fifth conductor and coupling second power enhancement circuitry between the fourth conductor and an eighth conductor to add a harmonic signal to the output of a corresponding class-E power amplifier to shape the output voltage of that class-E power amplifier across all phase angles between the first and second RF drive signals so as to reduce a maximum peak drain voltage in the class-E power amplifiers.

11. An outphasing amplifier comprising: a first class-E power amplifier having an output at a node where a choke inductor is coupled with a first switching device, the output being coupled to a first conductor and an input coupled to a first RF drive signal, a first reactive circuit element coupled between the first conductor and a second conductor and a second reactive circuit element coupled between the second conductor and a third conductor; and a second class-E power amplifier having an output at a node where a choke inductor is coupled with a second switching device, the output being coupled to a fourth conductor and an input coupled to a second RF drive signal, a third reactive circuit element coupled between the fourth conductor and the second conductor, the third conductor being coupled to a first terminal of a load, outputs of the first and second class-E power amplifiers being combined by means of the first, second, and third reactive elements to produce an output current to the load; wherein the second reactive element is a capacitor; wherein the first reactive circuit element is an inductor that has an inductance value selected to form a high impedance parallel resonance network with an output capacitance of the first switching device at a frequency of the first RF drive signal; wherein the third reactive circuit element is an inductor that has an inductance value selected to form a high impedance parallel resonance network with an output capacitance of the second switching device at a frequency of the second RF drive signal; and further including a fourth reactive element that is an inductor coupled in series with the second reactive element.

12. A method for providing an outphasing power amplifier including a first class-E power amplifier having an output at a node where a choke inductor is coupled with a first switching device, the output being coupled to a first conductor and an input coupled to a first RF drive signal and a second class-E power amplifier having an output at a node where a choke inductor is coupled with a second switching device, the output being coupled to a fourth conductor and an input coupled to a second RF drive signal, the method comprising combining output signals produced by the first and second power amplifiers by: coupling a first reactive circuit element between the first conductor and a second conductor; coupling a second reactive circuit element between the second conductor and a third conductor; and coupling a third reactive circuit element between the fourth conductor and the second conductor, to produce an output current to a load; wherein the second reactive element is a capacitor; wherein the first reactive circuit element is an inductor that has an inductance value selected to form a high impedance parallel resonance network with an output capacitance of the first switching device at a frequency of the first RF drive signal; wherein the third reactive circuit element is an inductor that has an inductance value selected to form a high impedance parallel resonance network with an output capacitance of the second switching device at a frequency of the second RF drive signal; and further including coupling a fourth reactive element that is an inductor in series with the second reactive element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a schematic drawing of a conventional outphasing amplifier with class E power amplifiers and asymmetric transmission line combiners.

(2) FIG. 1B is a schematic diagram of a conventional class-E switching amplifier.

(3) FIG. 2A is a schematic diagram illustrating a differential class-E outphasing power amplifier having a combiner that includes efficiency enhancement circuitry and a power enhancement circuitry.

(4) FIG. 2B is a schematic diagram of a single-ended outphasing power amplifier which consists of part of the differential implementation shown in FIG. 2A.

(5) FIG. 3 is a schematic diagram of a variation of the differential class-E outphasing power amplifier of FIG. 2A further including cascode transistors, an output transformer, and an output capacitor.

(6) FIG. 4A is a graph illustrating efficiency versus output power for the differential class-E outphasing power amplifier of FIG. 3 with and without the efficiency enhancement circuitry.

(7) FIG. 4B is a graph illustrating switching transistor drain voltage in a class-E outphasing power amplifier with and without power enhancement circuitry.

(8) FIG. 5 is a schematic diagram of another variation of the differential class-E outphasing power amplifier of FIG. 2A wherein the locations of the various “C.sub.A capacitors” and “L.sub.A inductors” have been interchanged.

(9) FIG. 6 is a schematic diagram of another variation of the differential class-E outphasing power amplifier of FIG. 2A.

(10) FIG. 7 is a schematic diagram of another variation of the differential class-E outphasing power amplifier of FIG. 2A.

(11) FIG. 8 is a schematic diagram of a tunable variation of the differential class-E outphasing power amplifier of FIG. 2A.

(12) FIG. 9 is a schematic diagram of another variation of the differential class-E outphasing power amplifier of FIG. 2A.

(13) FIG. 10 is a schematic diagram of another variation of the differential class-E outphasing power amplifier of FIG. 2A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(14) The embodiments of the invention described below provide class-E power amplifier circuits and associated combiner circuits for use in an outphasing transmitter to improve back-off power efficiency and to improve output power levels. This is accomplished by providing passive combining network circuitry along with additional efficiency enhancement circuits and power enhancement circuits.

(15) FIG. 2A shows an outphasing power amplifier 15 that includes four Class-E power amplifiers in which four N-channel switching transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 are driven by RF outphasing signals S.sub.1(t), S.sub.1′(t), S.sub.2(t), and S.sub.2′(t), respectively. RF signals S.sub.1′(t) and S.sub.2′(t) are the complementary or inverse signals of S.sub.1(t) and S.sub.2(t), respectively. RF drive signals S.sub.1(t) and S.sub.2(t) are rectangular, constant-amplitude, phase modulated waveforms that are generated from the amplitude and phase modulated RF signal S(t). Inductors L.sub.C connect the switching transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4, respectively, to the supply voltage V.sub.DD. In a “traditional” class-E power amplifier design (see FIG. 1B), choke inductors having very high values of inductance are used, but in the design of FIG. 2A the inductors L.sub.C may have much smaller inductance. Capacitors C.sub.P-1, C.sub.P-2, C.sub.P-3, and C.sub.P-4 are connected in parallel with the switching transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4, respectively, and represent separate capacitances and/or drain-to-source parasitic capacitances of switching transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4. Capacitors C.sub.A-1, C.sub.A-2,C.sub.A-3, and C.sub.A-4 and inductors L.sub.A-1 and L.sub.A-2 form output matching and signal-combining circuitry tuned for class-E operation at the fundamental carrier frequency of the RF drive signals. Outphasing power amplifier 15 drives a load resistor R.

(16) More specifically, class-E power amplifier 16-1 of outphasing power amplifier 15 in FIG. 2A receives the RF drive signal S.sub.1(t) which is applied to the input of class-E power amplifier 16-1. Class-E power amplifier 16-1 includes an N-channel MOS switching transistor M.sub.1, an inductor L.sub.C, and capacitor C.sub.P-1. (Capacitor C.sub.P-1 can be the output capacitance of class-E power amplifier 16-1 or a parallel combination of the output capacitance of that power amplifier and an external capacitance.) The gate of switching transistor M.sub.1 is coupled to receive RF drive signal S.sub.1(t) through a driver circuit. The source of switching transistor M.sub.1 is connected to ground, and its drain is connected by a conductor 31-1 to one terminal of choke inductor L.sub.C, one terminal of capacitor C.sub.P-1, one terminal of a capacitor C.sub.A-1, one terminal of a power enhancement circuit 20-1, and to one terminal of an efficiency enhancement circuit (such as one including the subsequently described L.sub.EEC or Z.sub.EEC elements). The other terminal of inductor L.sub.C is connected to a power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-1 is connected to conductor 30-1. ePower enhancement circuit 20-1 includes an inductor L.sub.PEC and a capacitor C.sub.PEC connected in series between conductors 31-1 and 31-3. The efficiency enhancement circuit includes an inductor L.sub.EEC-1 connected between conductors 31-1 and 31-2.

(17) Similarly, outphasing power amplifier 15 also receives another RF drive signal S.sub.1′(t) which is the complement of RF drive signal S.sub.1(t). A class-E power amplifier 16-2 includes an N-channel MOS switching transistor M.sub.2, an inductor L.sub.C, and a capacitor C.sub.P-2. The gate of switching transistor M.sub.2 is coupled to receive RF drive signal S.sub.1′(t) through a driver circuit. The source of switching transistor M.sub.2 is connected to ground, and its drain is connected by conductor 31-3 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-2, one terminal of a capacitor C.sub.A-2, one terminal of an efficiency enhancement circuit including inductor L.sub.EEC-2, and to one terminal of power enhancement circuit 20-1. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-2 is connected to conductor 30-2.

(18) Outphasing power amplifier 15 also receives the RF drive signal S.sub.2(t), which is applied to the input of a class-E power amplifier 17-1. Class-E power amplifier 17-1 includes an N-channel MOS switching transistor M.sub.3, an inductor L.sub.C, and a capacitor C.sub.P-3. The gate of switching transistor M.sub.3 is coupled to receive RF drive signal S.sub.2(t) through a driver circuit. The source of switching transistor M.sub.3 is connected to ground, and its drain is connected by a conductor 31-2 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-3, one terminal of a capacitor C.sub.A-3, one terminal of the efficiency enhancement circuit including inductor L.sub.EEC-1, and to one terminal of a power enhancement circuit 20-2. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-3 is connected to conductor 30-1. Power enhancement circuit 20-2 includes an inductor L.sub.PEC and a capacitor C.sub.PEC connected in series between conductors 31-2 and 31-4. The efficiency enhancement circuit including inductor L.sub.EEC-1 thus is connected between conductors 31-1 and 31-2.

(19) Outphasing power amplifier 15 receives yet another RF drive signal S.sub.2′(t), which is applied to the input of a class-E power amplifier 17-2. Class-E power amplifier 17-2 includes an N-channel MOS switching transistor M.sub.4, an inductor L.sub.C, and a capacitor C.sub.P-4. The gate of switching transistor M.sub.4 is coupled to receive RF drive signal S.sub.2′(t) through a driver circuit. The source of switching transistor M.sub.4 is connected to ground, and its drain is connected by conductor 31-4 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-4, one terminal of a capacitor C.sub.A-4, one terminal of an efficiency enhancement circuit, and to the other terminal of power enhancement circuit 20-2. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-4 is connected to conductor 30-2. The efficiency enhancement circuit includes inductor L.sub.EEC-2 which is connected between conductors 31-3 and 31-4.

(20) The inductors L.sub.EEC-1 and L.sub.EEC-2 form the efficiency enhancement circuits and are designed to improve the efficiency of the power amplifier under power back-off conditions, hereinafter referred to as the power amplifier being “at power back-off”. (The power back-off is a conventional way of indicating how much less power a power amplifier is presently delivering to its load compared to the maximum amount of power the power amplifier could safely deliver to the load.) An inductor L.sub.PEC and a capacitor C.sub.PEC form each of power enhancement circuits 20-1 and 20-2 in order to increase the peak output power that outphasing power amplifier 15 can safely supply to the load resistor R without damaging the transistors.

(21) Efficiency Enhancement Circuitry:

(22) The purpose of efficiency enhancement circuits L.sub.EEC-1 and L.sub.EEC-2 is to improve the power efficiency of outphasing power amplifier 15 at power back-off. When the load power is less than the peak power due to applying a value of phase angle θ greater than zero between RF drive signals S.sub.1(t) and S.sub.2(t), the power efficiency of a traditional outphasing power amplifier rapidly falls from its maximum value as θ increases.

(23) It should be understood that the in-phase components of the RF drive signals S.sub.1(t) and S.sub.2(t) contribute to the amount of power being delivered to load resistor R, but the out-of-phase components of RF drive signals S.sub.1(t) and S.sub.2(t) contribute to power dissipation in the circuit, and this results in a reduction in the power efficiency of outphasing power amplifier 15. The in-phase components of RF drive signals S.sub.1(t) and S.sub.2(t) cause the drain voltages of the switching transistors (or associated cascode transistors) connected to the opposite terminals of efficiency enhancement circuit L.sub.EEC-1 or L.sub.EEC-2 to be equal, so no RF current flows through efficiency enhancement circuit L.sub.EEC-1 or L.sub.EEC-2. However, for the out-of-phase components of the RF drive signals S.sub.1(t) and S.sub.2(t) the conductors 30-1 and 30-2 behave like a virtual ground and the L.sub.EEC inductors with the C.sub.P and C.sub.A capacitors form parallel resonant circuits and present very high impedance for the out-of-phase components at the carrier frequency. This high impedance of the parallel resonant circuit reduces the out-of-phase current, and this causes a reduction in the amount of power dissipation due to the out-of-phase current components. Use of efficiency enhancement circuits L.sub.EEC-1 and L.sub.EEC-2 therefore improves the power efficiency of outphasing power amplifier 15 at back-off power levels.

(24) Power Enhancement Circuitry:

(25) Note that the permissible V.sub.DD level applied to the outphasing power amplifier 15 depends on the source-to-drain breakdown voltages of switching transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 (and associated cascode transistors if they are being used), and also note that the permissible V.sub.DD level determines how much the peak load current (and peak power) can be safely delivered to the load resistor R without damaging the switching transistors (or cascode transistors). Consequently, an increase in the peak load current and peak load power cannot be achieved by simply increasing the V.sub.DD level.

(26) The switching on and off of a particular power amplifier switch transistor, e.g., switching transistor M.sub.1, at the fundamental frequency results in a sinusoidal voltage signal at the fundamental frequency on the drain of that switch transistor (or the drain of an associated cascode transistor if one is being used) when the switch transistor is turned off. The power enhancement circuitry operates to add a third harmonic (and/or possibly other harmonics) of the carrier frequency in such a way that the peak drain voltage is reduced.

(27) Each of the power enhancement circuits 20-1 and 20-2 includes a series-connected combination of an inductor L.sub.PEC and a capacitor C.sub.PEC which can be tuned to the third harmonic of the fundamental RF frequency (although other harmonics could be used). The third harmonic signal current is added to the drain of the switching transistor (or cascode transistor, if used) to which that power enhancement circuit 20-1 or 20-2 is connected. The result of the added third harmonic signal current is to “shape” or “flatten” the drain voltages of the switching transistors (as in FIG. 2A and FIGS. 5-12), or to shape/flatten the drain voltages of the cascode transistors (as in FIG. 3), of the class-E power amplifiers in such a way that the maximum peak drain voltages are significantly reduced across all phase angles between RF drive signals S.sub.1(t) and S.sub.2(t). The reduced drain voltages allow the power supply voltage V.sub.DD to be significantly increased without damaging the switching transistors or cascode transistors by exceeding their drain-to-source voltage reliability limits. The increased value of V.sub.DD increases the peak output power that can be delivered to the load R by each class-E power amplifier and therefore increases the total peak output current/power that can be delivered to load R by outphasing power amplifier 15.

(28) When the phase angle θ between the RF drive vectors S.sub.1(t) and S.sub.2(t) indicated in FIG. 1A changes with respect to time, this causes the drain voltages of the various power switching transistors (or cascode transistors, if used) to also change. The values of L.sub.PEC and C.sub.PEC are selected such that the third harmonic signal current is added to the fundamental frequency current in such a way as to decrease the switching transistor peak drain voltage not only at a particular value of phase angle θ but the maximum drain voltage is reduced across all possible values of 0 between the S.sub.1(t) and S.sub.2(t) input signal vectors.

(29) Note that this is in direct contrast to the harmonic circuitry shown in the above mentioned paper by S. D. Kee et al., in which the drain voltage is shaped in a static class-E PA without any phase modulation as in outphasing operation.

(30) The use of power enhancement circuits 20-1 and 20-2 in FIG. 3 provides a safe way of increasing the peak permissible load current and peak permissible load power by increasing the V.sub.DD level. In power enhancement circuits 20-1 and 20-2, L.sub.PEC and C.sub.PEC are tuned such that their resonant frequency is very close to the third harmonic of the fundamental carrier frequency. A benefit of that, for a class-E power amplifier, is that in the circuit of FIG. 3 the peak levels of the drain voltages of the cascode transistors N.sub.1, N.sub.2, N.sub.3 and N.sub.4 actually decrease. The tuned L.sub.PEC and C.sub.PEC components of power enhancement circuits 20-1 and 20-2 operate to, in effect, add their third harmonic current components to the fundamental-frequency currents of the class-E power amplifiers and thereby shift the drain voltages of the four cascode transistors N.sub.1, N.sub.2, N.sub.3 and N.sub.4 waveforms by “shaping” or “flattening” those waveforms such that their maximum levels are reduced over a wide range of values of θ. This provides a margin within which the V.sub.DD level can be safely increased while nevertheless maintaining the maximum peak drain voltage waveform levels within the predetermined drain-to-source voltage specifications of the input switch transistors and their associated cascode transistors. Consequently, the amount of current/power that can be safely delivered by outphasing power amplifier 15 to load resistor R is increased by simply increasing the V.sub.DD level.

(31) The fundamental carrier phase angle θ between RF drive signals S.sub.1(t) and S.sub.2(t) changes as a function of the present power back-off requirement. Therefore, it is highly desirable that the above mentioned tuning of L.sub.PEC and C.sub.PEC so as to minimize the peak drain voltage be effective for all expected values of phase angle θ. In contrast, the prior art (see the above-mentioned Kee et al. reference) only discloses generating harmonic signals and adding them to a single fundamental-frequency signal to reduce the peak drain voltage of a switching transistor of a switching power amplifier without any phase modulation (as in outphasing operation).

(32) The basic outphasing power amplifier in FIG. 2A can be modified in various ways, for example as shown in FIGS. 2B, 3, and 5-12 below, to obtain similar performance. Some of the alternative topologies require different numbers of components.

(33) FIG. 2B shows a single-ended implementation of the outphasing power amplifier 15 in FIG. 2A wherein class-E power amplifiers 16-2 and 17-2, efficiency enhancement circuit L.sub.EEC-2, capacitors C.sub.A-2 and C.sub.A-4, and inductor L.sub.A-2 of FIG. 2A are omitted and conductors 31-3 and 31-4 are connected to ground. One terminal of load resistor R also is connected to ground.

(34) In FIG. 3 an outphasing power amplifier 15-1 is shown which is similar to outphasing power amplifier 15 in FIG. 2A, except that in FIG. 3 the class-E power amplifier 16-1 includes a N-channel cascode transistor N.sub.1 coupled between the drain of switching transistor M.sub.1 and conductor 31-1 and load resistor R is replaced by a load circuit including an output capacitor Co coupled across the primary winding of a transformer T having load resistor R coupled across its secondary winding, one terminal of which is connected to ground. The benefit of the cascode structure is that higher peak output power can be obtained at the load because the drain-to-source voltage is distributed across the two transistors (the cascode transistor and the switching transistor) where the drain-to-source breakdown voltage of the cascode transistor is much higher than that of the core switching transistor.

(35) In class-E power amplifier 16-1, the gate of switching transistor M.sub.1 is coupled to receive RF drive signal S.sub.1(t) through a driver circuit. The source of switching transistor M.sub.1 is connected to ground, and its drain is connected source of cascode transistor N.sub.1, the drain of which is connected by conductor 31-1 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-1, one terminal of a capacitor C.sub.A-1, one terminal of efficiency enhancement circuit L.sub.EEC-1, and to one terminal of a power enhancement circuit 20-1. The gate of cascode transistor N.sub.1 is connected to receive a bias voltage Bias. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-1 is connected to conductor 30-1. Power enhancement circuit 20-1 includes inductor L.sub.PEC and capacitor C.sub.PEC connected in series between conductors 31-1 and 31-3. Inductor L.sub.EEC-1, connected between conductors 31-1 and 31-2, forms a first efficiency enhancement circuit.

(36) In class-E power amplifier 16-2 of FIG. 3, the gate of switching transistor M.sub.2 is coupled to receive RF drive signal S.sub.1′(t) through a driver circuit. The source of switching transistor M.sub.2 is connected to ground, and its drain is connected to the source of cascode transistor N.sub.2, the drain of which is connected by conductor 31-3 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-2, one terminal of capacitor C.sub.A-2, one terminal of efficiency enhancement circuit L.sub.EEC-2, and to one terminal of power enhancement circuit 20-1. The gate of cascode transistor N.sub.2 is connected to receive the bias voltage Bias. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-2 is connected to conductor 30-2. Power enhancement circuit 20-1 includes an inductor L.sub.PEC and a capacitor C.sub.PEC connected in series between conductors 31-1 and 31-3.

(37) In class-E power amplifier 17-1, the gate of switching transistor M.sub.3 is coupled to receive RF drive signal S.sub.2(t) through a driver circuit. The source of switching transistor M.sub.3 is connected to ground, and its drain is connected source of cascode transistor N.sub.3, the drain of which is connected by conductor 31-2 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-3, one terminal of capacitor C.sub.A-3, one terminal of the efficiency enhancement circuit L.sub.EEC-1, and to one terminal of power enhancement circuit 20-2. The gate of cascode transistor N.sub.3 is connected to receive the bias voltage Bias. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-3 is connected to conductor 30-1. Power enhancement circuit 20-2 includes inductor L.sub.PEC and capacitor C.sub.PEC connected in series between conductors 31-2 and 31-4. Inductor L.sub.EEC-2, connected between conductors 31-3 and 31-4, forms a second efficiency enhancement circuit.

(38) In class-E power amplifier 17-2, the gate of switching transistor M.sub.4 is coupled to receive RF drive signal S.sub.2′(t) through a driver circuit. The source of switching transistor M.sub.4 is connected to ground, and its drain is connected to the source of cascode transistor N.sub.4, the drain of which is connected by conductor 31-4 to one terminal of inductor L.sub.C, one terminal of capacitor C.sub.P-4, one terminal of capacitor C.sub.A-4, one terminal of the efficiency enhancement circuit L.sub.EEC-2, and to one terminal of power enhancement circuit 20-2. The gate of cascode transistor N.sub.4 is connected to receive bias voltage Bias. The other terminal of inductor L.sub.C is connected to power supply voltage V.sub.DD. The other terminal of capacitor C.sub.A-4 is connected to conductor 30-2. Power enhancement circuit 20-2 includes an inductor L.sub.PEC and a capacitor C.sub.PEC connected in series between conductors 31-2 and 31-4.

(39) Inductor L.sub.A-1 is coupled between conductor 30-1 and conductor 32-1, and inductor L.sub.A-2 is coupled between conductor 30-2 and conductor 32-2. An output capacitor C.sub.O is connected between conductors 32-1 and 32-2, and the terminals of the primary winding of transformer T are connected to conductors 32-1 and 32-2, respectively. The load resistor R is connected between the terminals of the secondary winding of transformer T, one of the secondary winding terminals being connected to ground.

(40) The cascode transistors in FIG. 3 allow higher RF voltages at the drain terminals of the cascode transistors, and this allows outphasing power amplifier 15-1 to deliver higher peak output power. By adding the power enhancement circuits 20-1 and 20-2, maximum peak voltage at the drain of the cascode device is reduced across all phase angles. In one case, this allows increasing of V.sub.DD by 0.4 volts without violating the allowed maximum drain-source voltage limitation. In that case, this increase in supply voltage results in a 200 milliwatt increase in the peak output power that can be delivered by the outphasing power amplifier of FIG. 3.

(41) The graph in FIG. 4A shows drain efficiency versus instantaneous output power delivered to load, with and without use of the L.sub.EEC efficiency enhancement circuit. The output power of the described outphasing power amplifier is increased by reducing the phase angle θ between the S.sub.1(t) and S.sub.2(t) vectors. The addition of the L.sub.EEC inductor improves the power efficiency of the outphasing power amplifier during large power back-off conditions, as indicated by curve “A” in the graph of FIG. 4A. If the phase angle θ between the S.sub.1(t) and S.sub.2(t) vectors is increased, the output power is decreased and the outphasing power amplifier's power efficiency falls sharply without the L.sub.EEC efficiency enhancement circuit, as indicated by curve “B”. The graph of FIG. 4B shows drain voltage in a class-E outphasing power amplifier with and without power enhancement circuitry. The drain voltage is “flattened” by adding the power enhancement circuitry.

(42) FIG. 5 is similar to FIG. 2A, except that in outphasing amplifier 15-2 of FIG. 5 the locations of the various “C.sub.A capacitors” and “L.sub.A inductors” have been interchanged. Specifically, inductor L.sub.A-1 is connected between conductor 31-1 and conductor 30-1, and capacitor C.sub.A-1 is connected between conductor 30-1 and conductor 32-1. Also, inductor L.sub.A-3 is connected between conductor 31-2 and conductor 30-1. Similarly, inductor L.sub.A-2 is connected between conductor 31-3 and conductor 30-2, and capacitor C.sub.A-2 is connected between conductor 30-2 and conductor 32-2. Inductor L.sub.A-4 is connected between conductor 31-4 and conductor 30-2. The values of the “L.sub.A inductors” and the “C.sub.A capacitors” are different in this case compared to their values in FIGS. 2A and 3. In FIG. 5, the efficiency enhancement circuits Z.sub.EEC-1 and Z.sub.EEC-2 may be either capacitive or inductive, depending on the values of the “C.sub.P capacitors” and the “L.sub.A inductors”, so as to provide high-impedance parallel resonant circuits. Also, the efficiency enhancement circuits Z.sub.EEC-1 and Z.sub.EEC-2 in FIGS. 7-8 may be either capacitive or inductive.

(43) In FIG. 6, outphasing power amplifier 15-3 has a configuration somewhat similar to that of FIG. 2A. The output circuit is different in this case and includes output capacitor C.sub.O connected between conductors 32-1 and 32-2 in parallel with load resistance R. The output capacitor is part of the matching network and is used for transforming a 50 ohm load impedance to a lower value at the output of the individual PAs for the purpose of maximizing power transfer.

(44) In outphasing power amplifier 15-4 of FIG. 7, the locations of the “L.sub.A inductors” and the “C.sub.A capacitors” have been reversed relative to FIG. 6. The outphasing power amplifier in FIG. 6 has a lower number of inductors and is easier to implement in integrated circuits compared to the outphasing power amplifier in FIG. 7. (Note that FIGS. 2A, 5, 6, and 7 show various combinations of the locations of the “C.sub.A capacitors” and the “L.sub.A inductors” with and without the output capacitor C.sub.O.)

(45) In outphasing power amplifier 15-5 of FIG. 8, the circuit connections are the same as in FIG. 7 except that all of the “C.sub.A capacitors”, “C.sub.P capacitors”, “C.sub.PEC capacitors”, and the output capacitor C.sub.O are tunable. The tunable capacitors make it practical to compensate for the effects of manufacturing process variations and also make it practical to tune for different center frequencies or carrier frequencies of the RF drive signals S.sub.1(t) and S.sub.2(t). The reason that the tunability is desirable is that in a practical scenario the actual components (inductor, capacitor, resistor, etc.) values typically may vary from their nominal design values due to manufacturing process variation. That variation can cause undesired change in circuit performance and/or other undesired circuit problems. The “tunability” of certain capacitances allows the integrated circuit to be adjusted after fabrication so as to compensate for the above indicated “process variation” in component parameters. (Note that tuning capacitors also can be provided for the other described embodiments of the present invention. The tunable capacitors can be implemented by varactors or parallel capacitors connected by switches and switching them on and off from the circuit to control the effective capacitance.)

(46) In outphasing power amplifier 15-9 of FIG. 9, the basic circuit configuration is similar to that in FIG. 7 except the efficiency enhancement circuits are implemented by L.sub.A inductors. Power enhancement circuit 20-1 is connected between conductors 31-1 and 31-3, and power enhancement circuit 20-2 is connected between conductors 31-2 and 31-4, as shown in FIG. 9. Inductors L.sub.A-1, L.sub.A-2, L.sub.A-3, and L.sub.A-4, inductors L.sub.B-1 and L.sub.B-2, and capacitors C.sub.A-1 and C.sub.A-2 are connected as shown in FIG. 9. However, the efficiency enhancement circuit function, in addition to the class-E output signal combining function is performed by the above-mentioned components shown in outphasing power amplifier 15-9. For out-of-phase components of S.sub.1(t) and S.sub.2(t), the L.sub.A inductors with the C.sub.P capacitors form parallel resonant circuits and provide high impedance at fundamental frequency and reduce the out-of-phase current and thereby perform the efficiency enhancement function. The L.sub.A and L.sub.B inductors and C.sub.A capacitors form the class-E tuned combiner circuit. The inductors are “split” as the L.sub.A and L.sub.B inductors such that the L.sub.A inductors perform the efficiency enhancement function and the L.sub.A and L.sub.B inductors together provide the required combiner circuit inductance.

(47) Still referring to FIG. 9, it should be understood that for out-of-phase components of S.sub.1(t) and S.sub.2(t), there is a virtual ground at the at the left terminal 30-1 of inductor L.sub.B-1. Consequently, capacitor C.sub.P-1 and inductor L.sub.A-1 are effectively coupled in parallel. The inductance of L.sub.A-1 is such that it resonates with capacitor C.sub.P-1 to provide a high impedance parallel resonant network at the carrier frequency of RF drive signals S.sub.1(t) and S.sub.2(t). (This could not be accomplished in the above-described embodiments of the invention because the value of inductor L.sub.A-1 is determined by the various design parameter values chosen for the combiner circuitry which adds the four class-E power amplifier output signals in order to generate the output voltage across the load resistor R. Consequently, the circuit designer does not have the flexibility to choose the value of inductor L.sub.A-1 such that it can contribute to the “efficiency enhancement function” in addition to performing the power amplifier output signal combining function. However, in outphasing power amplifier 15-9 of FIG. 9, the circuit designer does have the flexibility to choose the value of inductor L.sub.A-1 in such a way as to provide both the efficiency enhancement function and the power amplifier output signal combining function with class-E operation, because for the combining function the value of inductor L.sub.B-1 can be added with the value of inductor L.sub.A-1. (This is also true for the other L.sub.A inductors.)

(48) FIG. 10 shows a variation which is the same as the outphasing power amplifier 15-9 of FIG. 9 except that in each of the power enhancement circuits 20-1 and 20-2 of FIG. 10, each of the single inductors L.sub.PEC has been “split” into two separate inductors each having an inductance equal to L.sub.PEC/2. In power enhancement circuit 20-1, one of the two L.sub.PEC/2 inductors is connected between conductor 31-1 and one terminal of the C.sub.PEC capacitor and the other L.sub.PEC/2 inductor is connected between conductor 31-3 and the opposite terminal of the C.sub.PEC capacitor. Similarly, in power enhancement circuit 20-2, one of the L.sub.PEC/2 inductors is connected between conductor 31-2 and one terminal of the C.sub.PEC capacitor and the other L.sub.PEC/2 inductor is connected between conductor 31-4 and the other terminal of the C.sub.PEC capacitor. Note that in FIG. 10 the drains of the switching transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 all are coupled to inductors. One benefit of this configuration is that if the switching transistors are implemented “on-chip” and the elements of the combiner are implemented using external (“off-chip”) discrete components, then the inductors of the combiner can be implemented by bond wire inductance or the bond wire inductors can be in effect “absorbed” by the external inductors.

(49) The above described embodiments of the invention have the advantages of providing improvement in power efficiency, improvement in achievable peak output power levels, and ease of implementation.

(50) While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, more cascode transistors can be “stacked” in series in any of the described embodiments of the invention if needed to allow V.sub.DD to be increased, and thereby increase the amount of peak power that can be safely delivered to the load by outphasing power amplifier without exceeding the power transistor breakdown specifications. In any of the disclosed embodiments of the invention, an output capacitor can be coupled by a transformer to the load driven by the outphasing power amplifier.