Multilevel class-D amplifiers

Abstract

Implementations of a class-D amplifier can be used to amplify an input analog signal and provide to a load a multilevel amplified signal having an amplitude larger than a voltage level of a power source used by the class-D amplifier.

Claims

1. An amplifier system for amplifying an input signal that varies over time, the amplifier system comprising: a multilevel output stage powered with a voltage having a predetermined voltage level relative to ground; a multilevel modulator configured to form a plurality of pulse-width modulated (PWM) driving signals based on i) the input signal and ii) a square carrier signal, and drive the multilevel output stage with the plurality of PWM driving signals; a pair of output ports coupled with the multilevel output stage; and a boost capacitor having two terminals, one of the two terminals being coupled with a first output port of the pair of output ports, wherein the multilevel output stage is configured to output, at the pair of output ports, when driven with the plurality of PWM driving signals, an output signal having a plurality of levels, wherein differences between adjacent levels of the output signal have a magnitude equal to the predetermined voltage level, wherein an amplitude of the output signal is a non-unity integer multiple of the predetermined voltage level, wherein the output signal varies over time between its multiple levels in accordance with the input signal, and wherein the multilevel output stage comprises four high-voltage (HV) switches, that form, when a load is coupled between the pair of output ports, an output bridge that includes the four HV switches and the load; and a boost bridge that includes a pair of the HV switches, a pair of low-voltage (LV) switches, and the boost capacitor, wherein the pair of the HV switches are coupled with each other and with the one of the two terminals of the boost capacitor at the first output port, wherein the pair of LV switches are coupled with each other and with another one of the two terminals of the boost capacitor, and wherein the boost bridge is driven by a pair of PWM driving signals of the plurality of PWM driving signals.

2. The amplifier system of claim 1, wherein the amplitude of the output signal is twice the predetermined voltage level.

3. The amplifier system of claim 1, wherein the multilevel output stage further comprises a second boost capacitor having two terminals, one of the two terminals being coupled with a second output port of the pair of output ports; and a second boost bridge that includes a second pair of the HV switches, a second pair of LV switches, and the second boost capacitor, wherein the second pair of the HV switches are coupled with each other and with the one of the terminals of the second boost capacitor at the second output port, wherein the second pair of LV switches are coupled with each other and with another one of the terminals of the second boost capacitor, and wherein the second boost bridge is driven by a second pair of PWM driving signals of the plurality of PWM driving signals.

4. The amplifier system of claim 3, wherein the amplitude of the output signal is three times the predetermined voltage level.

5. The amplifier system of claim 3, comprising a power supply that provides the predetermined voltage level to the multilevel output stage.

6. The amplifier system of claim 3, wherein the multilevel output stage further comprises a boost stage, and the amplifier system comprises a power supply that powers the boost stage through a boost inductor with a power supply voltage level smaller than the predetermined voltage level, and causes the boost stage to provide the predetermined voltage level to the first and second boost bridges.

7. The amplifier system of claim 1, wherein the multilevel modulator comprises a fully differential integrator.

8. The amplifier system of claim 7, wherein the multilevel modulator comprises a differential input to receive the input signal.

9. The amplifier system of claim 8, wherein the multilevel modulator comprises four outputs through which respective four PWM driving signals are delivered to the multilevel output stage.

10. An amplification system comprising: an integrated circuit chip comprising amplifier circuitry, the amplifier circuitry comprising a multilevel modulator including two modulator input ports, and four modulator output ports; and a multilevel output stage including four output stage input ports respectively coupled with the four modulator output ports, four output stage boost ports, a first pair of high-voltage (HV) switches connected to each other at a first one of the output stage boost ports, the first pair of HV switches having a first control terminal coupled to a first one of the output stage input ports, a second pair of HV switches connected to each other at a second one of the output stage boost ports, the second pair of HV switches having a second control terminal coupled to a second one of the output stage input ports, a first pair of low-voltage (LV) switches connected to each other at a third one of the output stage boost ports, the first pair of LV switches having a third control terminal coupled to a third one of the output stage input ports, and a second pair of LV switches connected to each other at a fourth one of the output stage boost ports, the second pair of LV switches having a fourth control terminal coupled to a fourth one of the output stage input ports; two amplifier input ports respectively coupled with the modulator input ports; two amplifier output ports respectively coupled with the first output stage boost port and the second output stage boost port, wherein, during operation of the amplifier system, a load coupled between the two amplifier output ports causes formation of an output bridge that includes the first pair of HV switches, the second pair of HV switches and the load; and a boost capacitor having two terminals, one of the two terminals being coupled to the first output stage boost port, and another of the two terminals being coupled to the third output stage boost port, thereby forming a boost bridge that includes the first pair of HV switches, the first pair of LV switches and the boost capacitor.

11. The amplification system of claim 10, comprising: a second boost capacitor having two terminals, one of the two terminals of the second boost capacitor being coupled to the second output stage boost port and at the other one of the terminals of the second boost capacitor being coupled to the fourth output stage boost port, thereby forming a second boost bridge that includes the second pair of HV switches, the second pair of LV switches and the second boost capacitor.

12. The amplification system of claim 11, comprising a power supply to power the multilevel output stage with a predetermined voltage level.

13. The amplification system of claim 11, wherein the multilevel output stage comprises a boost stage including a boost stage input and a boost stage output, the amplification system further comprises: a boost inductor coupled with the boost stage input; and a power supply to power the boost stage through the boost inductor with a power supply voltage level, the boost stage to power the multilevel output stage with a predetermined voltage level that is boosted relative to the power supply voltage level.

14. The amplification system of claim 10, wherein the multilevel modulator comprises a fully differential integrator.

15. The amplification system of claim 14, wherein the multilevel modulator is configured to perform, during operation of the integrated circuit chip comprising amplifier circuitry, operations comprising: receive an input signal through the modulator input ports, form four pulse-width modulated (PWM) drive signals based on (i) the input signal and (ii) a square carrier signal, and provide the four PWM drive signals, through respective modulator output ports to respective output stage input ports, to drive the output stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A-1D show aspects of a multilevel class D amplifier that includes a multilevel modulator and a multilevel output stage.

(2) FIG. 2 shows aspects of a multilevel output stage that provides a multilevel output signal with an amplitude equal to a non-unity integer multiple of a power supply voltage.

(3) FIGS. 3A-3B show aspects of a multilevel output stage that provides an output signal with an amplitude equal to a power supply voltage.

(4) FIGS. 4A-4B show aspects of a multilevel output stage that provides a multilevel output signal with an amplitude equal to twice a power supply voltage.

(5) FIGS. 5A-5B show aspects of a multilevel output stage that provides a multilevel output signal with an amplitude equal to three times a power supply voltage.

(6) FIGS. 6A-6B show aspects of a multilevel output stage that provides a multilevel output signal with an amplitude equal to three times a boosted power supply voltage.

(7) FIG. 7 shows an example of a multilevel modulator.

(8) FIG. 8 shows aspects of signals formed inside, and aspects of pulse-width modulated (PWM) driving signals output by, the multilevel modulator from FIG. 7.

(9) FIGS. 9A-9B show aspects of a conventional charge-pump implementation of an output stage of a class D amplifier.

(10) FIGS. 10A-10B show aspects of a conventional DC-DC boosted implementation of an output stage of a class D amplifier.

(11) Certain illustrative aspects of the systems, apparatuses, and methods according to the disclosed technologies are described herein in connection with the following description and the accompanying figures. These aspects are, however, indicative of but a few of the various ways in which the principles of the disclosed technologies may be employed and the disclosed technologies are intended to include all such aspects and their equivalents. Other advantages and novel features of the disclosed technologies may become apparent from the following detailed description when considered in conjunction with the figures.

DETAILED DESCRIPTION

(12) FIGS. 1A-1D show aspects of a multilevel class D amplifier 100, also referred to as an amplifier system or amplification system, that includes a multilevel modulator 110 and a multilevel output stage 160. FIG. 1A shows an example of an implementation of the amplifier system 100 in which the multilevel modulator 110 and the multilevel output stage 160 are part of the same IC chip 103. In other implementations, the multilevel modulator 110 is part of a first IC chip and the multilevel output stage 160 is part of a second, different IC chip. Further, the amplifier system 100 includes a pair of input ports (inP, inM) to receive an input analog signal, when an analog signal source 102 is coupled to the input ports. Note that the input analog signal can be an audio signal having frequency components in the audio frequency range [200 Hz, 20 kHz], or can be an analog signal having frequency components in other frequency ranges (e.g., lower than, overlapping or higher than the audio frequency range). Furthermore, the amplifier system 100 includes a pair of output ports (outP, outM) to provide an amplified signal, when a load 105 is coupled to the output ports. Here, the amplified signal is an amplified replica of the input analog signal received from the signal source 102.

(13) The multilevel modulator 110 includes a pair of modulator input ports (mi1, mi2) that are respectively coupled to the input ports (inP, inM) of the amplifier system 100. Additionally, the multilevel modulator 110 includes four modulator output ports (mo1, mo2, mo3, mo4). The multilevel output stage 160 includes four output stage input ports (si1, si3, si2, si4) respectively coupled to the four modulator output ports (mo1, mo2, mo3, mo4). Also, the multilevel output stage 160 includes four output stage boost ports (so1, so3, so2, so4). Here, a first pair (so1, so2) of the output stage boost ports (so1, so3, so2, so4) is coupled to the output ports (outP, outM) of the amplifier system 100.

(14) In some implementations, a terminal of a power supply associated with the amplifier system 100 that is biased with a voltage level V.sub.BAT is coupled directly with the multilevel output stage 160 through a power connector. In other implementations, the terminal of the power supply that is biased with the voltage lever V.sub.BAT is coupled with the multilevel output stage 160 through a boost inductor L.sub.BST of the amplifier system 100. Here, the power supply can be a battery and a value of the voltage level can be V.sub.BAT=3.7V. It should be noted that the mechanisms described herein apply equally to other types of power supplies and/or other voltage levels.

(15) In addition, the amplifier system 100 can include a boost capacitor C.sub.BST1 having two terminals, where one of the two terminals is coupled to the first output stage boost port so1—that also is coupled to the first output port outP, and another of the two terminals is coupled to the third output stage boost port so3. In this boosted implementation of the amplifier system 100, the predetermined voltage level V.sub.BAT is provided by the power supply directly to the multilevel output stage 160, as described below in connection with FIGS. 4A-4B. Note that the boost capacitor C.sub.BST1 and the power supply can be connected to the multilevel output stage 160 in the foregoing manner during fabrication of the amplifier system 100, e.g., to satisfy specifications of a low-to-mid-priced consumer electronics device in which this boosted amplifier system will be integrated.

(16) Further, the amplifier system 100 can include a second boost capacitor C.sub.BST2 in addition to the boost capacitor C.sub.BST1. The second boost capacitor C.sub.BST2 also has two terminals, where one of the two terminals is coupled to the second output stage boost port so2, which is coupled to the second output port outM, and another of the two terminals is coupled to the fourth output stage boost port so4. In this double-boosted implementation of the amplifier system 100, the predetermined voltage level V.sub.BAT is provided by the power supply directly to the multilevel output stage 160, as described below in connection with FIGS. 5A-5B. Note that the boost capacitor C.sub.BST1, the second boost capacitor C.sub.BST2 and the power supply can be connected to the multilevel output stage 160 in the foregoing manner during fabrication of the amplifier system 100, e.g., to satisfy specifications of a mid-to-high-priced consumer electronics device in which this double-boosted amplifier system will be integrated.

(17) Moreover, a highly boosted implementation of the amplifier system 100 once again includes the boost capacitor C.sub.BST1 coupled between the first output stage boost port so1 and the third output stage boost port so3 and the second boost capacitor C.sub.BST2 coupled between the second output stage boost port so2 and the fourth output stage boost port so4. However, in the highly boosted implementation of the amplifier system 100, the predetermined voltage level V.sub.BAT is provided by the power supply to the multilevel output stage 160 through the boost inductor L.sub.BST, as described below in connection with FIGS. 6A-6B. Note that the boost capacitor C.sub.BST1, the second boost capacitor C.sub.BST2, the boost inductor L.sub.BST and the power supply can be connected to the multilevel output stage 160 in the foregoing manner during fabrication of the amplifier system 100, e.g., to satisfy specifications of a high-priced consumer electronics device in which this boosted amplifier system will be integrated.

(18) FIG. 1B shows an implementation of the amplifier system 100 in which the boost capacitor C.sub.BST1 is connected to one output port (outP) of the amplifier system and second the boost capacitor C.sub.BST2 is connected to the other output port (outM) of the amplifier system as described above for the double-boosted implementation or the highly boosted implementation of the amplifier system. In the example illustrated in FIG. 1B, a first instance 101(+) and a second instance 101(−) of the input analog signal is received by the amplifier system 100 through the input ports (inP, inM). Here, the input analog signal 101(+), 101(−) is an audio signal, and the load 105 coupled to the output ports (outP, outM) of the amplifier system 100 is a speaker.

(19) The multilevel modulator 110 forms four pulse-width modulated (PWM) driving signals 152 (labeled HM, LM, LP, HP) by combining the input analog signal 101(+), 101(−) and an internal, square carrier signal. The formed PWM driving signals 152 (HM, LM, LP, HP) are indicative of the input analog signal 101(+), 101(−), as illustrated in FIG. 1C.

(20) Referring again to FIG. 1B, the multilevel output stage 160 is driven by the four PWM driving signals 152 (HM, LM, LP, HP) and issues a first multilevel output signal 192a to one output port (outP) of the amplifier system 100 and a second multilevel output signal 192b to the other output port (outM) of the amplifier system. In this implementation, each of the multilevel output signals 192a, 192b issued respectively to the output ports (outP, outM) has a dynamic range of [−V.sub.DD, +2V.sub.DD], that corresponds to a peak-to-peak swing of 3V.sub.DD, as shown in FIG. 1D. Moreover, differences between adjacent levels of each of the multilevel output signals 192a, 192b have a magnitude equal to V.sub.DD. Note that V.sub.DD.sup.=V.sub.BAT for the double boosted implementation of the amplifier system 100, when the power supply provides the predetermined voltage level V.sub.BAT directly to the multilevel output stage 160, and V.sub.DD=V.sub.BST for the highly boosted implementation of the amplifier system 100, when the power supply provides the predetermined voltage level V.sub.BAT to the multilevel output stage through the boost inductor L.sub.BST. For example, a value of the boosted voltage level is V.sub.BST=5.5V.

(21) An amplified signal 192, provided by the multilevel output stage 160 to the load 105 coupled to the outputs (outP, outM), is a difference between the multilevel output signals 192a, 192b. In this manner, the amplified signal 192 provided to the load 105 is a multilevel replica of the input signal and has an amplitude of 3V.sub.DD, that corresponds to a peak-to-peak swing of 6V.sub.DD, as shown in FIG. 1D. As in the case of the multilevel output signals 192a, 192b, differences between adjacent levels of the amplified signal 192 have a magnitude equal to V.sub.DD (where V.sub.DD=V.sub.BAT or V.sub.DD=V.sub.BST).

(22) FIG. 2 shows aspects of a multilevel output stage 260 that can provide to a load a multilevel amplified signal V.sub.LOAD with an amplitude equal to an integer multiple of a power supply voltage V.sub.DD. The multilevel output stage 260 can be used as the multilevel output stage 160 of the multilevel class-D amplifier 100 shown in FIGS. 1A-1B. Note that the multilevel output stage 260 can be formed on an IC chip, e.g., on the IC chip 103 shown in FIG. 1A.

(23) The multilevel output stage 260 includes four output stage input ports (si1, si3, si2, si4). When integrated in a multilevel class-D amplifier (like the one shown in FIGS. 1A-1B), the output stage input ports (si1, si3, si2, si4) are respectively coupled to modulator output ports of a multilevel modulator (e.g., the modulator output ports (mo1, mo2, mo3, mo4) of the multilevel modulator 110 shown in FIG. 1A) to receive respective driving PWM signals (LP, LM, HP, HM). Further, the multilevel output stage 260 includes four output stage boost ports (so1, so3, so2, so4).

(24) The multilevel output stage 260 includes a first pair of high-voltage (HV) switches (e.g., high-voltage power MOSFETs arranged in a cascoded structure) connected to each other at a first one (so1) of the output stage boost ports (so1, so3, so2, so4). The first pair of HV switches is powered with a power supply voltage level V.sub.DD (relative to ground), and has a first control terminal coupled to a first one (si1) of the output stage input ports (si1, si3, si2, si4). Note that each of the HV switches of the first pair includes a gate terminal and the gate terminals are coupled with the first control terminal through logic circuitry. When the multilevel output stage 260 is used in the multilevel class-D amplifier 100, a first PWM driving signal LP is applied to the first output stage input port (si1), and the first output stage boost port (so1) is coupled to one output port (outP) of the multilevel class-D amplifier where one of two terminals of a load is connected. Additionally, the multilevel output stage 260 includes a second pair of HV switches connected to each other at a second one (so2) of the output stage boost ports (so1, so3, so2, so4). The second pair of HV switches also is powered with the power supply voltage level V.sub.DD, and has a second control terminal coupled to a second one (si2) of the output stage input ports (si1, si3, si2, si4). Note that each of the HV switches of the second pair includes a gate terminal, and the gate terminals are coupled with the second control terminal through logic circuitry. When the multilevel output stage 260 is used in the multilevel class-D amplifier 100, a second PWM driving signal LM is applied to the second output stage input port (si2), and the second output stage boost port (so1) is coupled to the other output port (outM) of the multilevel class-D amplifier where the other one of the two terminals of the load is connected. In this manner, when the load is connected to the output ports (outP, outM), an output bridge 270 is formed that includes the first pair of HV switches, the second pair of HV switches and the load. Here, the output bridge 270 provides to the load the amplified signal V.sub.LOAD.

(25) Further, the multilevel output stage 260 includes a first pair of low-voltage (LV) switches (e.g., low-voltage MOSFETs arranged in a cascoded complementary metal-oxide semiconductor (CMOS) structure) connected to each other at a third one (so3) of the output stage boost ports (so1, so3, so2, so4). The first pair of LV switches also is powered with the power supply voltage level V.sub.DD, and has a third control terminal coupled to a third one (si3) of the output stage input ports (si1, si3, si2, si4). Note that each of the LV switches of the first pair includes a gate terminal and the gate terminals are coupled with the third control terminal through logic circuitry. When the multilevel output stage 260 is used in the multilevel class-D amplifier 100, a third PWM driving signal HP is applied to the third output stage input port (si3). Furthermore, the multilevel output stage 260 includes a second pair of LV switches connected to each other at a fourth one (so4) of the output stage boost ports (so1, so3, so2, so4). The second pair of LV switches also is powered with the power supply voltage level V.sub.DD, and has a fourth control terminal coupled to a fourth one (si4) of the output stage input ports (si1, si3, si2, si4). Note that each of the LV switches of the fourth pair includes a gate terminal, and the gate terminals are coupled with the fourth control terminal through logic circuitry. When the multilevel output stage 260 is used in the multilevel class-D amplifier 100, a fourth PWM driving signal HM is applied to the fourth output stage input port (si4).

(26) Moreover, the multilevel output stage 260 includes a boost stage 180. If the boost stage 180 is powered with a voltage level V.sub.L through a boost inductor L.sub.BST, which is external to the multilevel output stage, then the boost stage outputs the power supply voltage level V.sub.DD.sup.=V.sub.BST (relative to ground). For example, a battery is used to provide the voltage level V.sub.L, such that V.sub.L=V.sub.BAT<V.sub.BST. Else, if the boost stage 180 is not powered, i.e., a boost inductor L.sub.BST is not connected between the battery and the boost stage 180, then the battery is connected directly to the multilevel output stage 260 (not via the boost inductor L.sub.BST) and provides the power supply voltage level V.sub.DD.sup.=V.sub.BAT (relative to ground).

(27) The multilevel output stage 260 can be integrated in the amplifier system 100, as is, i.e., without connecting one or two boost capacitors C.sub.BST1, C.sub.BST2 to select pairs of the output stage boost ports (so1, so3, so2, so4), and without connecting the boost inductor L.sub.BST to the boost stage 180. This case is illustrated in FIG. 3A, where L.sub.BST=N/A, V.sub.L=N/A, C.sub.BST1=N/A, C.sub.BST2=N/A and the power supply voltage level is V.sub.DD=V.sub.BAT. Here, PWM driving signals (LP, LM, HP, HM) are applied to respective output stage input ports (si1, si3, si2, si4). FIG. 3B shows a graph 392 of an amplified signal V.sub.LOAD provided to the load at the output ports (outP, outM) of the output bridge 270. In this case, an amplitude of the amplified signal V.sub.LOAD is equal to the power supply voltage level V.sub.BAT, e.g., amplitude(V.sub.LOAD)=3.7V.

(28) Referring again to FIG. 2, one or two boost capacitors C.sub.BST1, C.sub.BST2, that are external to the multilevel output stage 260, can be connected to select pairs of the output stage boost ports (so1, so3, so2, so4), and the boost inductor L.sub.BST can be connected to the boost stage 180, when the multilevel output stage 260 is integrated in the amplifier system 100. In a first example, a boost capacitor C.sub.BST1 is coupled between the third output stage input port (si3) and the first output stage input port (si1/outP) to form a boost bridge 272a that includes the first pair of HV switches, the first pair of LV switches and the boost capacitor C.sub.BST1. This case is illustrated in FIG. 4A, where L.sub.BST=N/A, V.sub.L=N/A, C.sub.BST2=N/A and the power supply voltage level is V.sub.DD=V.sub.BAT. Here, PWM driving signals (LP, LM, HP, HM) are applied to respective output stage input ports (si1, si3, si2, si4), and a value of 10 μF can be chosen for the boost capacitor C.sub.BST1 of the boost bridge 272a, for instance. FIG. 4B shows a graph 492 of a multilevel amplified signal V.sub.LOAD provided to the load by the output bridge 270 at the output ports (outP, outM). In this case, an amplitude of the amplified signal V.sub.LOAD is equal to twice the power supply voltage level 2V.sub.BAT, e.g., amplitude(V.sub.LOAD)=3.7+3.7=7.4V, while differences between adjacent levels of the multilevel amplified signal V.sub.LOAD have a magnitude equal to the power supply voltage level V.sub.BAT. The increase from V.sub.BAT to 2V.sub.BAT of the amplitude of the multilevel amplified signal V.sub.LOAD provided to the load at the output ports (outP, outM) of the output bridge 270 is caused by charging and discharging of the boost capacitor C.sub.BST1 of the boost bridge 272a.

(29) Referring again to FIG. 2, as a second example, a first boost capacitor C.sub.BST1 is coupled between the third output stage input port (si3) and the first output stage input port (si1/outP) to form a first boost bridge 272a that includes the first pair of HV switches, the first pair of LV switches and the first boost capacitor C.sub.BST1. And a second boost capacitor C.sub.BST2 is coupled between the fourth output stage input port (si4) and the second output stage input port (si2/outM) to form a second boost bridge 272b that includes the second pair of HV switches, the second pair of LV switches and the second boost capacitor C.sub.BST2. This case is illustrated in FIG. 5A, where L.sub.BST=N/A, V.sub.L=N/A and the power supply voltage level is V.sub.DD=V.sub.BAT. Here, PWM driving signals (LP, LM, HP, HM) are applied to respective output stage input ports (si1, si3, si2, si4), and a value of 10 μF can be chosen for both the first boost capacitor C.sub.BST1 of the first boost bridge 272a and the second boost capacitor C.sub.BST2 of the second boost bridge 272b, for instance. FIG. 5B shows a graph 592 of a multilevel amplified signal V.sub.LOAD provided to the load by the output bridge 270 at the output ports (outP, outM). In this case, an amplitude of the amplified signal V.sub.LOAD is equal to three times the power supply voltage level 3V.sub.BAT, e.g., amplitude(V.sub.LoAD)=3.7+3.7+3.7=11.1V, while differences between adjacent levels of the multilevel amplified signal V.sub.LOAD have a magnitude equal to the power supply voltage level V.sub.BAT. The increase from 2V.sub.BAT To 3V.sub.BAT of the amplitude of the multilevel amplified signal V.sub.LOAD provided to the load at the output ports (outP, outM) of the output bridge 270 is caused by charging and discharging of both the first boost capacitor C.sub.BST1 of the first boost bridge 272a and the second boost capacitor C.sub.BST2 of the second boost bridge 272b.

(30) Referring again to FIG. 2, as a third example, a first boost capacitor C.sub.BST1 is coupled between the third output stage input port (si3) and the first output stage input port (si1/outP) to form a first boost bridge 272a that includes the first pair of HV switches, the first pair of LV switches and the first boost capacitor C.sub.BST1. Further, a second boost capacitor C.sub.BST2 is coupled between the fourth output stage input port (si4) and the second output stage input port (si2/outM) to form a second boost bridge 272b that includes the second pair of HV switches, the second pair of LV switches and the second boost capacitor C.sub.BST2. Furthermore, a boost inductor L.sub.BST is coupled between a battery that outputs a voltage level V.sub.BAT and an input of the boost stage 180. This case is illustrated in FIG. 6A, where the voltage level V.sub.L used to power the boost stage 180 through the boost inductor L.sub.BST is V.sub.L=V.sub.BAT, which causes for the power supply voltage level V.sub.DD to be equal to a boosted voltage level V.sub.BST output by the boost stage 180: V.sub.DD=V.sub.BST. Here, PWM driving signals (LP, LM, HP, HM) are applied to respective output stage input ports (si1, si3, si2, si4). Moreover, a value of 10 μF can be chosen for both the first boost capacitor C.sub.BST1 of the first boost bridge 272a and the second boost capacitor C.sub.BST2 of the second boost bridge 272b, and a value of 2 μH can be chosen for the boost inductance L.sub.BST, for instance. FIG. 6B shows a graph 692 of a multilevel amplified signal V.sub.LOAD provided to the load by the output bridge 270 at the output ports (outP, outM). In this case, an amplitude of the amplified signal V.sub.LOAD is equal to three times the power supply voltage level 3V.sub.BST, e.g., amplitude(V.sub.LOAD)=5.5+5.5+5.5=16.5V, while differences between adjacent levels of the multilevel amplified signal V.sub.LOAD have a magnitude equal to the power supply voltage level V.sub.BST. Once again, the increase from 2V.sub.BST to 3V.sub.BST of the amplitude of the multilevel amplified signal V.sub.LOAD provided to the load at the output ports (outP, outM) of the output bridge 270 is caused by charging and discharging of both the first boost capacitor C.sub.BST1 of the first boost bridge 272a and the second boost capacitor C.sub.BST2 of the second boost bridge 272b. Connecting the boost inductor L.sub.BST to the boost stage 180 of the multilevel output stage 260, for the example illustrated in FIG. 6A, causes not only an increase of the amplitude of the amplified signal V.sub.LOAD from 11.1V to 15.5V compared to the example shown in FIG. 5A, but also ensures that the amplitude 3V.sub.BST of the amplified signal V.sub.LOAD is independent from the state of charge of the battery. In contrast, the amplitude 3V.sub.BAT of the amplified signal V.sub.LOAD for the double boosted implementation of the multilevel output state 260, illustrated in FIG. 5A, can decrease along with the voltage level V.sub.BAT when the charge of the battery decreases.

(31) FIG. 7 shows an example of a multilevel modulator 710. The multilevel modulator 710 can be used as the multilevel modulator 110 of the multilevel class-D amplifier 100 shown in FIGS. 1A-1B. Note that the multilevel modulator 710 can be formed on an IC chip, e.g., on the IC chip 103 shown in FIG. 1A.

(32) The multilevel modulator 710 includes a pair of modulator input ports (mi1, mi2). When used in the amplifier system 100 shown in FIG. 1A, the modulator input ports (mi1, mi2) are respectively coupled to the input ports (inP, inM) of the amplifier system to receive a first instance 101(+) and a second instance 101(−) of an input analog signal. Note that in the configurations shown in FIGS. 1A-1B and 7, the input analog signal is received by the multilevel modulator 710 as an input differential signal. Additionally, the multilevel modulator 110 includes four modulator output ports (mo1, mo2, mo3, mo4). When used in the amplifier system 100 shown in FIG. 1A, the modulator output ports (mo1, mo2, mo3, mo4) are respectively coupled with the output stage input ports (si1, si3, si2, si4) of the multilevel output stage 160. The multilevel modulator 710 forms four PWM signals (LP, LM, HP, HM) by combining the input differential signal 101(+), 101(−) with a square carrier signal 702 generated internally to the multilevel modulator. When used in the amplifier system 100 shown in FIG. 1A, the formed PWM signals (LP, LM, HP, HM)—issued at the respective modulator output ports (mo1, mo2, mo3, mo4)—are used to drive the multilevel output stage 160.

(33) The multilevel modulator 710 is arranged and configured as a fully differential integrator. When no input differential signal 101(+), 101(−) is received by the multilevel modulator 710, the fully differential integrator integrates only the carrier square wave 702 to obtain a triangular wave centered on a reference voltage V.sub.REF. Comparison of the obtained triangular wave (centered on the reference voltage V.sub.REF) to the reference voltage V.sub.REF results in a PWM signal with 50% duty cycle. If an input differential signal 101(+), 101(−) is received by the multilevel modulator 710, then the fully differential integrator integrates a combination of the input differential signal and the carrier square wave 702 to obtain two triangular waves 742(+), 742(−) (having opposing signs), where the obtained triangular waves are indicative of the received input differential signal.

(34) Comparators 770a, 770b of the multilevel modulator 710 perform comparisons of the obtained triangular waves 742(+), 742(−) to the reference voltage V.sub.REF, as shown in FIG. 8, in portion 842 of graph 800. The multilevel modulator 710 generates, based on results of the comparisons, respective PWM signals (LP, LM) having differential (opposite in time) duty cycles, as shown in FIG. 8, in portion 852 of graph 800. Referring again to FIG. 7, the generated PWM signals (LP, LM) are output at respective first and second modulator output ports (mo1, mo2) of the multilevel modulator 710. When the multilevel modulator 710 is part of an amplifier system 100 that includes a multilevel output stage 260, the PWM signals (LP, LM) are used to respectively drive the first pair of HV switches and the second pair of HV switches of the multilevel output stage, when the multilevel output signals 192a, 192b—respectively issued by the first pair of HV switches and the second pair of HV switches—swing from ground to V.sub.DD, where V.sub.DD can be V.sub.BAT or V.sub.BST, as described above in connection with FIGS. 5A and 6A.

(35) However, if the triangular waves 742(+), 742(−) output by the differential integrator exceed a threshold of the comparators 770a, 770b, then the combination of comparators 770c of the multilevel modulator 710 starts comparing each of the triangular waves 742(+), 742(−) with two additional reference voltages V.sub.REF+2 kV.sub.DD and V.sub.REF−2 kV.sub.DD. Corresponding comparisons of the triangular waves 742(+), 742(−) to the noted additional reference voltages V.sub.REF±2 kV.sub.DD are shown in FIG. 8, in portion 844 of graph 800. The multilevel modulator 710 generates, based on results of the comparisons, respective PWM signals (HP, HM) having differential (opposite in time) duty cycles, as shown in FIG. 8, in portion 854 of graph 800. Referring again to FIG. 7, the generated PWM signals (HP, HM) are output at respective third and fourth modulator output ports (mo3, mo4) of the multilevel modulator 710.

(36) When the multilevel modulator 710 is part of an amplifier system 100 that includes a multilevel output stage 260, the PWM signals (HP, HM) are used to respectively drive the first pair of LV switches and the second pair of LV switches of the multilevel output stage, such that if the multilevel output signals 192a, 192b—respectively issued by the first pair of HV switches and the second pair of HV switches—swing (i) from V.sub.DD to 2V.sub.DD, then the gates of the cascoded MOSFETs of each of the first pair of LV switches and the second pair of LV switches are connected to V.sub.DD, or (ii) from ground to −V.sub.DD, then the gates of the cascoded MOSFETs of each of the first pair of LV switches and the second pair of LV switches are connected to ground. In this manner, each of the first pair of HV switches and the second pair of HV switches can safely issue respective multilevel output signals 192a, 192b that swing between +2V.sub.DD and −V.sub.DD, as shown above in graphs 192a, 192b, without causing damage to the power MOSFETs included therein.

(37) Note that the described class-D amplifier can transfer power more efficiently to a load than the conventional charge-pump implementation of the class-D amplifier shown in FIG. 9A, because the multilevel output stage 260 has smaller output resistance R.sub.OUT than the output resistance R.sub.OUT,CP of the single-level output stage shown in FIG. 9A. Charge-pump circuitry includes four switches (e.g., MOSFETs) in a bridge configuration with the fly capacitor C.sub.Fly, and the switches of the charge-pump circuitry are always ON, hence, a contribution of the charge-pump circuitry to R.sub.OUT,CP is a resistance 4R.sub.ON. Here, R.sub.ON is the series resistance of a single MOSFET in its ON state. Further, as two diagonally arranged switches of the output bridge of the conventional charge-pump implementation of the class-D amplifier are alternately always on, the contribution of the output bridge to R.sub.OUT,CP is a resistance 2R.sub.ON. Thus, the total output resistance R.sub.OUT,CP of the single-level output stage of the conventional charge-pump implementation of the class-D amplifier shown in FIG. 9A is R.sub.OUT,CP=6R.sub.ON.

(38) In contrast, the contribution to the output resistance R.sub.OUT of the multilevel output stage 260 (as shown, e.g., in FIG. 2 or FIG. 6A) varies based on an amplitude of the amplified signal V.sub.LOAD output at the output ports (outP, outM). When the amplified signal amplitude is between zero and V.sub.BAT, the output resistance of the multilevel output stage 260 is R.sub.OUT(0, V.sub.BAT)=2R.sub.ON because two diagonally arranged HV switches of the output bridge 270 are ON (to provide current to the load) and contribute a resistance 2R.sub.ON to the output resistance R.sub.OUT. Further, when the amplified signal amplitude is between V.sub.BAT and 2V.sub.BAT, the output resistance of the multilevel output stage 260 is R.sub.OUT(V.sub.BAT,2V.sub.BAT)=4R.sub.ON because (i) two diagonally arranged switches of the first boost bridge 272a are ON (to charge the first boost capacitor C.sub.BST1 of the first boost bridge) and contribute a resistance 2R.sub.ON to the output resistance R.sub.OUT, and (ii) two other switches diagonally arranged relative to the first boost capacitor C.sub.BST1 and load are ON (to deliver charge from the first boost capacitor C.sub.BST1 to the load) and contribute an additional resistance of 2R.sub.ON to the output resistance R.sub.OUT. Furthermore, when the amplified signal amplitude is between 2V.sub.BAT and 3V.sub.BAT, the output resistance of the multilevel output stage 260 is R.sub.OUT(2V.sub.BAT,3V.sub.BAT)=6R.sub.ON because (i) two diagonally arranged switches of the first boost bridge 272a are ON (to charge the first boost capacitor C.sub.BST1 of the first boost bridge) and contribute a resistance 2R.sub.ON to the output resistance R.sub.OUT, (ii) two diagonally arranged switches of the second boost bridge 272b are ON (to charge the second boost capacitor C.sub.BST2 of the second boost bridge) and contribute a resistance 2R.sub.ON to the output resistance R.sub.OUT, and (iii) two other switches diagonally arranged relative to the first boost capacitor C.sub.BST1, load and second boost capacitor C.sub.BST2 are ON (to deliver charge from the first boost capacitor and the second boost capacitor to the load) and contribute an additional resistance of 2R.sub.ON to the output resistance R.sub.OUT. In this manner, the output resistance of the multilevel output stage 260 over all amplified signal amplitudes, from zero to 3V.sub.BAT, is a weighted average:

(39) $\begin{array}{cc}\begin{array}{c}{R}_{\mathrm{OUT}}=w_1*R_{\mathrm{OUT}}\left(0,V_{\mathrm{BAT}}\right)+w_2*R_{\mathrm{OUT}}\left(V_{\mathrm{BAT}},2V_{\mathrm{BAT}}\right)+\\ w_3*R_{\mathrm{OUT}}\left(2V_{\mathrm{BAT}},3V_{\mathrm{BAT}}\right)\\ =w_1*2R_{\mathrm{ON}}+w_2*4R_{\mathrm{ON}}+w_3*6R_{\mathrm{ON}}\\ =\left(2_{w1}+4_{w2}+6_{w3}\right)R_{\mathrm{ON}}.\end{array}& \left(1\right)\end{array}$

(40) The weights w.sub.1, w.sub.2, w.sub.3 are proportional to the amount of time that the amplitude of the amplified signal is in respective ranges (0;V.sub.BAT], (V.sub.BAT,2V.sub.BAT], (2V.sub.BAT,3V.sub.BAT], and thus they are finite (non-zero), w.sub.1>0, w.sub.2>0, w.sub.3>0, and they add to 1: w.sub.1+w.sub.2+w.sub.3=1. Because the foregoing weighted average R.sub.OUT is necessarily smaller than 6R.sub.ON, the multilevel output stage 260 has smaller output resistance R.sub.OUT than the output resistance R.sub.OUT,CP=6R.sub.ON of the single-level output stage of the conventional charge-pump implementation of the class-D amplifier shown in FIG. 9A. For example, an amplified audio signal may have an amplitude less than V.sub.BAT for a portion of 90% of the total signal duration, thus, in this case, the multilevel output stage 260 has an output resistance R.sub.OUT=2R.sub.ON for 90% of the total signal duration, while the single-level output stage of the conventional charge-pump implementation of the class-D amplifier shown in FIG. 9A has an output resistance R.sub.OUT,CP=6R.sub.ON for the entire signal duration.

(41) A few embodiments have been described in detail above, and various modifications are possible. The disclosed subject matter, including the functional operations described in this specification, can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof, including system on chip (SoC) implementations, which can include one or more controllers and embedded code.

(42) While this specification contains many specifics, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

(43) Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments.

(44) Other embodiments fall within the scope of the following claims.