DML Driver

Abstract

The DML driver includes: a post driver which supplies a driving current to the LD; and a pre-driver which drives the post driver in response to a modulated signal. The pre-driver has a transistor, a peaking inductor, a peaking inductor, a group delay inhibition inductor, and a peaking capacitor.

Claims

1.-4. (canceled)

5. A DML driver comprising: a post driver configured to supply a driving current to a laser diode; and a pre-driver configured to drive the post driver in response to an inputted modulated signal, the pre-driver including: a first transistor, wherein the inputted modulated signal is configured to be input into a gate of the first transistor or a base of the first transistor; a first resistor, wherein a first end of the first resistor is connected to a first power supply voltage; a first inductor, wherein a first end of the first inductor is connected to a second end of the first resistor, wherein a second end of the first inductor is connected to a drain of the first transistor or a collector of the first transistor; a second inductor, wherein a first end of the second inductor is connected to the drain of the first transistor or the collector of the first transistor, wherein a second end of the second inductor is connected to an input terminal of the post driver; a third inductor, wherein a first end of the third inductor is connected to a source of the first transistor or an emitter of the first transistor, wherein a second end of the third inductor is connected to a second power supply voltage; and a capacitor, wherein a first end of the capacitor is connected to the source of the first transistor or the emitter of the first transistor, wherein a second end of the capacitor is connected to the second power supply voltage.

6. The DML driver according to claim 5, wherein the pre-driver further includes a second resistor between the source of the first transistor or the emitter of the first transistor and the first end of the third inductor as well as the first end of the capacitor.

7. The DML driver according to claim 5, wherein the pre-driver further includes a second resistor between the source of the first transistor and the second end of the third inductor or between the emitter of the first transistor and the second end of the third inductor.

8. The DML driver according to claim 5, wherein the pre-driver further includes a second transistor between a connection point and the drain of the first transistor or between the connection point and the collector of the first transistor, wherein the connection point is of the first inductor and the second inductor, wherein a bias voltage is configured to be input to the a gate of the second transistor or a base of the second transistor, wherein a drain of the second transistor or a collector of the second transistor is connected to the connection point, and wherein a source of the second transistor or an emitter of the second transistor is connected to the drain of the first transistor or the collector of the first transistor.

9. A method comprising: supplying, by a post driver of a DML driver, a driving current to a laser diode; and driving, by a pre-driver of the DML driver, the post driver in response to an inputted modulated signal, the pre-driver including: a first transistor, wherein the inputted modulated signal is input into a gate of the first transistor or a base of the first transistor; a first resistor, wherein a first end of the first resistor is connected to a first power supply voltage; a first inductor, wherein a first end of the first inductor is connected to a second end of the first resistor, wherein a second end of the first inductor is connected to a drain of the first transistor or a collector of the first transistor; a second inductor, wherein a first end of the second inductor is connected to the drain of the first transistor or the collector of the first transistor, wherein a second end of the second inductor is connected to an input terminal of the post driver; a third inductor, wherein a first end of the third inductor is connected to a source of the first transistor or an emitter of the first transistor, wherein a second end of the third inductor is connected to a second power supply voltage; and a capacitor, wherein a first end of the capacitor is connected to the source of the first transistor or the emitter of the first transistor, wherein a second end of the capacitor is connected to the second power supply voltage.

10. The method according to claim 9, wherein the pre-driver further includes a second resistor between the source of the first transistor or the emitter of the first transistor and the first end of the third inductor as well as the first end of the capacitor.

11. The method according to claim 9, wherein the pre-driver further includes a second resistor between the source of the first transistor and the second end of the third inductor or between the emitter of the first transistor and the second end of the third inductor.

12. The method according to claim 9, wherein the pre-driver further includes a second transistor between a connection point and the drain of the first transistor or between the connection point and the collector of the first transistor, wherein the connection point is of the first inductor and the second inductor, wherein a bias voltage is configured to be input to the a gate of the second transistor or a base of the second transistor, wherein a drain of the second transistor or a collector of the second transistor is connected to the connection point, and wherein a source of the second transistor or an emitter of the second transistor is connected to the drain of the first transistor or the collector of the first transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a circuit diagram showing a configuration of a DML driver according to a first embodiment of the present invention.

[0013] FIG. 2 is a diagram showing parasitic capacitances of a post driver and a pre-driver in FIG. 1.

[0014] FIG. 3 shows graphs showing ideal characteristics of the first embodiment of the present invention.

[0015] FIG. 4 shows a graph for explaining effect of the DML driver according to the first embodiment of the present invention.

[0016] FIG. 5 shows a graph for explaining effect of the DML driver according to the first embodiment of the present invention.

[0017] FIG. 6 is a circuit diagram showing a configuration of a DML driver according to a second embodiment of the present invention.

[0018] FIG. 7 is a circuit diagram showing a configuration of a DML driver according to a third embodiment of the present invention.

[0019] FIG. 8 is a circuit diagram showing a configuration of a DML driver according to a fourth embodiment of the present invention.

[0020] FIG. 9 shows graphs showing EO response characteristics and group delay characteristics of an LD.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

First Embodiment

[0021] Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described. FIG. 1 is a circuit diagram showing a configuration of a DML driver according to a first embodiment of the present invention. The DML driver in the present embodiment includes a post driver 2 which supplies a driving current I.sub.LD to an LD 1 and a pre-driver 3 which drives the post driver 2 in response to an inputted modulated signal Vin.

[0022] The post driver 2 includes a transistor (not shown) and is a driver capable of driving the LD 1. In embodiments of the present invention, a driver circuit having any configuration is applicable to the post driver 2.

[0023] The pre-driver 3 has a peaking function to improve a band while group delay near a relaxation oscillation frequency f.sub.r of the LD 1 is inhibited. Specifically, the pre-driver 3 includes an NMOS transistor M.sub.1, a load resistor R.sub.D, a peaking inductor L.sub.1, a group delay inhibition inductor L.sub.X, and a peaking capacitor C. The NMOS transistor M.sub.1 is an NMOS to whose gate a modulated signal Vin is inputted. The load resistor R.sub.D is a load resistor whose one end is connected to a power supply voltage Vdd (first power supply voltage). One end of the peaking inductor L.sub.1 is connected to another end of the load resistor RD and another end of the peaking inductor L.sub.1 is connected to a drain of the transistor M.sub.1. One end of the L.sub.2 is connected to the drain of the transistor M.sub.1 and another end of the L.sub.2 is connected to an input terminal of the post driver 2. One end of the group delay inhibition inductor L.sub.X is connected to a source of the transistor M.sub.1 and another end of the group delay inhibition inductor L.sub.X is connected to a ground voltage GND (a second power supply voltage lower than the first power supply voltage). One end of the peaking capacitor C.sub.X is connected to the source of the transistor M.sub.1 and another end of the peaking capacitor C.sub.X is connected to a ground voltage GND.

[0024] FIG. 2 is a diagram showing parasitic capacitances of the post driver 2 and the pre-driver 3 shown in FIG. 1. A mark C.sub.1 indicates a parasitic capacitance of the transistor M.sub.1 and a mark C.sub.2 indicates a parasitic capacitance of a transistor (not shown) of an input part of the post driver 2. In a case where the transistor M.sub.1 is an FET, the parasitic capacitance C.sub.1 is a drain-source parasitic capacitance, and in a case where the transistor M.sub.1 is a bipolar transistor, the parasitic capacitance C.sub.1 is a collector-emitter parasitic capacitance. In a case where a transconductance of the transistor M.sub.1 is defined as g.sub.m, a gain A.sub.v of the pre-driver 3 can be represented by the following Expression (1).

[00001]$\begin{array}{cc}\mathrm{Math}.1& \\ .Math.A_v\left(s\right).Math.=\frac{C_{x}s+\frac{1}{L_{x}s}}{C_{2}s+\frac{1}{L_{2}s+\frac{1}{C_{1}s+\frac{1}{R_D+L_{1}s}}}}{g}_m& \left(1\right)\end{array}$

[0025] A mark s in the Expression (1) is a Laplace operator. A part 30 in FIG. 2 which includes the load resistor R.sub.D and the peaking inductors L.sub.1 and L.sub.2 constitutes a peaking function part. In the peaking function part 30, the larger values of the load resistor R.sub.D and the peaking inductors L.sub.1 and L.sub.2 are, the larger a peaking amount is. In addition, the smaller the parasitic capacitances C.sub.1 and C.sub.2 are, the larger the peaking amount is.

[0026] A part 31 in FIG. 2 which includes the inductor L.sub.x constitutes a group delay inhibition function part. A peak of a group delay amount near the relaxation oscillation frequency f.sub.r of the LD 1 can be inhibited by the inductor L.sub.x.

[0027] A part 32 in FIG. 2 which includes the peaking capacitor C.sub.x constitutes a peaking function part in a high band. A decrease in the group delay amount of the LD 1 in the high band and a decrease in a group delay amount of the inductor L.sub.x can be inhibited by the peaking capacitor C.sub.x.

[0028] FIG. 3 shows graphs showing ideal characteristics of the present embodiment. In FIG. 3(a), 100 shows EO response characteristics of the LD 1 as a single body, 101 shows EO response characteristics of a combination of the DML driver of the present embodiment and the LD 1, and 102 shows response characteristics of an injection current (driving current) I.sub.LD to the LD 1. In addition, in FIG. 3(b), 103 shows group delay characteristics of the LD 1 as the single body and 104 shows group delay characteristics of the combination of the DML driver of the present embodiment and the LD 1.

[0029] In FIG. 3(a), the response characteristics of the injection current ILD are made up of characteristics in the individual configurations of the peaking function parts 30 and 32 and the group delay inhibition function part 31 shown in FIG. 2. In FIG. 3(a), 105 is a portion where improvement effect by the peaking function part 30 and the group delay inhibition function part 31 is exhibited and 106 is a portion where improvement effect by the peaking function parts 30 and 32 is exhibited.

[0030] The group delay inhibition function part 31 performs compensation to deal with a resonant-state peak of the EO response characteristics of the LD 1 as the single body, thereby inhibiting the group delay. In addition, the peaking function parts 30 and 32 have a peaking function by inductance and a peaking function by capacitance, respectively. As shown in FIG. 3, improving a band of the EO response characteristics by the peaking function parts 30 and 32 and the group delay inhibition function part 31 without increasing the resonant-state peak of the EO response characteristics can be expected, and inhibiting the group delay can be expected.

[0031] FIG. 4 shows a graph for explaining effect of the present embodiment, the graph showing a simulation result of the EO response characteristics of the LD 1 as the single body and a simulation result of the EO response characteristics of the combination of the DML driver of the present embodiment and the LD 1. As in FIG. 3, 100 shows the EO response characteristics of the LD 1 as the single body and 101 shows the EO response characteristics of the combination of the DML driver of the present embodiment and the LD 1. It is seen from FIG. 4 that although the EO response characteristics shown therein are slightly different from the ideal characteristics shown in FIG. 3(a), the band of the EO response characteristics can be improved by using the DML driver of the present embodiment without increasing the resonant-state peak, as compared with the EO response characteristics of the LD 1 as the single body.

[0032] FIG. 5 shows a graph for explaining effect of the present embodiment, the graph showing a simulation result of the group delay characteristics of the LD 1 as the single body and a simulation result of the group delay characteristics of the combination of the DML driver of the present embodiment and the LD 1. As in FIG. 3, 103 shows the group delay characteristics of the LD 1 as the single body and 104 shows the group delay characteristics of the combination of the DML driver of the present embodiment and the LD 1. It is seen from FIG. 5 that although the group delay characteristics shown therein are slightly different from the ideal characteristics shown in FIG. 3(b), a peak of a group delay amount near the relaxation oscillation frequency f.sub.r of the LD 1 can be inhibited by using the DML driver of embodiments of the present invention with respect to the group delay characteristics of the LD 1 as the single body and a maximum value of a group delay amount also as to the whole frequency band can be reduced.

Second Embodiment

[0033] Next, a second embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a DML driver according to the second embodiment of the present invention, and in FIG. 6, the same components as those in FIG. 1 are denoted by the same reference signs. The DML driver of the present embodiment includes a post driver 2 and a pre-driver 3a.

[0034] In the pre-driver 3a of the present embodiment, a resistor R.sub.x is inserted between the source of the transistor M.sub.1 of the pre-driver 3 of the first embodiment and one end of the inductor L.sub.x of the pre-driver 3 thereof as well as one end of the capacitor C.sub.x of the pre-driver 3 thereof. In this way, in the present embodiment, a linearization function can be added to the pre-driver 3a. In a case where the post driver 2 also has the linearization function, even when a signal Vin inputted to the pre-driver 3a is a signal, such as a four level pulse amplitude modulation (PAM4) signal and a discrete multitone (DMT) signal, for which linearity is required, it is made possible to drive an LD 1.

Third Embodiment

[0035] Next, a third embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing a configuration of a DML driver according to the third embodiment of the present invention, and in FIG. 7, the same components as those in FIG. 1 are denoted by the same reference signs. The DML driver of the present embodiment includes a post driver 2 and a pre-driver 3b.

[0036] In the pre-driver 3b of the present embodiment, a resistor R.sub.x is inserted between the source of the transistor M.sub.1 of the pre-driver 3 of the first embodiment and one end of the inductor L.sub.x of the pre-driver 3 thereof. In the present embodiment, as compared with the configuration of the second embodiment, impedance added to the source of the transistor M.sub.1 can be lowered in a high band and a gain of the driver can be increased, thereby enabling a frequency band to be improved.

Fourth Embodiment

[0037] Next, a fourth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a DML driver according to the fourth embodiment of the present invention, and in FIG. 8, the same components as those in FIG. 1 are denoted by the same reference signs. The DML driver of the present embodiment includes a post driver 2 and a pre-driver 3c.

[0038] In the pre-driver 3c of the present embodiment, an NMOS transistor M.sub.2, to whose gate a DC bias voltage Vb is inputted, whose drain is connected to a connection point of inductors L.sub.1 and L.sub.2, and whose source is connected to the drain of the transistor M.sub.1, is inserted to the pre-driver 3 of the first embodiment. It is desirable that the bias voltage Vb is set in such a way that the transistors M.sub.1 and M.sub.2 operate in a saturated region.

[0039] Since in the present embodiment, by connecting the transistors M.sub.1 and M.sub.2 in a cascode manner, mirror effect in the transistor M.sub.1 can be inhibited, frequency characteristics of the DML driver can be further improved.

[0040] Note that although in the first to fourth embodiments, the example in which the FET is used as each of the transistors M.sub.1 and M.sub.2 is shown, a bipolar transistor may be used. In a case where the bipolar transistor is used, in the above description, it is only required for the gate to be replaced with a base, for the drain to be replaced with a collector, and for the source to be replaced with an emitter.

INDUSTRIAL APPLICABILITY

[0041] Embodiments of the present invention are applicable to technology which directly modulates optical output of a laser diode.

REFERENCE SIGNS LIST

[0042] 1 Laser diode

[0043] 2 Post driver

[0044] 3, 3a, 3b, 3c Pre-driver

[0045] M.sub.1, M.sub.2 Transistor

[0046] R.sub.D, R.sub.x Resistor

[0047] L.sub.1, L.sub.2, L.sub.x Inductor

[0048] C.sub.x Capacitor

[0049] 30, 32 Peaking function part

[0050] 31 Group delay inhibition function part.