OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP

Abstract

In at least one embodiment, the optoelectronic semiconductor chip (100) comprises a semiconductor layer sequence (1) comprising a top side (2), a bottom side (3) diametrically opposite the top side (2), and an active layer (11) for generating electromagnetic radiation at a first wavelength (10), wherein the semiconductor chip (100) is free of a growth substrate for the semiconductor chip layer sequence (1). The semiconductor chip (100) further comprises a plurality of contact elements (30) which are arranged on the bottom side (3) and can be electronically controlled individually and independently from each other. The semiconductor layer sequence (1) is thereby divided into a plurality of emission regions (20) which are arranged laterally adjacent to one another and are constructed for the purpose of emitting radiation during operation. One of the contact elements (30) is thereby assigned to each emission region (20). Each emission region (20) further comprises a recess in the semiconductor layer sequence (1) which extends from the top side (2) in the direction of the active layer (11). In a top view of the top side (2), the recess of each emission region (20) is completely surrounded by a continuous path made of separating walls (21), wherein the separating walls (21) are formed from the semiconductor layer sequence (1).

Claims

1. Optoelectronic semiconductor chip comprising a semiconductor layer sequence with a top, a bottom opposite the top and an active layer for generating electromagnetic radiation of a first wavelength, wherein the semiconductor chip is free of a growth substrate for the semiconductor layer sequence, a plurality of contact elements arranged on the bottom, which are individually and mutually independently electrically activatable when operated as intended, wherein the semiconductor layer sequence is subdivided into a plurality of emission regions arranged adjacent one another in the lateral direction, which emission regions are configured to emit radiation when in operation, at least one of the contact elements is associated with each of the emission regions, each emission region comprises a recess in the semiconductor layer sequence, which extends from the top in the direction of the active layer, in plan view onto the top, the recess of each emission region is completely surrounded by a contiguous web of partitions, wherein the partitions are formed from the semiconductor layer sequence and wherein the partitions form boundaries between adjacent emission regions.

2. Optoelectronic semiconductor chip according to claim 1, wherein the recess of at least one emission region is filled at least in part with a converter material, the converter material converts the radiation of the first wavelength generated when the relevant emission region is in operation at least partly into radiation of a second wavelength different from the first wavelength, the partitions form a lateral boundary for the converter material.

3. Optoelectronic semiconductor chip according to claim 1, wherein in the region of the recesses of the emission regions, the semiconductor layer sequence has a thickness measured perpendicular to the top of at most 3 μm.

4. Optoelectronic semiconductor chip according to claim 1, wherein precisely one contact element is associated on a one-to-one basis with each emission region, the contact element belonging to an emission region is opposite the recess, the recesses of the emission regions completely cover over the associated contact elements when viewed in plan view, the lateral extents of the recesses of the emission regions differ by at most 50% from the lateral extents of the associated contact elements.

5. Optoelectronic semiconductor chip according to claim 1, wherein when viewed in plan view onto the top, the emission regions are arranged in a matrix, when viewed in plan view onto the top, the emission regions are surrounded by a grid of partitions.

6. Optoelectronic semiconductor chip according to claim 1, wherein the partitions are covered with a contiguous counter contact, which is arranged on the top of the semiconductor layer sequence and in operation serves in contacting a plurality of emission regions, the recesses of the emission regions are at least partly free of the counter contact, to operate an emission region, a voltage is applied between the counter contact and the contact element associated with the emission region.

7. Optoelectronic semiconductor chip according to claim 1, wherein the counter contact comprises a light-reflecting or light-absorbing material, the counter contact covers the partitions not only on the top but also on side faces of the partitions, such that the individual emission regions are optically separated from one another by the partitions.

8. Optoelectronic semiconductor chip according to claim 1, wherein the bottom of the semiconductor layer sequence is free of contact elements in the region of the partitions, such that in operation the active layer generates little or no radiation in the regions of the partitions.

9. Optoelectronic semiconductor chip according to claim 1, wherein a common active matrix element which serves in selective electrical activation of the individual contact elements is applied on the bottom to a plurality of contact elements.

10. Optoelectronic semiconductor chip according to claim 1, wherein the lateral extent of the recesses of the emission regions decreases from the top in the direction of the active layer, the recesses of the emission regions each have a base surface which extends parallel to the active layer.

11. Optoelectronic semiconductor chip according to claim 1, wherein the partitions taper to a point in the direction of the top when viewed from the active layer, such that a width of the partitions in the region of the top amounts to at most 1/10 of the maximum width of the partitions.

12. Optoelectronic semiconductor chip according to at least claim 6, wherein a protective layer is applied to the sides of the counter contact remote from the semiconductor layer sequence, which protective layer protects the counter contact from external influences.

13. Optoelectronic semiconductor chip according to claim 1, wherein the recesses of the emission regions have a lateral extent of between 1 μm and 300 μm, the maximum width of the partitions amounts to between 10% and 100% inclusive of the lateral extent of the recesses of the emission regions, the thickness of the semiconductor layer sequence in the region of the partitions amounts to between 5 μm and 12 μm inclusive.

14. Optoelectronic semiconductor chip according to claim 1, wherein the counter contact comprises or consists of at least one of the following materials: Ag, Au, Pt, Pd, Ni, Rh, Al, TCO; the converter material comprises or consists of at least one transparent matrix material with at least one light-converting luminescent material introduced therein, wherein the luminescent material comprises or consists of organic molecules and/or luminescent polymers and/or quantum dots; the protective layer comprises or consists of at least one of the following materials: Al.sub.2O.sub.3, SiO.sub.2, SiN.sub.x, SiO.sub.xN.sub.y, TaN.sub.x, TiO.sub.2, parylenes, PU coating materials, EP coating materials.

15. Optoelectronic semiconductor chip according to claim 1, wherein the active layer of the semiconductor layer sequence generates radiation in the blue region of the spectrum when in operation, the semiconductor chip comprises a plurality of pixel groups, wherein each pixel group comprises three emission regions arranged adjacent one another, in each pixel group a recess of a first emission region is filled with a red converter material and a recess of a second emission region is filled with a green converter material and a third emission region is free of a converter material, such that each pixel group forms a red-green-blue emitting unit, the pixel groups are arranged in a matrix on the top.

16. Method for producing an optoelectronic semiconductor chip, comprising the following steps: A) growing a semiconductor layer sequence on a growth substrate, wherein the semiconductor layer sequence comprises an active layer for generating electromagnetic radiation; B) mounting contact elements on a bottom, remote from the growth substrate, of the semiconductor layer sequence; C) applying a carrier to the bottom; D) detaching the growth substrate, wherein a top of the semiconductor layer sequence opposite the bottom is exposed; E) forming emission regions by forming recesses in the semiconductor layer sequence, wherein each recess extends from the top in the direction of the active layer, wherein partitions consisting of the semiconductor layer sequence remain around each recess, which partitions form a contiguous web completely surrounding the recess when viewed in plan view onto the top and wherein the lateral extent of the recesses of the emission regions decreases from the top in the direction of the active layer.

17. Method for producing an optoelectronic semiconductor chip according to claim 16, wherein the partitions taper to a point in the direction of the top when viewed from the active layer; in a step F) an uninterrupted, contiguous counter contact layer is applied over the entire surface of the sides of the semiconductor layer sequence remote from the carrier; subsequently, an uninterrupted, contiguous protective layer is applied over the entire surface of the sides of the counter contact layer remote from the carrier; thereafter, a directional etching method is used, in which the protective layer is etched away in the region of base surfaces of the recesses to a greater extent than in the region of side faces of the partitions, such that, after the directional etching method, the side faces are completely covered by the protective layer and the base surfaces are at least partly free of the protective layer; subsequently, a further etching method is used, in which the protective layer acts as a mask, and in which the counter contact layer is at least partially removed in the region of the base surfaces of the recesses.

18. Method for producing an optoelectronic semiconductor chip according to claim 16, wherein in a step G) the recesses in the semiconductor layer sequence are at least partly filled with a converter material using one of the following methods: inkjet printing, aerosol jetting, dispensing, screen printing.

19. Optoelectronic semiconductor chip comprising a semiconductor layer sequence with a top, a bottom opposite the top and an active layer for generating electromagnetic radiation of a first wavelength, wherein the semiconductor chip is free of a growth substrate for the semiconductor layer sequence, a plurality of contact elements arranged on the bottom, which are individually and mutually independently electrically activatable when operated as intended, wherein the semiconductor layer sequence is subdivided into a plurality of emission regions arranged adjacent one another in the lateral direction, which emission regions are configured to emit radiation when in operation, at least one of the contact elements is associated with each of the emission regions, each emission region comprises a recess in the semiconductor layer sequence, which extends from the top in the direction of the active layer, in plan view onto the top, the recess of each emission region is completely surrounded by a contiguous web of partitions, wherein the partitions are formed from the semiconductor layer sequence and wherein the partitions form boundaries between adjacent emission regions, the lateral extent of the recesses of the emission regions decreases from the top in the direction of the active layer.

Description

[0068] In the figures:

[0069] FIGS. 1 to 8 are schematic representations of exemplary embodiments of optoelectronic semiconductor chips described here,

[0070] FIGS. 9A to 9C are schematic representations of method steps of a method described here for producing an optoelectronic semiconductor chip.

[0071] FIG. 1 shows a semiconductor chip 100 with a carrier in the form of an active matrix element 6, to which a semiconductor layer sequence 1 has been applied. The semiconductor layer sequence 1 further comprises an active layer 11 for generating electromagnetic radiation of a first wavelength 10. The semiconductor layer sequence 1 is based for example on InGaAlN, while the active layer 11 is for example a pn junction. Furthermore, the semiconductor layer sequence 1 comprises a top 2, which extends parallel to the active layer 11 and which comprises the regions of the semiconductor layer sequence 1 furthest from the active layer 11. Opposite the top 2 the semiconductor layer sequence 1 comprises a bottom 3, which likewise extends parallel to the active layer 11 and likewise comprises the regions of the semiconductor layer sequence 1 furthest from the active layer 11. The bottom 3 faces the active matrix element 6.

[0072] A plurality of recesses has moreover been introduced into the semiconductor layer sequence 1, these extending from the top 2 in the direction of the active layer 11 but not piercing the active layer 11. In the present case, in the cross-sectional view shown the recesses take the form of upside-down truncated cones or pyramids, wherein a base surface 23 of each recess extends parallel to the active layer 11. The individual recesses are separated and spaced from one another in the lateral direction parallel to the active layer 11 by partitions 21. The partitions 21 here form part of the semiconductor layer sequence 1, such that the entire semiconductor chip 100 comprises a single contiguous semiconductor layer sequence 1 formed in one piece.

[0073] Side faces 22 of the partitions 21 extend obliquely to the active layer 11 and laterally define the recesses in the semiconductor layer sequence 1.

[0074] Moreover a counter contact 31, for example of Al, has been applied to plateau-like vertices of the partitions 21 in the region of the top 2, which counter contact serves in electrical contacting of the semiconductor layer sequence 1. In the present case shown in FIG. 1, the side walls 22 of the partitions 21 are free of the counter contact 31. The counter contact 31 is electrically connected laterally by way of a bonding wire to the active matrix element 6.

[0075] Between the active matrix element 6 and the bottom 3 of the semiconductor layer sequence 1, moreover, contact elements 30 are mounted in the region of the recesses. In plan view onto the top 2, the contact elements 30 are completely covered over by the recess or the base surface 23 of the recess. A single contact element 30 is associated on a one-to-one basis with each recess.

[0076] Furthermore, an insulation layer consisting for example of silicon oxide is mounted between the contact elements 30 in the region of the partitions 21. The insulation layer is preferably arranged on the bottom 3 throughout the region of the partitions 21.

[0077] Furthermore, in FIG. 1 the insulation layer terminates flush with the contact elements 30 on a side remote from the semiconductor layer sequence 1, such that the insulation layer and the contact elements 30 together form a layer with flat major faces. The active matrix element 6 is applied for example by means of a direct bonding method to one of the flat major faces.

[0078] The contact elements 30 are constructed in the example of FIG. 1 from two layers stacked on one another, wherein the layer facing the active layer 11 is a mirror layer for example of Ag. The layer of the contact element 30 remote from the active layer 11 preferably serves as a bonding layer to the active matrix element 6 and consists for example of Ni or Al or Cu.

[0079] In the example of FIG. 1 the individual contact elements 30 are electrically connected via individually activatable transistors, for example thin film transistors, to a shift register likewise arranged in the active matrix element 6. This ensures that the individual contact elements 30 may be individually and mutually independently activated or energized. As shown in FIG. 1, when a contact element 30 is activated charge carriers are injected by the contact element 30 in the direction of the active layer 11 into the semiconductor layer sequence 1. From the counter contact 31 mounted on the top 2, which serves as a common counter contact for all the contact elements 30 on the bottom 3, oppositely charged charge carriers are injected via the partitions 21 in the direction of the active layer 11. On recombination of the charge carriers in the active layer 11, radiation preferably arises only in the region around the respectively activated contact element 30. The radiation of a first wavelength 10 generated then exits from the semiconductor layer sequence 1 via the base surface 23.

[0080] In this way, the semiconductor layer sequence 1 is subdivided into a multiplicity of emission regions 20 arranged laterally adjacent one another. The emission regions 20 are regions via which electromagnetic radiation is outcoupled from the semiconductor layer sequence 1, and which are perceptible to an observer, when viewed in plan view onto the top 2, as separate picture elements or pixels. The partitions 21 with the counter contact elements 31 mounted thereon are in each case arranged between the emission regions 20. Because no or little radiation is generated in the region of the partitions 21 due to the insulation layer and because a counter contact 31 has been applied to the partitions 21, virtually no radiation exits from the semiconductor layer sequence 1 via the partitions 21. In plan view, the partitions 21 thus form a possibly dark optical boundary between adjacent emission regions 20. Furthermore, due to the configuration of the semiconductor chip 100 in FIG. 1, the lateral extent of each emission region 20 is defined by the lateral extent of the associated recess.

[0081] In FIG. 1, moreover, some of the recesses are filled with a converter material 5. The converter material 5 for example comprises luminescent organic molecules or quantum dots, which are introduced in a transparent matrix material of a silicone or acrylate. The light of the first wavelength 10 emitted in the respective recess via the base surface 23 is converted by way of the converter material 5 at least in part into light of a second wavelength 50 different from the first wavelength 10. Blue light emitted by the active layer 11 when the semiconductor chip 100 is in operation is for example converted by the converter material 5 into red or green light. The recesses serve in particular as molds for filling with the converter material 5. The partitions 21 prevent converter material 5 from overflowing into adjacent recesses.

[0082] The exemplary embodiment of FIG. 2 shows a plan view onto the top 2 of a semiconductor chip 100. The recesses in the semiconductor layer sequence 1 in the present case have a rectangular basic shape and are arranged in a regular rectangular matrix pattern. The partitions 21 between the recesses form a rectangular-mesh grid, which completely surrounds the recesses in the semiconductor layer sequence 1 in uninterrupted manner. The contact element 31 has been applied fully to the partitions 21, i.e. the contact element 31 reproduces the grid of the recesses and is likewise of uninterrupted and continuous configuration. In particular, the counter contact 31 is formed between a plurality of recesses and laterally completely surrounds the recesses.

[0083] In the example of FIG. 2 it is moreover apparent that in each case three neighboring emission regions 20 are combined into a pixel group 200. The pixel groups 200 are likewise arranged in a matrix on the top 2. In each pixel group 200 a first recess is filled with a red converter material 5 and a second recess with a green converter material 5. The third recess is free of a converter material. If the active layer 11 of the semiconductor layer sequence 1 emits blue light, for example, this is converted by the red converter material at least in part into red light and by the green converter material at least in part into green light. Blue light is emitted via the third recess. Overall, each pixel group 200 thus forms a blue-red-green emitting unit of three different colored pixels. Such a configuration results in the semiconductor chip 100 of FIG. 2 taking the form, for example, of a polychromatically emitting pixel display.

[0084] The exemplary embodiment of FIG. 3 shows a similar semiconductor chip 100 to FIG. 1. In contrast to FIG. 1, however, in FIG. 3 side walls 22 of the partitions 21 are also completely covered with the counter contact 31. The counter contact 31 in this case preferably comprises a reflective material such as Ag or Al. Radiation which exits from the semiconductor layer sequence 1 from the base surface 23 of the recesses cannot then enter an adjacent recess through the partitions 21. The completely covered partitions 21 therefore ensure a particularly high contrast ratio between adjacent emission regions 20.

[0085] Unlike in the exemplary embodiment of FIG. 3, in the exemplary embodiment of FIG. 4 each partition 21 is configured such that the partitions 21 taper to a point in the direction of the top 2 when viewed from the active layer 11. The lateral extent of the partitions 21 in the region of the top is then for example negligibly small in comparison with the maximum lateral extent of the partitions 21. In the exemplary embodiment of FIG. 4 too, the side faces 22 of the partitions 21 are completely covered with the counter contact 31.

[0086] The exemplary embodiment of FIG. 5 differs from the exemplary embodiment of FIG. 3 in that the counter contact 31 is not contacted with the active matrix element 6 by way of a bonding wire. Instead, the counter contact 31 here takes the form of a layer which projects laterally beyond the semiconductor layer sequence 1 and is guided over a side face of the semiconductor layer sequence 1 as far as the active matrix element 6. There, the counter contact 31 is connected electrically conductively with a shift register of the active matrix element 6. Unlike what is shown in FIG. 5, the counter contact 31 is insulated from the semiconductor layer sequence 1 preferably at least in the region of the side face of the semiconductor layer sequence 1 by way of an insulation layer, such that during operation no short circuit is generated in the semiconductor layer sequence 1 by the counter contact 31.

[0087] Moreover, in FIG. 5 a recess, which was free of a converter material 5 in the previous exemplary embodiments, has now been filled with a transparent filler material. When operated as intended, the transparent filler material does not convert the light emitted by the active layer 11 or does so only to a very limited extent. The transparent filler material here serves for example to protect the semiconductor layer sequence 1 from external influences in the region of the recesses. The transparent filler material may be the same material as is also used for the above-stated transparent matrix material.

[0088] Unlike in the exemplary embodiment of FIG. 5, in the exemplary embodiment of FIG. 6 a protective layer 7 has additionally been applied to the semiconductor layer sequence 1. The protective layer 7 is here at least in part in direct contact with the semiconductor layer sequence 1 in the region of the recesses and has been arranged between the semiconductor layer sequence 1 and the converter material 5. For example, the protective layer 7 completely covers the base surfaces 23 of the recesses. Moreover, the protective layer 7 has also been applied to the side walls 22 and to the top of the partitions 21. The protective layer 7 then preferably completely covers over the counter contact 31 applied to the partitions 21. The protective layer 7 protects the counter contact 31 from external influences, in particular from oxidation or from ingress of moisture. In FIG. 6 the protective layer 7 is configured for example as a contiguous, uninterrupted protective layer 7 applied over the entire surface.

[0089] As in FIG. 6, in the exemplary embodiment of FIG. 7 each partition 21 is completely covered by the protective layer 7.

[0090] However, in FIG. 7 the base surfaces 23 of the recesses are free of the protective layer 7. Such a configuration may be achieved, for example, in that prior to filling of the recesses with the converter material 5 the protective layer 7 is removed in the region of the recesses using an etching method.

[0091] In FIG. 8 the protective layer 7 is not arranged, as in the exemplary embodiments of FIG. 6, between the converter material 5 and the semiconductor layer sequence 1, but rather the protective layer 7 is here applied as a potting compound over the entire semiconductor layer sequence 1. The protective layer 7 is thus arranged on the side of the converter material 5 remote from the active layer 11.

[0092] In particular, the protective layer 7 completely covers over all the recesses, all the partitions 21 and all the side faces of the semiconductor layer sequence 1.

[0093] FIG. 9A shows a method step for producing a semiconductor chip 100 described here. In the method step a semiconductor layer sequence 11 has already been applied to an active matrix element 6, which is not the growth substrate for the semiconductor layer sequence 1. Furthermore, recesses have already been introduced from the top 2 into the semiconductor layer sequence 1 for example by way of an etching method. The recesses have here been introduced in such a way that the remaining partitions 21, which completely surround the recesses, have a cross-sectional shape that tapers to a point. Furthermore, a contiguous, uninterrupted counter contact layer 310 has already been applied to the side of the semiconductor layer sequence 1 remote from the active matrix element 6 over the entire surface of the semiconductor layer sequence 1. The counter contact layer 310 completely covers the base surfaces 23 of the recesses and all the side faces 22 of the partitions 21. Furthermore, a protective layer 7 has been applied to the side of the counter contact layer 310 remote from the active matrix element 6, which protective layer is likewise contiguous and uninterrupted and has been applied over the entire surface of the counter contact layer 310. The protective layer 7 consists for example of a silicon oxide, such as SiO.sub.2, while the counter contact layer 310 consists for example of Ag.

[0094] FIG. 9A further shows how the protective layer 7 is treated with a directional etching method 70, such as reactive-ion etching, from a side remote from the active matrix element 6. The directional etching method 70 allows the protective layer 7 to be removed to a greater extent in the region of the base surface 23 of the recesses than on the side faces 22 of the partitions 21.

[0095] A possible result of this directional etching method 70 is shown in FIG. 9B. In FIG. 9B the protective layer 7 has been completely removed in the region of the base surfaces 23 of the recesses. Since the side faces 22 extend at an angle other than 90° to the main etching direction of the directional etching method 70, it is possible for the protective layer 7 not to be simultaneously completely removed in the region of the side faces 22. The side faces 22 of the partitions 21 are thus still completely covered over by the protective layer 7.

[0096] FIG. 9B moreover shows how a further etching method 80, for example a wet chemical etching method, is carried out from a side remote from the active matrix element 6.

[0097] In the etching method 80 the protective layer 7 on the side walls 22 now serves as a mask structure, which is barely or only slightly attacked by the further etching method 80. To this end, the counter contact layer 310 is now partially or completely removed by the further etching method 80 in the region of the recesses 23 which is free of the protective layer 7.

[0098] The result of this further etching method 80 is shown in FIG. 9C, in which the base surfaces 23 of the recesses are completely free both of the counter contact layer 310 and of the protective layer 7. The protective layer 7 and the counter contact layer 310 remain solely on the side walls 22 of the partitions 21.

The method depicted in FIGS. 9A to 9C thus allows the partitions 21 to be provided with a common patterned counter contact 31, without complex mask forming and lithography methods being needed to pattern the counter contact 31. Instead, the method here is a self-adjusting method, which makes use of the fact that the partitions 21 taper to a point.

[0099] The invention described here is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly listed in the claims or exemplary embodiments.

[0100] This patent application claims priority from German patent application 10 2014 112 551.7, the disclosure content of which is hereby included by reference.

LIST OF REFERENCE SIGNS

[0101] 1 Semiconductor layer sequence [0102] 2 Top [0103] 3 Bottom [0104] 5 Converter material [0105] 6 Active matrix element [0106] 7 Protective layer [0107] 10 Radiation of a first wavelength [0108] 11 Active layer [0109] 20 Emission region [0110] 21 Partition [0111] 22 Side faces of the partition 21 [0112] 23 Base surface of the recess [0113] 30 Contact element [0114] 31 Counter contact [0115] 50 Radiation of a second wavelength [0116] 100 Semiconductor chip [0117] 200 Pixel group